Rev 2304 | Rev 2326 | Go to most recent revision | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2304 | Rev 2318 | ||
---|---|---|---|
1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | #include <panic.h> |
34 | #include <panic.h> |
35 | #include <arch/exception.h> |
35 | #include <arch/exception.h> |
36 | #include <arch/debug_print/print.h> |
36 | #include <arch/debug_print/print.h> |
37 | #include <arch/mm/page_fault.h> |
37 | #include <arch/mm/page_fault.h> |
38 | #include <mm/as.h> |
38 | #include <mm/as.h> |
39 | #include <genarch/mm/page_pt.h> |
39 | #include <genarch/mm/page_pt.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | 42 | ||
43 | 43 | ||
44 | /** Returns value stored in fault status register. |
44 | /** Returns value stored in fault status register. |
45 | * |
45 | * |
46 | * \return Value stored in CP15 fault status register (FSR). |
46 | * \return Value stored in CP15 fault status register (FSR). |
47 | */ |
47 | */ |
48 | static inline fault_status_t read_fault_status_register(void) |
48 | static inline fault_status_t read_fault_status_register(void) |
49 | { |
49 | { |
50 | fault_status_union_t fsu; |
50 | fault_status_union_t fsu; |
51 | 51 | ||
52 | // fault adress is stored in CP15 register 5 |
52 | // fault adress is stored in CP15 register 5 |
53 | asm volatile ( |
53 | asm volatile ( |
54 | "mrc p15, 0, %0, c5, c0, 0" |
54 | "mrc p15, 0, %0, c5, c0, 0" |
55 | : "=r"(fsu.dummy) |
55 | : "=r"(fsu.dummy) |
56 | ); |
56 | ); |
57 | return fsu.fs; |
57 | return fsu.fs; |
58 | } |
58 | } |
59 | 59 | ||
60 | 60 | ||
61 | /** Returns FAR (fault address register) content. |
61 | /** Returns FAR (fault address register) content. |
62 | * |
62 | * |
63 | * \return FAR (fault address register) content (address that caused a page fault) |
63 | * \return FAR (fault address register) content (address that caused a page fault) |
64 | */ |
64 | */ |
65 | static inline uintptr_t read_fault_address_register(void) |
65 | static inline uintptr_t read_fault_address_register(void) |
66 | { |
66 | { |
67 | uintptr_t ret; |
67 | uintptr_t ret; |
68 | 68 | ||
69 | // fault adress is stored in CP15 register 6 |
69 | // fault adress is stored in CP15 register 6 |
70 | asm volatile ( |
70 | asm volatile ( |
71 | "mrc p15, 0, %0, c6, c0, 0" |
71 | "mrc p15, 0, %0, c6, c0, 0" |
72 | : "=r"(ret) |
72 | : "=r"(ret) |
73 | ); |
73 | ); |
74 | return ret; |
74 | return ret; |
75 | } |
75 | } |
76 | 76 | ||
77 | 77 | ||
78 | /** Decides whether the instructions is load/store or not. |
78 | /** Decides whether the instructions is load/store or not. |
79 | * |
79 | * |
80 | * \param instr Instruction |
80 | * \param instr Instruction |
81 | * |
81 | * |
82 | * \return true when instruction is load/store, false otherwise |
82 | * \return true when instruction is load/store, false otherwise |
83 | */ |
83 | */ |
84 | static inline bool is_load_store_instruction(instruction_t instr) |
84 | static inline bool is_load_store_instruction(instruction_t instr) |
85 | { |
85 | { |
86 | // load store immediate offset |
86 | // load store immediate offset |
87 | if (instr.type == 0x2) { |
87 | if (instr.type == 0x2) { |
88 | return true; |
88 | return true; |
89 | } |
89 | } |
90 | 90 | ||
91 | // load store register offset |
91 | // load store register offset |
92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
93 | return true; |
93 | return true; |
94 | } |
94 | } |
95 | 95 | ||
96 | // load store multiple |
96 | // load store multiple |
97 | if (instr.type == 0x4) { |
97 | if (instr.type == 0x4) { |
98 | return true; |
98 | return true; |
99 | } |
99 | } |
100 | 100 | ||
101 | // coprocessor load/store |
101 | // coprocessor load/store |
102 | if (instr.type == 0x6) { |
102 | if (instr.type == 0x6) { |
103 | return true; |
103 | return true; |
104 | } |
104 | } |
105 | 105 | ||
106 | return false; |
106 | return false; |
107 | } |
107 | } |
108 | 108 | ||
109 | 109 | ||
110 | /** Decides whether the instructions is swap or not. |
110 | /** Decides whether the instructions is swap or not. |
111 | * |
111 | * |
112 | * \param instr Instruction |
112 | * \param instr Instruction |
113 | * |
113 | * |
114 | * \return true when instruction is swap, false otherwise |
114 | * \return true when instruction is swap, false otherwise |
115 | */ |
115 | */ |
116 | static inline bool is_swap_instruction(instruction_t instr) |
116 | static inline bool is_swap_instruction(instruction_t instr) |
117 | { |
117 | { |
118 | // swap, swapb instruction |
118 | // swap, swapb instruction |
119 | if (instr.type == 0x0 && |
119 | if (instr.type == 0x0 && |
120 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
120 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
121 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
121 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
122 | return true; |
122 | return true; |
123 | } |
123 | } |
124 | 124 | ||
125 | return false; |
125 | return false; |
126 | } |
126 | } |
127 | 127 | ||
128 | 128 | ||
129 | /** Decides whether read or write into memory is requested. |
129 | /** Decides whether read or write into memory is requested. |
130 | * |
130 | * |
131 | * \param instr_addr Address of instruction which tries to access memory |
131 | * \param instr_addr Address of instruction which tries to access memory |
132 | * \param badvaddr Virtual address the instruction tries to access |
132 | * \param badvaddr Virtual address the instruction tries to access |
133 | * |
133 | * |
134 | * \return Type of access into memmory |
134 | * \return Type of access into memmory |
135 | * \note Returns #PF_ACESS_EXEC if no memory access is requested |
135 | * \note Returns #PF_ACESS_EXEC if no memory access is requested |
136 | */ |
136 | */ |
137 | //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC |
- | |
138 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
137 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
139 | { |
138 | { |
140 | instruction_union_t instr_union; |
139 | instruction_union_t instr_union; |
141 | instr_union.pc = instr_addr; |
140 | instr_union.pc = instr_addr; |
142 | 141 | ||
143 | instruction_t instr = *(instr_union.instr); |
142 | instruction_t instr = *(instr_union.instr); |
144 | 143 | ||
145 | // undefined instructions |
144 | // undefined instructions |
146 | if (instr.condition == 0xf) { |
145 | if (instr.condition == 0xf) { |
147 | panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)", |
146 | panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)", |
148 | instr, badvaddr); |
147 | instr, badvaddr); |
149 | return PF_ACCESS_EXEC; |
148 | return PF_ACCESS_EXEC; |
150 | } |
149 | } |
151 | 150 | ||
152 | // load store instructions |
151 | // load store instructions |
153 | if (is_load_store_instruction(instr)) { |
152 | if (is_load_store_instruction(instr)) { |
154 | if (instr.access == 1) { |
153 | if (instr.access == 1) { |
155 | return PF_ACCESS_READ; |
154 | return PF_ACCESS_READ; |
156 | } else { |
155 | } else { |
157 | return PF_ACCESS_WRITE; |
156 | return PF_ACCESS_WRITE; |
158 | } |
157 | } |
159 | } |
158 | } |
160 | 159 | ||
161 | // swap, swpb instruction |
160 | // swap, swpb instruction |
162 | if (is_swap_instruction(instr)) { |
161 | if (is_swap_instruction(instr)) { |
163 | /* Swap instructions make read and write in one step. |
162 | /* Swap instructions make read and write in one step. |
164 | * Type of access that caused exception have to page tables |
163 | * Type of access that caused exception have to page tables |
165 | * and access rights. |
164 | * and access rights. |
166 | */ |
165 | */ |
167 | //TODO: ALF!!!!! cann't use AS asi is define as THE->as and THE structure is |
- | |
168 | //sored after stack_base of current thread |
- | |
169 | //but now ... in exception we have separate stacks <==> different |
- | |
170 | //stack_pointer ... so AS contains nonsence data |
- | |
171 | //same case as_page_fault .... it's nessesary to solve "stack" problem |
- | |
172 | 166 | ||
173 | pte_level1_t* pte = (pte_level1_t*) |
167 | pte_level1_t* pte = (pte_level1_t*) |
174 | pt_mapping_operations.mapping_find(AS, badvaddr); |
168 | pt_mapping_operations.mapping_find(AS, badvaddr); |
175 | 169 | ||
176 | ASSERT(pte); |
170 | if ( pte == NULL ) { |
- | 171 | return PF_ACCESS_READ; |
|
- | 172 | } |
|
177 | 173 | ||
178 | /* check if read possible |
174 | /* check if read possible |
179 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
175 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
180 | if ( !PTE_PRESENT(pte) ) { |
176 | if ( !PTE_PRESENT(pte) ) { |
181 | return PF_ACCESS_READ; |
177 | return PF_ACCESS_READ; |
182 | } |
178 | } |
183 | 179 | ||
184 | if ( !PTE_WRITABLE(pte) ) { |
180 | if ( !PTE_WRITABLE(pte) ) { |
185 | return PF_ACCESS_WRITE; |
181 | return PF_ACCESS_WRITE; |
186 | } else { |
182 | } else { |
187 | // badvaddr is present readable and writeable but error occured ... why? |
183 | // badvaddr is present readable and writeable but error occured ... why? |
188 | panic("page_fault - swap instruction, but address readable and writeable" |
184 | panic("page_fault - swap instruction, but address readable and writeable" |
189 | "(instr_code:%X, badvaddr:%X)", instr, badvaddr); |
185 | "(instr_code:%X, badvaddr:%X)", instr, badvaddr); |
190 | } |
186 | } |
191 | } |
187 | } |
192 | 188 | ||
193 | panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)", |
189 | panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)", |
194 | instr, badvaddr); |
190 | instr, badvaddr); |
195 | 191 | ||
196 | return PF_ACCESS_EXEC; |
192 | return PF_ACCESS_EXEC; |
197 | } |
193 | } |
198 | 194 | ||
199 | /** Handles "data abort" exception (load or store at invalid address). |
195 | /** Handles "data abort" exception (load or store at invalid address). |
200 | * |
196 | * |
201 | * \param exc_no exception number |
197 | * \param exc_no exception number |
202 | * \param istate CPU state when exception occured |
198 | * \param istate CPU state when exception occured |
203 | */ |
199 | */ |
204 | void data_abort(int exc_no, istate_t *istate) |
200 | void data_abort(int exc_no, istate_t *istate) |
205 | { |
201 | { |
206 | fault_status_t fsr = read_fault_status_register(); |
202 | fault_status_t fsr = read_fault_status_register(); |
207 | uintptr_t badvaddr = read_fault_address_register(); |
203 | uintptr_t badvaddr = read_fault_address_register(); |
208 | 204 | ||
209 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
205 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
210 | 206 | ||
211 | int ret = as_page_fault(badvaddr, access, istate); |
207 | int ret = as_page_fault(badvaddr, access, istate); |
212 | 208 | ||
213 | if (ret == AS_PF_FAULT) { |
209 | if (ret == AS_PF_FAULT) { |
214 | print_istate(istate); |
210 | print_istate(istate); |
215 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n", |
211 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n", |
216 | istate->pc, badvaddr, fsr.status, fsr, access); |
212 | istate->pc, badvaddr, fsr.status, fsr, access); |
217 | 213 | ||
218 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
214 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
219 | panic("page fault\n"); |
215 | panic("page fault\n"); |
220 | } |
216 | } |
221 | } |
217 | } |
222 | 218 | ||
223 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
219 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
224 | * |
220 | * |
225 | * \param exc_no exception number |
221 | * \param exc_no exception number |
226 | * \param istate CPU state when exception occured |
222 | * \param istate CPU state when exception occured |
227 | */ |
223 | */ |
228 | void prefetch_abort(int exc_no, istate_t *istate) |
224 | void prefetch_abort(int exc_no, istate_t *istate) |
229 | { |
225 | { |
230 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
226 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
231 | 227 | ||
232 | if (ret == AS_PF_FAULT) { |
228 | if (ret == AS_PF_FAULT) { |
233 | dprintf("prefetch_abort\n"); |
229 | dprintf("prefetch_abort\n"); |
234 | print_istate(istate); |
230 | print_istate(istate); |
235 | panic("page fault - prefetch_abort at address: %x\n", istate->pc); |
231 | panic("page fault - prefetch_abort at address: %x\n", istate->pc); |
236 | } |
232 | } |
237 | } |
233 | } |
238 | 234 | ||
239 | /** @} |
235 | /** @} |
240 | */ |
236 | */ |
241 | 237 | ||
242 | 238 |