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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Exception handlers and exception initialization routines. |
33 | * @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/memstr.h> |
37 | #include <arch/memstr.h> |
38 | #include <arch/regutils.h> |
38 | #include <arch/regutils.h> |
39 | #include <interrupt.h> |
39 | #include <interrupt.h> |
40 | #include <arch/mm/page_fault.h> |
40 | #include <arch/mm/page_fault.h> |
41 | #include <arch/barrier.h> |
41 | #include <arch/barrier.h> |
42 | #include <arch/drivers/gxemul.h> |
- | |
43 | #include <print.h> |
42 | #include <print.h> |
44 | #include <syscall/syscall.h> |
43 | #include <syscall/syscall.h> |
45 | 44 | ||
- | 45 | #ifdef MACHINE_testarm |
|
- | 46 | #include <arch/mach/testarm/testarm.h> |
|
- | 47 | #endif |
|
- | 48 | ||
- | 49 | #ifdef MACHINE_integratorcp |
|
- | 50 | #include <arch/mach/integratorcp/integratorcp.h> |
|
- | 51 | #endif |
|
- | 52 | ||
46 | /** Offset used in calculation of exception handler's relative address. |
53 | /** Offset used in calculation of exception handler's relative address. |
47 | * |
54 | * |
48 | * @see install_handler() |
55 | * @see install_handler() |
49 | */ |
56 | */ |
50 | #define PREFETCH_OFFSET 0x8 |
57 | #define PREFETCH_OFFSET 0x8 |
51 | 58 | ||
52 | /** LDR instruction's code */ |
59 | /** LDR instruction's code */ |
53 | #define LDR_OPCODE 0xe59ff000 |
60 | #define LDR_OPCODE 0xe59ff000 |
54 | 61 | ||
55 | /** Number of exception vectors. */ |
62 | /** Number of exception vectors. */ |
56 | #define EXC_VECTORS 8 |
63 | #define EXC_VECTORS 8 |
57 | 64 | ||
58 | /** Size of memory block occupied by exception vectors. */ |
65 | /** Size of memory block occupied by exception vectors. */ |
59 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
66 | #define EXC_VECTORS_SIZE (EXC_VECTORS * 4) |
60 | 67 | ||
61 | /** Switches to kernel stack and saves all registers there. |
- | |
62 | * |
- | |
63 | * Temporary exception stack is used to save a few registers |
- | |
64 | * before stack switch takes place. |
- | |
65 | * |
- | |
66 | */ |
- | |
67 | inline static void setup_stack_and_save_regs() |
- | |
68 | { |
- | |
69 | asm volatile ( |
- | |
70 | "ldr r13, =exc_stack\n" |
- | |
71 | "stmfd r13!, {r0}\n" |
- | |
72 | "mrs r0, spsr\n" |
- | |
73 | "and r0, r0, #0x1f\n" |
- | |
74 | "cmp r0, #0x10\n" |
- | |
75 | "bne 1f\n" |
- | |
76 | - | ||
77 | /* prev mode was usermode */ |
- | |
78 | "ldmfd r13!, {r0}\n" |
- | |
79 | "ldr r13, =supervisor_sp\n" |
- | |
80 | "ldr r13, [r13]\n" |
- | |
81 | "stmfd r13!, {lr}\n" |
- | |
82 | "stmfd r13!, {r0-r12}\n" |
- | |
83 | "stmfd r13!, {r13, lr}^\n" |
- | |
84 | "mrs r0, spsr\n" |
- | |
85 | "stmfd r13!, {r0}\n" |
- | |
86 | "b 2f\n" |
- | |
87 | - | ||
88 | /* mode was not usermode */ |
- | |
89 | "1:\n" |
- | |
90 | "stmfd r13!, {r1, r2, r3}\n" |
- | |
91 | "mrs r1, cpsr\n" |
- | |
92 | "mov r2, lr\n" |
- | |
93 | "bic r1, r1, #0x1f\n" |
- | |
94 | "orr r1, r1, r0\n" |
- | |
95 | "mrs r0, cpsr\n" |
- | |
96 | "msr cpsr_c, r1\n" |
- | |
97 | - | ||
98 | "mov r3, r13\n" |
- | |
99 | "stmfd r13!, {r2}\n" |
- | |
100 | "mov r2, lr\n" |
- | |
101 | "stmfd r13!, {r4-r12}\n" |
- | |
102 | "mov r1, r13\n" |
- | |
103 | - | ||
104 | /* the following two lines are for debugging */ |
- | |
105 | "mov sp, #0\n" |
- | |
106 | "mov lr, #0\n" |
- | |
107 | "msr cpsr_c, r0\n" |
- | |
108 | - | ||
109 | "ldmfd r13!, {r4, r5, r6, r7}\n" |
- | |
110 | "stmfd r1!, {r4, r5, r6}\n" |
- | |
111 | "stmfd r1!, {r7}\n" |
- | |
112 | "stmfd r1!, {r2}\n" |
- | |
113 | "stmfd r1!, {r3}\n" |
- | |
114 | "mrs r0, spsr\n" |
- | |
115 | "stmfd r1!, {r0}\n" |
- | |
116 | "mov r13, r1\n" |
- | |
117 | - | ||
118 | "2:\n" |
- | |
119 | ); |
- | |
120 | } |
- | |
121 | - | ||
122 | /** Returns from exception mode. |
- | |
123 | * |
- | |
124 | * Previously saved state of registers (including control register) |
- | |
125 | * is restored from the stack. |
- | |
126 | */ |
- | |
127 | inline static void load_regs() |
- | |
128 | { |
- | |
129 | asm volatile( |
- | |
130 | "ldmfd r13!, {r0} \n" |
- | |
131 | "msr spsr, r0 \n" |
- | |
132 | "and r0, r0, #0x1f \n" |
- | |
133 | "cmp r0, #0x10 \n" |
- | |
134 | "bne 1f \n" |
- | |
135 | - | ||
136 | /* return to user mode */ |
- | |
137 | "ldmfd r13!, {r13, lr}^ \n" |
- | |
138 | "b 2f \n" |
- | |
139 | - | ||
140 | /* return to non-user mode */ |
- | |
141 | "1:\n" |
- | |
142 | "ldmfd r13!, {r1, r2} \n" |
- | |
143 | "mrs r3, cpsr \n" |
- | |
144 | "bic r3, r3, #0x1f \n" |
- | |
145 | "orr r3, r3, r0 \n" |
- | |
146 | "mrs r0, cpsr \n" |
- | |
147 | "msr cpsr_c, r3 \n" |
- | |
148 | - | ||
149 | "mov r13, r1 \n" |
- | |
150 | "mov lr, r2 \n" |
- | |
151 | "msr cpsr_c, r0 \n" |
- | |
152 | - | ||
153 | /* actual return */ |
- | |
154 | "2:\n" |
- | |
155 | "ldmfd r13, {r0-r12, pc}^\n" |
- | |
156 | ); |
- | |
157 | } |
- | |
158 | - | ||
159 | - | ||
160 | /** Switch CPU to mode in which interrupts are serviced (currently it |
- | |
161 | * is Undefined mode). |
- | |
162 | * |
- | |
163 | * The default mode for interrupt servicing (Interrupt Mode) |
- | |
164 | * can not be used because of nested interrupts (which can occur |
- | |
165 | * because interrupts are enabled in higher levels of interrupt handler). |
- | |
166 | */ |
- | |
167 | inline static void switch_to_irq_servicing_mode() |
- | |
168 | { |
- | |
169 | /* switch to Undefined mode */ |
- | |
170 | asm volatile( |
- | |
171 | /* save regs used during switching */ |
- | |
172 | "stmfd sp!, {r0-r3} \n" |
- | |
173 | - | ||
174 | /* save stack pointer and link register to r1, r2 */ |
- | |
175 | "mov r1, sp \n" |
- | |
176 | "mov r2, lr \n" |
- | |
177 | - | ||
178 | /* mode switch */ |
- | |
179 | "mrs r0, cpsr \n" |
- | |
180 | "bic r0, r0, #0x1f \n" |
- | |
181 | "orr r0, r0, #0x1b \n" |
- | |
182 | "msr cpsr_c, r0 \n" |
- | |
183 | - | ||
184 | /* restore saved sp and lr */ |
- | |
185 | "mov sp, r1 \n" |
- | |
186 | "mov lr, r2 \n" |
- | |
187 | - | ||
188 | /* restore original regs */ |
- | |
189 | "ldmfd sp!, {r0-r3} \n" |
- | |
190 | ); |
- | |
191 | } |
- | |
192 | - | ||
193 | /** Calls exception dispatch routine. */ |
- | |
194 | #define CALL_EXC_DISPATCH(exception) \ |
- | |
195 | asm volatile ( \ |
- | |
196 | "mov r0, %[exc]\n" \ |
- | |
197 | "mov r1, r13\n" \ |
- | |
198 | "bl exc_dispatch\n" \ |
- | |
199 | :: [exc] "i" (exception) \ |
- | |
200 | );\ |
- | |
201 | - | ||
202 | /** General exception handler. |
- | |
203 | * |
- | |
204 | * Stores registers, dispatches the exception, |
- | |
205 | * and finally restores registers and returns from exception processing. |
- | |
206 | * |
- | |
207 | * @param exception Exception number. |
- | |
208 | */ |
- | |
209 | #define PROCESS_EXCEPTION(exception) \ |
- | |
210 | setup_stack_and_save_regs(); \ |
- | |
211 | CALL_EXC_DISPATCH(exception) \ |
- | |
212 | load_regs(); |
- | |
213 | - | ||
214 | /** Updates specified exception vector to jump to given handler. |
68 | /** Updates specified exception vector to jump to given handler. |
215 | * |
69 | * |
216 | * Addresses of handlers are stored in memory following exception vectors. |
70 | * Addresses of handlers are stored in memory following exception vectors. |
217 | */ |
71 | */ |
218 | static void install_handler(unsigned handler_addr, unsigned *vector) |
72 | static void install_handler(unsigned handler_addr, unsigned *vector) |
219 | { |
73 | { |
220 | /* relative address (related to exc. vector) of the word |
74 | /* relative address (related to exc. vector) of the word |
221 | * where handler's address is stored |
75 | * where handler's address is stored |
222 | */ |
76 | */ |
223 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
77 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - |
224 | PREFETCH_OFFSET; |
78 | PREFETCH_OFFSET; |
225 | 79 | ||
226 | /* make it LDR instruction and store at exception vector */ |
80 | /* make it LDR instruction and store at exception vector */ |
227 | *vector = handler_address_ptr | LDR_OPCODE; |
81 | *vector = handler_address_ptr | LDR_OPCODE; |
228 | smc_coherence(*vector); |
82 | smc_coherence(*vector); |
229 | 83 | ||
230 | /* store handler's address */ |
84 | /* store handler's address */ |
231 | *(vector + EXC_VECTORS) = handler_addr; |
85 | *(vector + EXC_VECTORS) = handler_addr; |
232 | 86 | ||
233 | } |
87 | } |
234 | 88 | ||
235 | /** Low-level Reset Exception handler. */ |
- | |
236 | static void reset_exception_entry(void) |
- | |
237 | { |
- | |
238 | PROCESS_EXCEPTION(EXC_RESET); |
- | |
239 | } |
- | |
240 | - | ||
241 | /** Low-level Software Interrupt Exception handler. */ |
- | |
242 | static void swi_exception_entry(void) |
- | |
243 | { |
- | |
244 | PROCESS_EXCEPTION(EXC_SWI); |
- | |
245 | } |
- | |
246 | - | ||
247 | /** Low-level Undefined Instruction Exception handler. */ |
- | |
248 | static void undef_instr_exception_entry(void) |
- | |
249 | { |
- | |
250 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
- | |
251 | } |
- | |
252 | - | ||
253 | /** Low-level Fast Interrupt Exception handler. */ |
- | |
254 | static void fiq_exception_entry(void) |
- | |
255 | { |
- | |
256 | PROCESS_EXCEPTION(EXC_FIQ); |
- | |
257 | } |
- | |
258 | - | ||
259 | /** Low-level Prefetch Abort Exception handler. */ |
- | |
260 | static void prefetch_abort_exception_entry(void) |
- | |
261 | { |
- | |
262 | asm volatile ( |
- | |
263 | "sub lr, lr, #4" |
- | |
264 | ); |
- | |
265 | - | ||
266 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
- | |
267 | } |
- | |
268 | - | ||
269 | /** Low-level Data Abort Exception handler. */ |
- | |
270 | static void data_abort_exception_entry(void) |
- | |
271 | { |
- | |
272 | asm volatile ( |
- | |
273 | "sub lr, lr, #8" |
- | |
274 | ); |
- | |
275 | - | ||
276 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
- | |
277 | } |
- | |
278 | - | ||
279 | /** Low-level Interrupt Exception handler. |
- | |
280 | * |
- | |
281 | * CPU is switched to Undefined mode before further interrupt processing |
- | |
282 | * because of possible occurence of nested interrupt exception, which |
- | |
283 | * would overwrite (and thus spoil) stack pointer. |
- | |
284 | */ |
- | |
285 | static void irq_exception_entry(void) |
- | |
286 | { |
- | |
287 | asm volatile ( |
- | |
288 | "sub lr, lr, #4" |
- | |
289 | ); |
- | |
290 | - | ||
291 | setup_stack_and_save_regs(); |
- | |
292 | - | ||
293 | switch_to_irq_servicing_mode(); |
- | |
294 | - | ||
295 | CALL_EXC_DISPATCH(EXC_IRQ) |
- | |
296 | - | ||
297 | load_regs(); |
- | |
298 | } |
- | |
299 | - | ||
300 | /** Software Interrupt handler. |
89 | /** Software Interrupt handler. |
301 | * |
90 | * |
302 | * Dispatches the syscall. |
91 | * Dispatches the syscall. |
303 | */ |
92 | */ |
304 | static void swi_exception(int exc_no, istate_t *istate) |
93 | static void swi_exception(int exc_no, istate_t *istate) |
305 | { |
94 | { |
306 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
95 | istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2, |
307 | istate->r3, istate->r4, istate->r5, istate->r6); |
96 | istate->r3, istate->r4, istate->r5, istate->r6); |
308 | } |
97 | } |
309 | 98 | ||
310 | /** Returns the mask of active interrupts. */ |
- | |
311 | static inline uint32_t gxemul_irqc_get_sources(void) |
- | |
312 | { |
- | |
313 | return *((uint32_t *) gxemul_irqc); |
- | |
314 | } |
- | |
315 | - | ||
316 | /** Interrupt Exception handler. |
- | |
317 | * |
- | |
318 | * Determines the sources of interrupt and calls their handlers. |
- | |
319 | */ |
- | |
320 | static void irq_exception(int exc_no, istate_t *istate) |
- | |
321 | { |
- | |
322 | uint32_t sources = gxemul_irqc_get_sources(); |
- | |
323 | unsigned int i; |
- | |
324 | - | ||
325 | for (i = 0; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
- | |
326 | if (sources & (1 << i)) { |
- | |
327 | irq_t *irq = irq_dispatch_and_lock(i); |
- | |
328 | if (irq) { |
- | |
329 | /* The IRQ handler was found. */ |
- | |
330 | irq->handler(irq); |
- | |
331 | spinlock_unlock(&irq->lock); |
- | |
332 | } else { |
- | |
333 | /* Spurious interrupt.*/ |
- | |
334 | printf("cpu%d: spurious interrupt (inum=%d)\n", |
- | |
335 | CPU->id, i); |
- | |
336 | } |
- | |
337 | } |
- | |
338 | } |
- | |
339 | } |
- | |
340 | - | ||
341 | /** Fills exception vectors with appropriate exception handlers. */ |
99 | /** Fills exception vectors with appropriate exception handlers. */ |
342 | void install_exception_handlers(void) |
100 | void install_exception_handlers(void) |
343 | { |
101 | { |
344 | install_handler((unsigned) reset_exception_entry, |
102 | install_handler((unsigned) reset_exception_entry, |
345 | (unsigned *) EXC_RESET_VEC); |
103 | (unsigned *) EXC_RESET_VEC); |
346 | 104 | ||
347 | install_handler((unsigned) undef_instr_exception_entry, |
105 | install_handler((unsigned) undef_instr_exception_entry, |
348 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
106 | (unsigned *) EXC_UNDEF_INSTR_VEC); |
349 | 107 | ||
350 | install_handler((unsigned) swi_exception_entry, |
108 | install_handler((unsigned) swi_exception_entry, |
351 | (unsigned *) EXC_SWI_VEC); |
109 | (unsigned *) EXC_SWI_VEC); |
352 | 110 | ||
353 | install_handler((unsigned) prefetch_abort_exception_entry, |
111 | install_handler((unsigned) prefetch_abort_exception_entry, |
354 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
112 | (unsigned *) EXC_PREFETCH_ABORT_VEC); |
355 | 113 | ||
356 | install_handler((unsigned) data_abort_exception_entry, |
114 | install_handler((unsigned) data_abort_exception_entry, |
357 | (unsigned *) EXC_DATA_ABORT_VEC); |
115 | (unsigned *) EXC_DATA_ABORT_VEC); |
358 | 116 | ||
359 | install_handler((unsigned) irq_exception_entry, |
117 | install_handler((unsigned) irq_exception_entry, |
360 | (unsigned *) EXC_IRQ_VEC); |
118 | (unsigned *) EXC_IRQ_VEC); |
361 | 119 | ||
362 | install_handler((unsigned) fiq_exception_entry, |
120 | install_handler((unsigned) fiq_exception_entry, |
363 | (unsigned *) EXC_FIQ_VEC); |
121 | (unsigned *) EXC_FIQ_VEC); |
364 | } |
122 | } |
365 | 123 | ||
366 | #ifdef HIGH_EXCEPTION_VECTORS |
124 | #ifdef HIGH_EXCEPTION_VECTORS |
367 | /** Activates use of high exception vectors addresses. */ |
125 | /** Activates use of high exception vectors addresses. */ |
368 | static void high_vectors(void) |
126 | static void high_vectors(void) |
369 | { |
127 | { |
370 | uint32_t control_reg; |
128 | uint32_t control_reg; |
371 | 129 | ||
372 | asm volatile ( |
130 | asm volatile ( |
373 | "mrc p15, 0, %[control_reg], c1, c1" |
131 | "mrc p15, 0, %[control_reg], c1, c1" |
374 | : [control_reg] "=r" (control_reg) |
132 | : [control_reg] "=r" (control_reg) |
375 | ); |
133 | ); |
376 | 134 | ||
377 | /* switch on the high vectors bit */ |
135 | /* switch on the high vectors bit */ |
378 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
136 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
379 | 137 | ||
380 | asm volatile ( |
138 | asm volatile ( |
381 | "mcr p15, 0, %[control_reg], c1, c1" |
139 | "mcr p15, 0, %[control_reg], c1, c1" |
382 | :: [control_reg] "r" (control_reg) |
140 | :: [control_reg] "r" (control_reg) |
383 | ); |
141 | ); |
384 | } |
142 | } |
385 | #endif |
143 | #endif |
386 | 144 | ||
- | 145 | /** Interrupt Exception handler. |
|
- | 146 | * |
|
- | 147 | * Determines the sources of interrupt and calls their handlers. |
|
- | 148 | */ |
|
- | 149 | static void irq_exception(int exc_no, istate_t *istate) |
|
- | 150 | { |
|
- | 151 | machine_irq_exception(exc_no, istate); |
|
- | 152 | } |
|
- | 153 | ||
387 | /** Initializes exception handling. |
154 | /** Initializes exception handling. |
388 | * |
155 | * |
389 | * Installs low-level exception handlers and then registers |
156 | * Installs low-level exception handlers and then registers |
390 | * exceptions and their handlers to kernel exception dispatcher. |
157 | * exceptions and their handlers to kernel exception dispatcher. |
391 | */ |
158 | */ |
392 | void exception_init(void) |
159 | void exception_init(void) |
393 | { |
160 | { |
394 | #ifdef HIGH_EXCEPTION_VECTORS |
161 | #ifdef HIGH_EXCEPTION_VECTORS |
395 | high_vectors(); |
162 | high_vectors(); |
396 | #endif |
163 | #endif |
397 | install_exception_handlers(); |
164 | install_exception_handlers(); |
398 | 165 | ||
399 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
166 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
400 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
167 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", |
401 | (iroutine) prefetch_abort); |
168 | (iroutine) prefetch_abort); |
402 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
169 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
403 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
170 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
404 | } |
171 | } |
405 | 172 | ||
406 | /** Prints #istate_t structure content. |
173 | /** Prints #istate_t structure content. |
407 | * |
174 | * |
408 | * @param istate Structure to be printed. |
175 | * @param istate Structure to be printed. |
409 | */ |
176 | */ |
410 | void print_istate(istate_t *istate) |
177 | void print_istate(istate_t *istate) |
411 | { |
178 | { |
412 | printf("istate dump:\n"); |
179 | printf("istate dump:\n"); |
413 | 180 | ||
414 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
181 | printf(" r0: %x r1: %x r2: %x r3: %x\n", |
415 | istate->r0, istate->r1, istate->r2, istate->r3); |
182 | istate->r0, istate->r1, istate->r2, istate->r3); |
416 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
183 | printf(" r4: %x r5: %x r6: %x r7: %x\n", |
417 | istate->r4, istate->r5, istate->r6, istate->r7); |
184 | istate->r4, istate->r5, istate->r6, istate->r7); |
418 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
185 | printf(" r8: %x r8: %x r10: %x r11: %x\n", |
419 | istate->r8, istate->r9, istate->r10, istate->r11); |
186 | istate->r8, istate->r9, istate->r10, istate->r11); |
420 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
187 | printf(" r12: %x sp: %x lr: %x spsr: %x\n", |
421 | istate->r12, istate->sp, istate->lr, istate->spsr); |
188 | istate->r12, istate->sp, istate->lr, istate->spsr); |
422 | 189 | ||
423 | printf(" pc: %x\n", istate->pc); |
190 | printf(" pc: %x\n", istate->pc); |
424 | } |
191 | } |
425 | 192 | ||
426 | /** @} |
193 | /** @} |
427 | */ |
194 | */ |
428 | 195 |