WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Exception handlers and exception initialization routines.
 */
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <arch/barrier.h>
#include <print.h>
#include <syscall/syscall.h>
 
/** Offset used in calculation of exception handler's relative address.
 *
 * @see install_handler()
 */
#define PREFETCH_OFFSET      0x8
 
/** LDR instruction's code */
#define LDR_OPCODE           0xe59ff000
 
/** Number of exception vectors. */
#define EXC_VECTORS          8
 
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
 
/** Switches to kernel stack and saves all registers there.
 *
 * Temporary exception stack is used to save a few registers
 * before stack switch takes place.
 */
inline static void setup_stack_and_save_regs()
{
    asm volatile(
        "ldr r13, =exc_stack        \n"
        "stmfd r13!, {r0}       \n"
        "mrs r0, spsr           \n"
        "and r0, r0, #0x1f      \n"
        "cmp r0, #0x10          \n"
        "bne 1f             \n"
 
        /* prev mode was usermode */
        "ldmfd r13!, {r0}       \n"
        "ldr r13, =supervisor_sp    \n"
        "ldr r13, [r13]         \n"
        "stmfd r13!, {lr}       \n"
        "stmfd r13!, {r0-r12}       \n"
        "stmfd r13!, {r13, lr}^     \n"
        "mrs r0, spsr           \n"
        "stmfd r13!, {r0}       \n"
        "b 2f               \n"
 
        /* mode was not usermode */
    "1:\n"
        "stmfd r13!, {r1, r2, r3}   \n"
        "mrs r1, cpsr           \n"
        "mov r2, lr         \n"
        "bic r1, r1, #0x1f      \n"
        "orr r1, r1, r0         \n"
        "mrs r0, cpsr           \n"
        "msr cpsr_c, r1         \n"
 
        "mov r3, r13            \n"
        "stmfd r13!, {r2}       \n"
        "mov r2, lr         \n"
        "stmfd r13!, {r4-r12}       \n"
        "mov r1, r13            \n"
        /* the following two lines are for debugging */
        "mov sp, #0         \n"
        "mov lr, #0         \n"
        "msr cpsr_c, r0         \n"
 
        "ldmfd r13!, {r4, r5, r6, r7}   \n"
        "stmfd r1!, {r4, r5, r6}    \n"
        "stmfd r1!, {r7}        \n"
        "stmfd r1!, {r2}        \n"
        "stmfd r1!, {r3}        \n"
        "mrs r0, spsr           \n"
        "stmfd r1!, {r0}        \n"
        "mov r13, r1            \n"
    "2:\n"
    );
}
 
/** Returns from exception mode.
 *
 * Previously saved state of registers (including control register)
 * is restored from the stack.
 */
inline static void load_regs()
{
    asm volatile(
        "ldmfd r13!, {r0}       \n"
        "msr spsr, r0           \n"
        "and r0, r0, #0x1f      \n"
        "cmp r0, #0x10          \n"
        "bne 1f             \n"
 
        /* return to user mode */
        "ldmfd r13!, {r13, lr}^     \n"
        "b 2f               \n"
 
        /* return to non-user mode */
    "1:\n"
        "ldmfd r13!, {r1, r2}       \n"
        "mrs r3, cpsr           \n"
        "bic r3, r3, #0x1f      \n"
        "orr r3, r3, r0         \n"
        "mrs r0, cpsr           \n"
        "msr cpsr_c, r3         \n"
 
        "mov r13, r1            \n"
        "mov lr, r2         \n"
        "msr cpsr_c, r0         \n"
 
        /* actual return */
    "2:\n"
        "ldmfd r13, {r0-r12, pc}^\n"
    );
}
 
 
/** Switch CPU to mode in which interrupts are serviced (currently it
 * is Undefined mode).
 *
 * The default mode for interrupt servicing (Interrupt Mode)
 * can not be used because of nested interrupts (which can occur
 * because interrupts are enabled in higher levels of interrupt handler).
 */
inline static void switch_to_irq_servicing_mode()
{
    /* switch to Undefined mode */
    asm volatile(
        /* save regs used during switching */
        "stmfd sp!, {r0-r3}     \n"
 
        /* save stack pointer and link register to r1, r2 */
        "mov r1, sp         \n"
        "mov r2, lr         \n"
 
        /* mode switch */
        "mrs r0, cpsr           \n"
        "bic r0, r0, #0x1f      \n"
        "orr r0, r0, #0x1b      \n"
        "msr cpsr_c, r0         \n"
 
        /* restore saved sp and lr */
        "mov sp, r1         \n"
        "mov lr, r2         \n"
 
        /* restore original regs */
        "ldmfd sp!, {r0-r3}     \n"
    );
}
 
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
/** General exception handler.
 *
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
/** Updates specified exception vector to jump to given handler.
 *
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler(unsigned handler_addr, unsigned *vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
        PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
    smc_coherence(*vector);
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry(void)
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry(void)
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
/** Low-level Interrupt Exception handler.
 *
 * CPU is switched to Undefined mode before further interrupt processing
 * because of possible occurence of nested interrupt exception, which
 * would overwrite (and thus spoil) stack pointer.
 */
static void irq_exception_entry(void)
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
   
    switch_to_irq_servicing_mode();
   
    CALL_EXC_DISPATCH(EXC_IRQ)
 
    load_regs();
}
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
        istate->r3, istate->r4, istate->r5, istate->r6);
}
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned) reset_exception_entry,
        (unsigned *) EXC_RESET_VEC);
   
    install_handler((unsigned) undef_instr_exception_entry,
        (unsigned *) EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned) swi_exception_entry,
        (unsigned *) EXC_SWI_VEC);
   
    install_handler((unsigned) prefetch_abort_exception_entry,
        (unsigned *) EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned) data_abort_exception_entry,
        (unsigned *) EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned) irq_exception_entry,
        (unsigned *) EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
        (unsigned *) EXC_FIQ_VEC);
}
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors(void)
{
    uint32_t control_reg;
   
    asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
   
    /* switch on the high vectors bit */
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
        (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
}
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
/** @}
 */
 

Rev 2927	Rev 3153
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Exception handlers and exception initialization routines.	33	* @brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36	#include <arch/exception.h>	36	#include <arch/exception.h>
37	#include <arch/debug/print.h>	37	#include <arch/debug/print.h>
38	#include <arch/memstr.h>	38	#include <arch/memstr.h>
39	#include <arch/regutils.h>	39	#include <arch/regutils.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41	#include <arch/machine.h>	41	#include <arch/machine.h>
42	#include <arch/mm/page_fault.h>	42	#include <arch/mm/page_fault.h>
-		43	#include <arch/barrier.h>
43	#include <print.h>	44	#include <print.h>
44	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
45		46
46	/** Offset used in calculation of exception handler's relative address.	47	/** Offset used in calculation of exception handler's relative address.
47	*	48	*
48	* @see install_handler()	49	* @see install_handler()
49	*/	50	*/
50	#define PREFETCH_OFFSET 0x8	51	#define PREFETCH_OFFSET 0x8
51		52
52	/** LDR instruction's code */	53	/** LDR instruction's code */
53	#define LDR_OPCODE 0xe59ff000	54	#define LDR_OPCODE 0xe59ff000
54		55
55	/** Number of exception vectors. */	56	/** Number of exception vectors. */
56	#define EXC_VECTORS 8	57	#define EXC_VECTORS 8
57		58
58	/** Size of memory block occupied by exception vectors. */	59	/** Size of memory block occupied by exception vectors. */
59	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)	60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
60		61
61	/** Switches to kernel stack and saves all registers there.	62	/** Switches to kernel stack and saves all registers there.
62	*	63	*
63	* Temporary exception stack is used to save a few registers	64	* Temporary exception stack is used to save a few registers
64	* before stack switch takes place.	65	* before stack switch takes place.
65	*/	66	*/
66	inline static void setup_stack_and_save_regs()	67	inline static void setup_stack_and_save_regs()
67	{	68	{
68	asm volatile(	69	asm volatile(
69	"ldr r13, =exc_stack \n"	70	"ldr r13, =exc_stack \n"
70	"stmfd r13!, {r0} \n"	71	"stmfd r13!, {r0} \n"
71	"mrs r0, spsr \n"	72	"mrs r0, spsr \n"
72	"and r0, r0, #0x1f \n"	73	"and r0, r0, #0x1f \n"
73	"cmp r0, #0x10 \n"	74	"cmp r0, #0x10 \n"
74	"bne 1f \n"	75	"bne 1f \n"
75		76
76	/* prev mode was usermode */	77	/* prev mode was usermode */
77	"ldmfd r13!, {r0} \n"	78	"ldmfd r13!, {r0} \n"
78	"ldr r13, =supervisor_sp \n"	79	"ldr r13, =supervisor_sp \n"
79	"ldr r13, [r13] \n"	80	"ldr r13, [r13] \n"
80	"stmfd r13!, {lr} \n"	81	"stmfd r13!, {lr} \n"
81	"stmfd r13!, {r0-r12} \n"	82	"stmfd r13!, {r0-r12} \n"
82	"stmfd r13!, {r13, lr}^ \n"	83	"stmfd r13!, {r13, lr}^ \n"
83	"mrs r0, spsr \n"	84	"mrs r0, spsr \n"
84	"stmfd r13!, {r0} \n"	85	"stmfd r13!, {r0} \n"
85	"b 2f \n"	86	"b 2f \n"
86		87
87	/* mode was not usermode */	88	/* mode was not usermode */
88	"1:\n"	89	"1:\n"
89	"stmfd r13!, {r1, r2, r3} \n"	90	"stmfd r13!, {r1, r2, r3} \n"
90	"mrs r1, cpsr \n"	91	"mrs r1, cpsr \n"
91	"mov r2, lr \n"	92	"mov r2, lr \n"
92	"bic r1, r1, #0x1f \n"	93	"bic r1, r1, #0x1f \n"
93	"orr r1, r1, r0 \n"	94	"orr r1, r1, r0 \n"
94	"mrs r0, cpsr \n"	95	"mrs r0, cpsr \n"
95	"msr cpsr_c, r1 \n"	96	"msr cpsr_c, r1 \n"
96		97
97	"mov r3, r13 \n"	98	"mov r3, r13 \n"
98	"stmfd r13!, {r2} \n"	99	"stmfd r13!, {r2} \n"
99	"mov r2, lr \n"	100	"mov r2, lr \n"
100	"stmfd r13!, {r4-r12} \n"	101	"stmfd r13!, {r4-r12} \n"
101	"mov r1, r13 \n"	102	"mov r1, r13 \n"
102	/* the following two lines are for debugging */	103	/* the following two lines are for debugging */
103	"mov sp, #0 \n"	104	"mov sp, #0 \n"
104	"mov lr, #0 \n"	105	"mov lr, #0 \n"
105	"msr cpsr_c, r0 \n"	106	"msr cpsr_c, r0 \n"
106		107
107	"ldmfd r13!, {r4, r5, r6, r7} \n"	108	"ldmfd r13!, {r4, r5, r6, r7} \n"
108	"stmfd r1!, {r4, r5, r6} \n"	109	"stmfd r1!, {r4, r5, r6} \n"
109	"stmfd r1!, {r7} \n"	110	"stmfd r1!, {r7} \n"
110	"stmfd r1!, {r2} \n"	111	"stmfd r1!, {r2} \n"
111	"stmfd r1!, {r3} \n"	112	"stmfd r1!, {r3} \n"
112	"mrs r0, spsr \n"	113	"mrs r0, spsr \n"
113	"stmfd r1!, {r0} \n"	114	"stmfd r1!, {r0} \n"
114	"mov r13, r1 \n"	115	"mov r13, r1 \n"
115	"2:\n"	116	"2:\n"
116	);	117	);
117	}	118	}
118		119
119	/** Returns from exception mode.	120	/** Returns from exception mode.
120	*	121	*
121	* Previously saved state of registers (including control register)	122	* Previously saved state of registers (including control register)
122	* is restored from the stack.	123	* is restored from the stack.
123	*/	124	*/
124	inline static void load_regs()	125	inline static void load_regs()
125	{	126	{
126	asm volatile(	127	asm volatile(
127	"ldmfd r13!, {r0} \n"	128	"ldmfd r13!, {r0} \n"
128	"msr spsr, r0 \n"	129	"msr spsr, r0 \n"
129	"and r0, r0, #0x1f \n"	130	"and r0, r0, #0x1f \n"
130	"cmp r0, #0x10 \n"	131	"cmp r0, #0x10 \n"
131	"bne 1f \n"	132	"bne 1f \n"
132		133
133	/* return to user mode */	134	/* return to user mode */
134	"ldmfd r13!, {r13, lr}^ \n"	135	"ldmfd r13!, {r13, lr}^ \n"
135	"b 2f \n"	136	"b 2f \n"
136		137
137	/* return to non-user mode */	138	/* return to non-user mode */
138	"1:\n"	139	"1:\n"
139	"ldmfd r13!, {r1, r2} \n"	140	"ldmfd r13!, {r1, r2} \n"
140	"mrs r3, cpsr \n"	141	"mrs r3, cpsr \n"
141	"bic r3, r3, #0x1f \n"	142	"bic r3, r3, #0x1f \n"
142	"orr r3, r3, r0 \n"	143	"orr r3, r3, r0 \n"
143	"mrs r0, cpsr \n"	144	"mrs r0, cpsr \n"
144	"msr cpsr_c, r3 \n"	145	"msr cpsr_c, r3 \n"
145		146
146	"mov r13, r1 \n"	147	"mov r13, r1 \n"
147	"mov lr, r2 \n"	148	"mov lr, r2 \n"
148	"msr cpsr_c, r0 \n"	149	"msr cpsr_c, r0 \n"
149		150
150	/* actual return */	151	/* actual return */
151	"2:\n"	152	"2:\n"
152	"ldmfd r13, {r0-r12, pc}^\n"	153	"ldmfd r13, {r0-r12, pc}^\n"
153	);	154	);
154	}	155	}
155		156
156		157
157	/** Switch CPU to mode in which interrupts are serviced (currently it	158	/** Switch CPU to mode in which interrupts are serviced (currently it
158	* is Undefined mode).	159	* is Undefined mode).
159	*	160	*
160	* The default mode for interrupt servicing (Interrupt Mode)	161	* The default mode for interrupt servicing (Interrupt Mode)
161	* can not be used because of nested interrupts (which can occur	162	* can not be used because of nested interrupts (which can occur
162	* because interrupts are enabled in higher levels of interrupt handler).	163	* because interrupts are enabled in higher levels of interrupt handler).
163	*/	164	*/
164	inline static void switch_to_irq_servicing_mode()	165	inline static void switch_to_irq_servicing_mode()
165	{	166	{
166	/* switch to Undefined mode */	167	/* switch to Undefined mode */
167	asm volatile(	168	asm volatile(
168	/* save regs used during switching */	169	/* save regs used during switching */
169	"stmfd sp!, {r0-r3} \n"	170	"stmfd sp!, {r0-r3} \n"
170		171
171	/* save stack pointer and link register to r1, r2 */	172	/* save stack pointer and link register to r1, r2 */
172	"mov r1, sp \n"	173	"mov r1, sp \n"
173	"mov r2, lr \n"	174	"mov r2, lr \n"
174		175
175	/* mode switch */	176	/* mode switch */
176	"mrs r0, cpsr \n"	177	"mrs r0, cpsr \n"
177	"bic r0, r0, #0x1f \n"	178	"bic r0, r0, #0x1f \n"
178	"orr r0, r0, #0x1b \n"	179	"orr r0, r0, #0x1b \n"
179	"msr cpsr_c, r0 \n"	180	"msr cpsr_c, r0 \n"
180		181
181	/* restore saved sp and lr */	182	/* restore saved sp and lr */
182	"mov sp, r1 \n"	183	"mov sp, r1 \n"
183	"mov lr, r2 \n"	184	"mov lr, r2 \n"
184		185
185	/* restore original regs */	186	/* restore original regs */
186	"ldmfd sp!, {r0-r3} \n"	187	"ldmfd sp!, {r0-r3} \n"
187	);	188	);
188	}	189	}
189		190
190	/** Calls exception dispatch routine. */	191	/** Calls exception dispatch routine. */
191	#define CALL_EXC_DISPATCH(exception) \	192	#define CALL_EXC_DISPATCH(exception) \
192	asm("mov r0, %0" : : "i" (exception)); \	193	asm("mov r0, %0" : : "i" (exception)); \
193	asm("mov r1, r13"); \	194	asm("mov r1, r13"); \
194	asm("bl exc_dispatch");	195	asm("bl exc_dispatch");
195		196
196	/** General exception handler.	197	/** General exception handler.
197	*	198	*
198	* Stores registers, dispatches the exception,	199	* Stores registers, dispatches the exception,
199	* and finally restores registers and returns from exception processing.	200	* and finally restores registers and returns from exception processing.
200	*	201	*
201	* @param exception Exception number.	202	* @param exception Exception number.
202	*/	203	*/
203	#define PROCESS_EXCEPTION(exception) \	204	#define PROCESS_EXCEPTION(exception) \
204	setup_stack_and_save_regs(); \	205	setup_stack_and_save_regs(); \
205	CALL_EXC_DISPATCH(exception) \	206	CALL_EXC_DISPATCH(exception) \
206	load_regs();	207	load_regs();
207		208
208	/** Updates specified exception vector to jump to given handler.	209	/** Updates specified exception vector to jump to given handler.
209	*	210	*
210	* Addresses of handlers are stored in memory following exception vectors.	211	* Addresses of handlers are stored in memory following exception vectors.
211	*/	212	*/
212	static void install_handler (unsigned handler_addr, unsigned* vector)	213	static void install_handler(unsigned handler_addr, unsigned *vector)
213	{	214	{
214	/* relative address (related to exc. vector) of the word	215	/* relative address (related to exc. vector) of the word
215	* where handler's address is stored	216	* where handler's address is stored
216	*/	217	*/
217	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -	218	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
218	PREFETCH_OFFSET;	219	PREFETCH_OFFSET;
219		220
220	/* make it LDR instruction and store at exception vector */	221	/* make it LDR instruction and store at exception vector */
221	*vector = handler_address_ptr \| LDR_OPCODE;	222	*vector = handler_address_ptr \| LDR_OPCODE;
-		223	smc_coherence(*vector);
222		224
223	/* store handler's address */	225	/* store handler's address */
224	*(vector + EXC_VECTORS) = handler_addr;	226	*(vector + EXC_VECTORS) = handler_addr;
225		227
226	}	228	}
227		229
228	/** Low-level Reset Exception handler. */	230	/** Low-level Reset Exception handler. */
229	static void reset_exception_entry()	231	static void reset_exception_entry(void)
230	{	232	{
231	PROCESS_EXCEPTION(EXC_RESET);	233	PROCESS_EXCEPTION(EXC_RESET);
232	}	234	}
233		235
234	/** Low-level Software Interrupt Exception handler. */	236	/** Low-level Software Interrupt Exception handler. */
235	static void swi_exception_entry()	237	static void swi_exception_entry(void)
236	{	238	{
237	PROCESS_EXCEPTION(EXC_SWI);	239	PROCESS_EXCEPTION(EXC_SWI);
238	}	240	}
239		241
240	/** Low-level Undefined Instruction Exception handler. */	242	/** Low-level Undefined Instruction Exception handler. */
241	static void undef_instr_exception_entry()	243	static void undef_instr_exception_entry(void)
242	{	244	{
243	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	245	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
244	}	246	}
245		247
246	/** Low-level Fast Interrupt Exception handler. */	248	/** Low-level Fast Interrupt Exception handler. */
247	static void fiq_exception_entry()	249	static void fiq_exception_entry(void)
248	{	250	{
249	PROCESS_EXCEPTION(EXC_FIQ);	251	PROCESS_EXCEPTION(EXC_FIQ);
250	}	252	}
251		253
252	/** Low-level Prefetch Abort Exception handler. */	254	/** Low-level Prefetch Abort Exception handler. */
253	static void prefetch_abort_exception_entry()	255	static void prefetch_abort_exception_entry(void)
254	{	256	{
255	asm("sub lr, lr, #4");	257	asm("sub lr, lr, #4");
256	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	258	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
257	}	259	}
258		260
259	/** Low-level Data Abort Exception handler. */	261	/** Low-level Data Abort Exception handler. */
260	static void data_abort_exception_entry()	262	static void data_abort_exception_entry(void)
261	{	263	{
262	asm("sub lr, lr, #8");	264	asm("sub lr, lr, #8");
263	PROCESS_EXCEPTION(EXC_DATA_ABORT);	265	PROCESS_EXCEPTION(EXC_DATA_ABORT);
264	}	266	}
265		267
266	/** Low-level Interrupt Exception handler.	268	/** Low-level Interrupt Exception handler.
267	*	269	*
268	* CPU is switched to Undefined mode before further interrupt processing	270	* CPU is switched to Undefined mode before further interrupt processing
269	* because of possible occurence of nested interrupt exception, which	271	* because of possible occurence of nested interrupt exception, which
270	* would overwrite (and thus spoil) stack pointer.	272	* would overwrite (and thus spoil) stack pointer.
271	*/	273	*/
272	static void irq_exception_entry()	274	static void irq_exception_entry(void)
273	{	275	{
274	asm("sub lr, lr, #4");	276	asm("sub lr, lr, #4");
275	setup_stack_and_save_regs();	277	setup_stack_and_save_regs();
276		278
277	switch_to_irq_servicing_mode();	279	switch_to_irq_servicing_mode();
278		280
279	CALL_EXC_DISPATCH(EXC_IRQ)	281	CALL_EXC_DISPATCH(EXC_IRQ)
280		282
281	load_regs();	283	load_regs();
282	}	284	}
283		285
284	/** Software Interrupt handler.	286	/** Software Interrupt handler.
285	*	287	*
286	* Dispatches the syscall.	288	* Dispatches the syscall.
287	*/	289	*/
288	static void swi_exception(int exc_no, istate_t *istate)	290	static void swi_exception(int exc_no, istate_t *istate)
289	{	291	{
290	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,	292	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
291	istate->r3, istate->r4, istate->r5, istate->r6);	293	istate->r3, istate->r4, istate->r5, istate->r6);
292	}	294	}
293		295
294	/** Interrupt Exception handler.	296	/** Interrupt Exception handler.
295	*	297	*
296	* Determines the sources of interrupt and calls their handlers.	298	* Determines the sources of interrupt and calls their handlers.
297	*/	299	*/
298	static void irq_exception(int exc_no, istate_t *istate)	300	static void irq_exception(int exc_no, istate_t *istate)
299	{	301	{
300	machine_irq_exception(exc_no, istate);	302	machine_irq_exception(exc_no, istate);
301	}	303	}
302		304
303	/** Fills exception vectors with appropriate exception handlers. */	305	/** Fills exception vectors with appropriate exception handlers. */
304	void install_exception_handlers(void)	306	void install_exception_handlers(void)
305	{	307	{
306	install_handler((unsigned) reset_exception_entry,	308	install_handler((unsigned) reset_exception_entry,
307	(unsigned *) EXC_RESET_VEC);	309	(unsigned *) EXC_RESET_VEC);
308		310
309	install_handler((unsigned) undef_instr_exception_entry,	311	install_handler((unsigned) undef_instr_exception_entry,
310	(unsigned *) EXC_UNDEF_INSTR_VEC);	312	(unsigned *) EXC_UNDEF_INSTR_VEC);
311		313
312	install_handler((unsigned) swi_exception_entry,	314	install_handler((unsigned) swi_exception_entry,
313	(unsigned *) EXC_SWI_VEC);	315	(unsigned *) EXC_SWI_VEC);
314		316
315	install_handler((unsigned) prefetch_abort_exception_entry,	317	install_handler((unsigned) prefetch_abort_exception_entry,
316	(unsigned *) EXC_PREFETCH_ABORT_VEC);	318	(unsigned *) EXC_PREFETCH_ABORT_VEC);
317		319
318	install_handler((unsigned) data_abort_exception_entry,	320	install_handler((unsigned) data_abort_exception_entry,
319	(unsigned *) EXC_DATA_ABORT_VEC);	321	(unsigned *) EXC_DATA_ABORT_VEC);
320		322
321	install_handler((unsigned) irq_exception_entry,	323	install_handler((unsigned) irq_exception_entry,
322	(unsigned *) EXC_IRQ_VEC);	324	(unsigned *) EXC_IRQ_VEC);
323		325
324	install_handler((unsigned)fiq_exception_entry,	326	install_handler((unsigned)fiq_exception_entry,
325	(unsigned *) EXC_FIQ_VEC);	327	(unsigned *) EXC_FIQ_VEC);
326	}	328	}
327		329
328	#ifdef HIGH_EXCEPTION_VECTORS	330	#ifdef HIGH_EXCEPTION_VECTORS
329	/** Activates use of high exception vectors addresses. */	331	/** Activates use of high exception vectors addresses. */
330	static void high_vectors(void)	332	static void high_vectors(void)
331	{	333	{
332	uint32_t control_reg;	334	uint32_t control_reg;
333		335
334	asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));	336	asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));
335		337
336	/* switch on the high vectors bit */	338	/* switch on the high vectors bit */
337	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	339	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
338		340
339	asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	341	asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
340	}	342	}
341	#endif	343	#endif
342		344
343	/** Initializes exception handling.	345	/** Initializes exception handling.
344	*	346	*
345	* Installs low-level exception handlers and then registers	347	* Installs low-level exception handlers and then registers
346	* exceptions and their handlers to kernel exception dispatcher.	348	* exceptions and their handlers to kernel exception dispatcher.
347	*/	349	*/
348	void exception_init(void)	350	void exception_init(void)
349	{	351	{
350	#ifdef HIGH_EXCEPTION_VECTORS	352	#ifdef HIGH_EXCEPTION_VECTORS
351	high_vectors();	353	high_vectors();
352	#endif	354	#endif
353	install_exception_handlers();	355	install_exception_handlers();
354		356
355	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	357	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
356	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",	358	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
357	(iroutine) prefetch_abort);	359	(iroutine) prefetch_abort);
358	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	360	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
359	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	361	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
360	}	362	}
361		363
362	/** Prints #istate_t structure content.	364	/** Prints #istate_t structure content.
363	*	365	*
364	* @param istate Structure to be printed.	366	* @param istate Structure to be printed.
365	*/	367	*/
366	void print_istate(istate_t *istate)	368	void print_istate(istate_t *istate)
367	{	369	{
368	dprintf("istate dump:\n");	370	dprintf("istate dump:\n");
369		371
370	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	372	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
371	istate->r0, istate->r1, istate->r2, istate->r3);	373	istate->r0, istate->r1, istate->r2, istate->r3);
372	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	374	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
373	istate->r4, istate->r5, istate->r6, istate->r7);	375	istate->r4, istate->r5, istate->r6, istate->r7);
374	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	376	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
375	istate->r8, istate->r9, istate->r10, istate->r11);	377	istate->r8, istate->r9, istate->r10, istate->r11);
376	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	378	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
377	istate->r12, istate->sp, istate->lr, istate->spsr);	379	istate->r12, istate->sp, istate->lr, istate->spsr);
378		380
379	dprintf(" pc: %x\n", istate->pc);	381	dprintf(" pc: %x\n", istate->pc);
380	}	382	}
381		383
382	/** @}	384	/** @}
383	*/	385	*/
384		386

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(root)/branches/dynload/kernel/arch/arm32/src/exception.c @ 4345 – Rev 2927 → 3153