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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <ipc/irq.h> |
36 | #include <ipc/irq.h> |
37 | #include <console/chardev.h> |
37 | #include <console/chardev.h> |
38 | #include <arch/drivers/gxemul.h> |
38 | #include <arch/drivers/gxemul.h> |
39 | #include <console/console.h> |
39 | #include <console/console.h> |
40 | #include <sysinfo/sysinfo.h> |
40 | #include <sysinfo/sysinfo.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <ddi/device.h> |
42 | #include <ddi/device.h> |
43 | #include <mm/page.h> |
43 | #include <mm/page.h> |
44 | #include <arch/machine.h> |
44 | #include <arch/machine.h> |
45 | #include <arch/debug/print.h> |
45 | #include <arch/debug/print.h> |
46 | 46 | ||
- | 47 | ||
47 | /** Address of devices. */ |
48 | /** Address of devices. */ |
48 | #define GXEMUL_VIDEORAM 0x10000000 |
49 | #define GXEMUL_VIDEORAM 0x10000000 |
49 | #define GXEMUL_KBD 0x10000000 |
50 | #define GXEMUL_KBD 0x10000000 |
50 | #define GXEMUL_HALT_OFFSET 0x10 |
51 | #define GXEMUL_HALT_OFFSET 0x10 |
51 | #define GXEMUL_RTC 0x15000000 |
52 | #define GXEMUL_RTC 0x15000000 |
52 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
53 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
53 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
54 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
54 | #define GXEMUL_IRQC 0x16000000 |
55 | #define GXEMUL_IRQC 0x16000000 |
55 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
56 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
56 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
57 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
57 | #define GXEMUL_MP 0x11000000 |
58 | #define GXEMUL_MP 0x11000000 |
58 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
59 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
- | 60 | #define GXEMUL_FB 0x12000000 |
|
59 | 61 | ||
60 | 62 | ||
61 | /** IRQs */ |
63 | /** IRQs */ |
62 | #define GXEMUL_KBD_IRQ 2 |
64 | #define GXEMUL_KBD_IRQ 2 |
63 | #define GXEMUL_TIMER_IRQ 4 |
65 | #define GXEMUL_TIMER_IRQ 4 |
64 | 66 | ||
65 | static gxemul_hw_map_t gxemul_hw_map; |
67 | static gxemul_hw_map_t gxemul_hw_map; |
66 | static chardev_t console; |
68 | static chardev_t console; |
67 | static irq_t gxemul_irq; |
69 | static irq_t gxemul_irq; |
68 | static irq_t gxemul_timer_irq; |
70 | static irq_t gxemul_timer_irq; |
69 | 71 | ||
70 | static bool hw_map_init_called = false; |
72 | static bool hw_map_init_called = false; |
71 | 73 | ||
72 | static void gxemul_write(chardev_t *dev, const char ch); |
74 | static void gxemul_write(chardev_t *dev, const char ch); |
73 | static void gxemul_enable(chardev_t *dev); |
75 | static void gxemul_enable(chardev_t *dev); |
74 | static void gxemul_disable(chardev_t *dev); |
76 | static void gxemul_disable(chardev_t *dev); |
75 | static char gxemul_do_read(chardev_t *dev); |
77 | static char gxemul_do_read(chardev_t *dev); |
76 | 78 | ||
77 | static chardev_operations_t gxemul_ops = { |
79 | static chardev_operations_t gxemul_ops = { |
78 | .resume = gxemul_enable, |
80 | .resume = gxemul_enable, |
79 | .suspend = gxemul_disable, |
81 | .suspend = gxemul_disable, |
80 | .write = gxemul_write, |
82 | .write = gxemul_write, |
81 | .read = gxemul_do_read, |
83 | .read = gxemul_do_read, |
82 | }; |
84 | }; |
83 | 85 | ||
- | 86 | /** Return the mask of active interrupts. */ |
|
- | 87 | static inline uint32_t gxemul_irqc_get_sources(void) |
|
- | 88 | { |
|
- | 89 | return *(uint32_t*) gxemul_hw_map.irqc; |
|
- | 90 | } |
|
- | 91 | ||
- | 92 | /** Masks interrupt. |
|
- | 93 | * |
|
- | 94 | * @param irq interrupt number |
|
- | 95 | */ |
|
- | 96 | static inline void gxemul_irqc_mask(uint32_t irq) |
|
- | 97 | { |
|
- | 98 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
|
- | 99 | } |
|
- | 100 | ||
- | 101 | /** Unmasks interrupt. |
|
- | 102 | * |
|
- | 103 | * @param irq interrupt number |
|
- | 104 | */ |
|
- | 105 | static inline void gxemul_irqc_unmask(uint32_t irq) |
|
- | 106 | { |
|
- | 107 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
|
- | 108 | } |
|
84 | 109 | ||
85 | /** Initializes #gxemul_hw_map. */ |
110 | /** Initializes #gxemul_hw_map. */ |
86 | void machine_hw_map_init(void) |
111 | void machine_hw_map_init(void) |
87 | { |
112 | { |
88 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
113 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
89 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
114 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
90 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
115 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
91 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
116 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
92 | 117 | ||
93 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
118 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
94 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
119 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
95 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
120 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
96 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
121 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
97 | 122 | ||
98 | hw_map_init_called = true; |
123 | hw_map_init_called = true; |
99 | } |
124 | } |
100 | 125 | ||
101 | /** Putchar that works with gxemul */ |
126 | /** Putchar that works with gxemul */ |
102 | void gxemul_write(chardev_t *dev, const char ch) |
127 | static void gxemul_write(chardev_t *dev, const char ch) |
103 | { |
128 | { |
104 | *((char *) gxemul_hw_map.videoram) = ch; |
129 | *((char *) gxemul_hw_map.videoram) = ch; |
105 | } |
130 | } |
106 | 131 | ||
107 | /* Called from getc(). */ |
132 | /* Called from getc(). */ |
108 | void gxemul_enable(chardev_t *dev) |
133 | static void gxemul_enable(chardev_t *dev) |
109 | { |
134 | { |
110 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
- | |
111 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
135 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
112 | } |
136 | } |
113 | 137 | ||
114 | /* Called from getc(). */ |
138 | /* Called from getc(). */ |
115 | void gxemul_disable(chardev_t *dev) |
139 | static void gxemul_disable(chardev_t *dev) |
116 | { |
140 | { |
117 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
- | |
118 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
141 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
119 | } |
142 | } |
120 | 143 | ||
121 | /** Read character using polling, assume interrupts disabled */ |
144 | /** Read character using polling, assume interrupts disabled */ |
122 | static char gxemul_do_read(chardev_t *dev) |
145 | static char gxemul_do_read(chardev_t *dev) |
123 | { |
146 | { |
124 | char ch; |
147 | char ch; |
125 | 148 | ||
126 | while (1) { |
149 | while (1) { |
127 | ch = *((volatile char *) gxemul_hw_map.kbd); |
150 | ch = *((volatile char *) gxemul_hw_map.kbd); |
128 | if (ch) { |
151 | if (ch) { |
129 | if (ch == '\r') |
152 | if (ch == '\r') |
130 | return '\n'; |
153 | return '\n'; |
131 | if (ch == 0x7f) |
154 | if (ch == 0x7f) |
132 | return '\b'; |
155 | return '\b'; |
133 | return ch; |
156 | return ch; |
134 | } |
157 | } |
135 | } |
158 | } |
136 | } |
159 | } |
137 | 160 | ||
138 | /** Process keyboard interrupt. */ |
161 | /** Process keyboard interrupt. */ |
139 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
162 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
140 | { |
163 | { |
141 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
164 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
142 | ipc_irq_send_notif(irq); |
165 | ipc_irq_send_notif(irq); |
143 | else { |
166 | else { |
144 | char ch = 0; |
167 | char ch = 0; |
145 | 168 | ||
146 | ch = *((char *) gxemul_hw_map.kbd); |
169 | ch = *((char *) gxemul_hw_map.kbd); |
147 | if (ch =='\r') |
170 | if (ch =='\r') |
148 | ch = '\n'; |
171 | ch = '\n'; |
149 | if (ch == 0x7f) |
172 | if (ch == 0x7f) |
150 | ch = '\b'; |
173 | ch = '\b'; |
151 | chardev_push_character(&console, ch); |
174 | chardev_push_character(&console, ch); |
152 | } |
175 | } |
153 | } |
176 | } |
154 | 177 | ||
155 | static irq_ownership_t gxemul_claim(void) |
178 | static irq_ownership_t gxemul_claim(void) |
156 | { |
179 | { |
157 | return IRQ_ACCEPT; |
180 | return IRQ_ACCEPT; |
158 | } |
181 | } |
159 | 182 | ||
160 | void machine_grab_console(void) |
183 | void machine_grab_console(void) |
161 | { |
184 | { |
162 | ipl_t ipl = interrupts_disable(); |
185 | ipl_t ipl = interrupts_disable(); |
163 | spinlock_lock(&gxemul_irq.lock); |
186 | spinlock_lock(&gxemul_irq.lock); |
164 | gxemul_irq.notif_cfg.notify = false; |
187 | gxemul_irq.notif_cfg.notify = false; |
165 | spinlock_unlock(&gxemul_irq.lock); |
188 | spinlock_unlock(&gxemul_irq.lock); |
166 | interrupts_restore(ipl); |
189 | interrupts_restore(ipl); |
167 | } |
190 | } |
168 | 191 | ||
169 | void machine_release_console(void) |
192 | void machine_release_console(void) |
170 | { |
193 | { |
171 | ipl_t ipl = interrupts_disable(); |
194 | ipl_t ipl = interrupts_disable(); |
172 | spinlock_lock(&gxemul_irq.lock); |
195 | spinlock_lock(&gxemul_irq.lock); |
173 | if (gxemul_irq.notif_cfg.answerbox) |
196 | if (gxemul_irq.notif_cfg.answerbox) |
174 | gxemul_irq.notif_cfg.notify = true; |
197 | gxemul_irq.notif_cfg.notify = true; |
175 | spinlock_unlock(&gxemul_irq.lock); |
198 | spinlock_unlock(&gxemul_irq.lock); |
176 | interrupts_restore(ipl); |
199 | interrupts_restore(ipl); |
177 | } |
200 | } |
178 | 201 | ||
179 | 202 | ||
180 | /** Return console object representing gxemul console */ |
203 | /** Return console object representing gxemul console */ |
181 | void machine_console_init(devno_t devno) |
204 | void machine_console_init(devno_t devno) |
182 | { |
205 | { |
183 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
206 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
184 | stdin = &console; |
207 | stdin = &console; |
185 | stdout = &console; |
208 | stdout = &console; |
186 | 209 | ||
187 | irq_initialize(&gxemul_irq); |
210 | irq_initialize(&gxemul_irq); |
188 | gxemul_irq.devno = devno; |
211 | gxemul_irq.devno = devno; |
189 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
212 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
190 | gxemul_irq.claim = gxemul_claim; |
213 | gxemul_irq.claim = gxemul_claim; |
191 | gxemul_irq.handler = gxemul_irq_handler; |
214 | gxemul_irq.handler = gxemul_irq_handler; |
192 | irq_register(&gxemul_irq); |
215 | irq_register(&gxemul_irq); |
193 | 216 | ||
194 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
- | |
195 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
217 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
196 | 218 | ||
197 | sysinfo_set_item_val("kbd", NULL, true); |
219 | sysinfo_set_item_val("kbd", NULL, true); |
198 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
220 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
199 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
221 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
200 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
222 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
201 | } |
223 | } |
202 | 224 | ||
203 | /** Return the mask of active interrupts. */ |
- | |
204 | inline uint32_t gxemul_irqc_get_sources(void) |
- | |
205 | { |
- | |
206 | return *(uint32_t*) gxemul_hw_map.irqc; |
- | |
207 | } |
- | |
208 | - | ||
209 | /** Masks interrupt. |
- | |
210 | * |
- | |
211 | * @param irq interrupt number |
- | |
212 | */ |
- | |
213 | inline void gxemul_irqc_mask(uint32_t irq) |
- | |
214 | { |
- | |
215 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
- | |
216 | } |
- | |
217 | - | ||
218 | /** Unmasks interrupt. |
- | |
219 | * |
- | |
220 | * @param irq interrupt number |
- | |
221 | */ |
- | |
222 | inline void gxemul_irqc_unmask(uint32_t irq) |
- | |
223 | { |
- | |
224 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
- | |
225 | } |
- | |
226 | 225 | ||
227 | 226 | ||
228 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
227 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
229 | * |
228 | * |
230 | * @param frequency interrupts frequency (0 disables RTC) |
229 | * @param frequency interrupts frequency (0 disables RTC) |
231 | */ |
230 | */ |
232 | void gxemul_timer_start(uint32_t frequency) |
231 | static void gxemul_timer_start(uint32_t frequency) |
233 | { |
232 | { |
234 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
233 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
235 | } |
234 | } |
236 | 235 | ||
237 | static irq_ownership_t gxemul_timer_claim(void) |
236 | static irq_ownership_t gxemul_timer_claim(void) |
238 | { |
237 | { |
239 | return IRQ_ACCEPT; |
238 | return IRQ_ACCEPT; |
240 | } |
239 | } |
241 | 240 | ||
242 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
241 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
243 | { |
242 | { |
244 | /* TODO time drifts ?? |
243 | /* TODO time drifts ?? |
245 | unsigned long drift; |
244 | unsigned long drift; |
246 | 245 | ||
247 | drift = cp0_count_read() - nextcount; |
246 | drift = cp0_count_read() - nextcount; |
248 | while (drift > cp0_compare_value) { |
247 | while (drift > cp0_compare_value) { |
249 | drift -= cp0_compare_value; |
248 | drift -= cp0_compare_value; |
250 | CPU->missed_clock_ticks++; |
249 | CPU->missed_clock_ticks++; |
251 | } |
250 | } |
252 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
251 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
253 | cp0_compare_write(nextcount); |
252 | cp0_compare_write(nextcount); |
254 | */ |
253 | */ |
255 | 254 | ||
256 | /* |
255 | /* |
257 | * We are holding a lock which prevents preemption. |
256 | * We are holding a lock which prevents preemption. |
258 | * Release the lock, call clock() and reacquire the lock again. |
257 | * Release the lock, call clock() and reacquire the lock again. |
259 | */ |
258 | */ |
260 | spinlock_unlock(&irq->lock); |
259 | spinlock_unlock(&irq->lock); |
261 | clock(); |
260 | clock(); |
262 | spinlock_lock(&irq->lock); |
261 | spinlock_lock(&irq->lock); |
263 | 262 | ||
264 | /* acknowledge tick */ |
263 | /* acknowledge tick */ |
265 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
264 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
266 | 265 | ||
267 | /* TODO what's that? * |
266 | /* TODO what's that? * |
268 | if (virtual_timer_fnc != NULL) |
267 | if (virtual_timer_fnc != NULL) |
269 | virtual_timer_fnc(); |
268 | virtual_timer_fnc(); |
270 | */ |
269 | */ |
271 | } |
270 | } |
272 | 271 | ||
273 | /** |
272 | /** |
274 | * Initializes and registers timer interrupt handler. |
273 | * Initializes and registers timer interrupt handler. |
275 | */ |
274 | */ |
276 | void gxemul_timer_irq_init() |
275 | static void gxemul_timer_irq_init() |
277 | { |
276 | { |
278 | irq_initialize(&gxemul_timer_irq); |
277 | irq_initialize(&gxemul_timer_irq); |
279 | gxemul_timer_irq.devno = device_assign_devno(); |
278 | gxemul_timer_irq.devno = device_assign_devno(); |
280 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
279 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
281 | gxemul_timer_irq.claim = gxemul_timer_claim; |
280 | gxemul_timer_irq.claim = gxemul_timer_claim; |
282 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
281 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
283 | 282 | ||
284 | irq_register(&gxemul_timer_irq); |
283 | irq_register(&gxemul_timer_irq); |
285 | } |
284 | } |
286 | 285 | ||
287 | void machine_timer_irq_start() |
286 | void machine_timer_irq_start() |
288 | { |
287 | { |
289 | gxemul_timer_irq_init(); |
288 | gxemul_timer_irq_init(); |
290 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
289 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
291 | } |
290 | } |
292 | 291 | ||
293 | size_t machine_get_memory_size(void) |
292 | size_t machine_get_memory_size(void) |
294 | { |
293 | { |
295 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
294 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
296 | } |
295 | } |
297 | 296 | ||
298 | void machine_debug_putc(char ch) |
297 | void machine_debug_putc(char ch) |
299 | { |
298 | { |
300 | char * addr = 0; |
299 | char * addr = 0; |
301 | if (!hw_map_init_called) { |
300 | if (!hw_map_init_called) { |
302 | addr = (char *) GXEMUL_KBD; |
301 | addr = (char *) GXEMUL_KBD; |
303 | } else { |
302 | } else { |
304 | addr = (char *) gxemul_hw_map.videoram; |
303 | addr = (char *) gxemul_hw_map.videoram; |
305 | } |
304 | } |
306 | 305 | ||
307 | *(addr) = ch; |
306 | *(addr) = ch; |
308 | } |
307 | } |
309 | 308 | ||
310 | void machine_cpu_halt(void) |
309 | void machine_cpu_halt(void) |
311 | { |
310 | { |
312 | char * addr = 0; |
311 | char * addr = 0; |
313 | if (!hw_map_init_called) { |
312 | if (!hw_map_init_called) { |
314 | addr = (char *) GXEMUL_KBD; |
313 | addr = (char *) GXEMUL_KBD; |
315 | } else { |
314 | } else { |
316 | addr = (char *) gxemul_hw_map.videoram; |
315 | addr = (char *) gxemul_hw_map.videoram; |
317 | } |
316 | } |
318 | 317 | ||
319 | *(addr + GXEMUL_HALT_OFFSET) = '\0'; |
318 | *(addr + GXEMUL_HALT_OFFSET) = '\0'; |
320 | } |
319 | } |
321 | 320 | ||
322 | void machine_irq_exception(int exc_no, istate_t *istate) |
321 | void machine_irq_exception(int exc_no, istate_t *istate) |
323 | { |
322 | { |
- | 323 | /* switch to Undefined mode */ |
|
- | 324 | /* |
|
- | 325 | asm volatile( |
|
- | 326 | "stmfd sp!, {r0-r3}\n" |
|
- | 327 | "mov r1, sp\n" |
|
- | 328 | "mov r2, lr\n" |
|
- | 329 | "mrs r3, spsr\n" |
|
- | 330 | "mrs r0, cpsr\n" |
|
- | 331 | "bic r0, r0, #0x1f\n" |
|
- | 332 | "orr r0, r0, #0x1b\n" |
|
- | 333 | "msr cpsr_c, r0\n" |
|
- | 334 | "mov sp, r1\n" |
|
- | 335 | "mov lr, r2\n" |
|
- | 336 | "msr spsr, r3\n" |
|
- | 337 | "ldmfd sp!, {r0-r3}\n" |
|
- | 338 | ); |
|
- | 339 | */ |
|
- | 340 | ||
324 | uint32_t sources = gxemul_irqc_get_sources(); |
341 | uint32_t sources = gxemul_irqc_get_sources(); |
325 | int i = 0; |
342 | int i = 0; |
326 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
343 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
327 | if (sources & (1 << i)) { |
344 | if (sources & (1 << i)) { |
328 | irq_t *irq = irq_dispatch_and_lock(i); |
345 | irq_t *irq = irq_dispatch_and_lock(i); |
329 | if (irq) { |
346 | if (irq) { |
330 | /* The IRQ handler was found. */ |
347 | /* The IRQ handler was found. */ |
331 | irq->handler(irq, irq->arg); |
348 | irq->handler(irq, irq->arg); |
332 | spinlock_unlock(&irq->lock); |
349 | spinlock_unlock(&irq->lock); |
333 | } else { |
350 | } else { |
334 | /* Spurious interrupt.*/ |
351 | /* Spurious interrupt.*/ |
335 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
352 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
336 | } |
353 | } |
337 | } |
354 | } |
338 | } |
355 | } |
339 | /* TODO remove after testing the above code |
356 | /* TODO remove after testing the above code |
340 | noirq = 0; |
357 | noirq = 0; |
341 | if (i == CONSOLE_IRQ) { |
358 | if (i == CONSOLE_IRQ) { |
342 | char readchar = *(char*)0x10000000; |
359 | char readchar = *(char*)0x10000000; |
343 | if (readchar == 0) { |
360 | if (readchar == 0) { |
344 | aux_puts("?"); |
361 | aux_puts("?"); |
345 | } |
362 | } |
346 | else { |
363 | else { |
347 | dprintf("%c", readchar); |
364 | dprintf("%c", readchar); |
348 | } |
365 | } |
349 | |
366 | |
350 | } |
367 | } |
351 | else if (i == TIMER_IRQ) { |
368 | else if (i == TIMER_IRQ) { |
352 | dprintf("\n.\n"); |
369 | dprintf("\n.\n"); |
353 | //acknowledge |
370 | //acknowledge |
354 | *(uint32_t*)0x15000110 = 0; |
371 | *(uint32_t*)0x15000110 = 0; |
355 | } |
372 | } |
356 | } |
373 | } |
357 | } |
374 | } |
358 | 375 | ||
359 | if (noirq) |
376 | if (noirq) |
360 | aux_puts("IRQ exception without source\n");*/ |
377 | aux_puts("IRQ exception without source\n");*/ |
361 | } |
378 | } |
362 | 379 | ||
- | 380 | ||
363 | /** @} |
381 | /** @} |
364 | */ |
382 | */ |
365 | 383 |