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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Paging related declarations. |
33 | * @brief Paging related declarations. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #ifndef KERN_arm32_PAGE_H_ |
36 | #ifndef KERN_arm32_PAGE_H_ |
37 | #define KERN_arm32_PAGE_H_ |
37 | #define KERN_arm32_PAGE_H_ |
38 | 38 | ||
39 | #include <arch/mm/frame.h> |
39 | #include <arch/mm/frame.h> |
40 | #include <mm/mm.h> |
40 | #include <mm/mm.h> |
41 | #include <arch/exception.h> |
41 | #include <arch/exception.h> |
42 | 42 | ||
43 | #define PAGE_WIDTH FRAME_WIDTH |
43 | #define PAGE_WIDTH FRAME_WIDTH |
44 | #define PAGE_SIZE FRAME_SIZE |
44 | #define PAGE_SIZE FRAME_SIZE |
45 | 45 | ||
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
47 | 47 | ||
48 | #ifndef __ASM__ |
48 | #ifndef __ASM__ |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
51 | #else |
51 | #else |
52 | # define KA2PA(x) ((x) - 0x80000000) |
52 | # define KA2PA(x) ((x) - 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
54 | #endif |
54 | #endif |
55 | 55 | ||
56 | #ifdef KERNEL |
56 | #ifdef KERNEL |
57 | 57 | ||
58 | /* Number of entries in each level. */ |
58 | /* Number of entries in each level. */ |
59 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
59 | #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ |
60 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL1_ENTRIES_ARCH 0 |
61 | #define PTL2_ENTRIES_ARCH 0 |
61 | #define PTL2_ENTRIES_ARCH 0 |
62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
62 | /* coarse page tables used (256 * 4 = 1KB per page) */ |
63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
63 | #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ |
64 | 64 | ||
65 | /* Page table sizes for each level. */ |
65 | /* Page table sizes for each level. */ |
66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
66 | #define PTL0_SIZE_ARCH FOUR_FRAMES |
67 | #define PTL1_SIZE_ARCH 0 |
67 | #define PTL1_SIZE_ARCH 0 |
68 | #define PTL2_SIZE_ARCH 0 |
68 | #define PTL2_SIZE_ARCH 0 |
69 | #define PTL3_SIZE_ARCH ONE_FRAME |
69 | #define PTL3_SIZE_ARCH ONE_FRAME |
70 | 70 | ||
71 | /* Macros calculating indices into page tables for each level. */ |
71 | /* Macros calculating indices into page tables for each level. */ |
72 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
72 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
73 | #define PTL1_INDEX_ARCH(vaddr) 0 |
73 | #define PTL1_INDEX_ARCH(vaddr) 0 |
74 | #define PTL2_INDEX_ARCH(vaddr) 0 |
74 | #define PTL2_INDEX_ARCH(vaddr) 0 |
75 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
75 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
76 | 76 | ||
77 | /* Get PTE address accessors for each level. */ |
77 | /* Get PTE address accessors for each level. */ |
78 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
78 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ |
79 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
79 | ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) |
80 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
80 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ |
81 | (ptl1) |
81 | (ptl1) |
82 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
82 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ |
83 | (ptl2) |
83 | (ptl2) |
84 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
84 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ |
85 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
85 | ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) |
86 | 86 | ||
87 | /* Set PTE address accessors for each level. */ |
87 | /* Set PTE address accessors for each level. */ |
88 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
88 | #define SET_PTL0_ADDRESS_ARCH(ptl0) \ |
89 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
89 | (set_ptl0_addr((pte_level0_t *) (ptl0))) |
90 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
90 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ |
91 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
91 | (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) |
92 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
92 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
93 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
93 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
94 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
94 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ |
95 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
95 | (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) |
96 | 96 | ||
97 | /* Get PTE flags accessors for each level. */ |
97 | /* Get PTE flags accessors for each level. */ |
98 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
98 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ |
99 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
99 | get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) |
100 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
100 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ |
101 | PAGE_PRESENT |
101 | PAGE_PRESENT |
102 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
102 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ |
103 | PAGE_PRESENT |
103 | PAGE_PRESENT |
104 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
104 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ |
105 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
105 | get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) |
106 | 106 | ||
107 | /* Set PTE flags accessors for each level. */ |
107 | /* Set PTE flags accessors for each level. */ |
108 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
108 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ |
109 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
109 | set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) |
110 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
110 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
111 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
111 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
112 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
112 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ |
113 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
113 | set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) |
114 | 114 | ||
115 | /* Macros for querying the last-level PTE entries. */ |
115 | /* Macros for querying the last-level PTE entries. */ |
116 | #define PTE_VALID_ARCH(pte) \ |
116 | #define PTE_VALID_ARCH(pte) \ |
117 | (*((uint32_t *) (pte)) != 0) |
117 | (*((uint32_t *) (pte)) != 0) |
118 | #define PTE_PRESENT_ARCH(pte) \ |
118 | #define PTE_PRESENT_ARCH(pte) \ |
119 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
119 | (((pte_level0_t *) (pte))->descriptor_type != 0) |
120 | #define PTE_GET_FRAME_ARCH(pte) \ |
120 | #define PTE_GET_FRAME_ARCH(pte) \ |
121 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
121 | (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) |
122 | #define PTE_WRITABLE_ARCH(pte) \ |
122 | #define PTE_WRITABLE_ARCH(pte) \ |
123 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
123 | (((pte_level1_t *) (pte))->access_permission_0 == \ |
124 | PTE_AP_USER_RW_KERNEL_RW) |
124 | PTE_AP_USER_RW_KERNEL_RW) |
125 | #define PTE_EXECUTABLE_ARCH(pte) \ |
125 | #define PTE_EXECUTABLE_ARCH(pte) \ |
126 | 1 |
126 | 1 |
127 | 127 | ||
128 | #ifndef __ASM__ |
128 | #ifndef __ASM__ |
129 | 129 | ||
130 | /** Level 0 page table entry. */ |
130 | /** Level 0 page table entry. */ |
131 | typedef struct { |
131 | typedef struct { |
132 | /* 0b01 for coarse tables, see below for details */ |
132 | /* 0b01 for coarse tables, see below for details */ |
133 | unsigned descriptor_type : 2; |
133 | unsigned descriptor_type : 2; |
134 | unsigned impl_specific : 3; |
134 | unsigned impl_specific : 3; |
135 | unsigned domain : 4; |
135 | unsigned domain : 4; |
136 | unsigned should_be_zero : 1; |
136 | unsigned should_be_zero : 1; |
137 | 137 | ||
138 | /* Pointer to the coarse 2nd level page table (holding entries for small |
138 | /* Pointer to the coarse 2nd level page table (holding entries for small |
139 | * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
139 | * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page |
140 | * tables that may hold even tiny pages (1KB) but they are bigger (4KB |
140 | * tables that may hold even tiny pages (1KB) but they are bigger (4KB |
141 | * per table in comparison with 1KB per the coarse table) |
141 | * per table in comparison with 1KB per the coarse table) |
142 | */ |
142 | */ |
143 | unsigned coarse_table_addr : 22; |
143 | unsigned coarse_table_addr : 22; |
144 | } ATTRIBUTE_PACKED pte_level0_t; |
144 | } ATTRIBUTE_PACKED pte_level0_t; |
145 | 145 | ||
146 | /** Level 1 page table entry (small (4KB) pages used). */ |
146 | /** Level 1 page table entry (small (4KB) pages used). */ |
147 | typedef struct { |
147 | typedef struct { |
148 | 148 | ||
149 | /* 0b10 for small pages */ |
149 | /* 0b10 for small pages */ |
150 | unsigned descriptor_type : 2; |
150 | unsigned descriptor_type : 2; |
151 | unsigned bufferable : 1; |
151 | unsigned bufferable : 1; |
152 | unsigned cacheable : 1; |
152 | unsigned cacheable : 1; |
153 | 153 | ||
154 | /* access permissions for each of 4 subparts of a page |
154 | /* access permissions for each of 4 subparts of a page |
155 | * (for each 1KB when small pages used */ |
155 | * (for each 1KB when small pages used */ |
156 | unsigned access_permission_0 : 2; |
156 | unsigned access_permission_0 : 2; |
157 | unsigned access_permission_1 : 2; |
157 | unsigned access_permission_1 : 2; |
158 | unsigned access_permission_2 : 2; |
158 | unsigned access_permission_2 : 2; |
159 | unsigned access_permission_3 : 2; |
159 | unsigned access_permission_3 : 2; |
160 | unsigned frame_base_addr : 20; |
160 | unsigned frame_base_addr : 20; |
161 | } ATTRIBUTE_PACKED pte_level1_t; |
161 | } ATTRIBUTE_PACKED pte_level1_t; |
162 | 162 | ||
163 | 163 | ||
164 | /* Level 1 page tables access permissions */ |
164 | /* Level 1 page tables access permissions */ |
165 | 165 | ||
166 | /** User mode: no access, privileged mode: no access. */ |
166 | /** User mode: no access, privileged mode: no access. */ |
167 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
167 | #define PTE_AP_USER_NO_KERNEL_NO 0 |
168 | 168 | ||
169 | /** User mode: no access, privileged mode: read/write. */ |
169 | /** User mode: no access, privileged mode: read/write. */ |
170 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
170 | #define PTE_AP_USER_NO_KERNEL_RW 1 |
171 | 171 | ||
172 | /** User mode: read only, privileged mode: read/write. */ |
172 | /** User mode: read only, privileged mode: read/write. */ |
173 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
173 | #define PTE_AP_USER_RO_KERNEL_RW 2 |
174 | 174 | ||
175 | /** User mode: read/write, privileged mode: read/write. */ |
175 | /** User mode: read/write, privileged mode: read/write. */ |
176 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
176 | #define PTE_AP_USER_RW_KERNEL_RW 3 |
177 | 177 | ||
178 | 178 | ||
179 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
179 | /* pte_level0_t and pte_level1_t descriptor_type flags */ |
180 | 180 | ||
181 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
181 | /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
182 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
182 | #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
183 | 183 | ||
184 | /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
184 | /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
185 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
185 | #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
186 | 186 | ||
187 | /** pte_level1_t small page table flag (used in descriptor type). */ |
187 | /** pte_level1_t small page table flag (used in descriptor type). */ |
188 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
188 | #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
189 | 189 | ||
190 | 190 | ||
191 | /** Sets the address of level 0 page table. |
191 | /** Sets the address of level 0 page table. |
192 | * |
192 | * |
193 | * @param pt Pointer to the page table to set. |
193 | * @param pt Pointer to the page table to set. |
194 | */ |
194 | */ |
195 | static inline void set_ptl0_addr(pte_level0_t *pt) |
195 | static inline void set_ptl0_addr(pte_level0_t *pt) |
196 | { |
196 | { |
197 | asm volatile ( |
197 | asm volatile ( |
198 | "mcr p15, 0, %0, c2, c0, 0 \n" |
198 | "mcr p15, 0, %0, c2, c0, 0 \n" |
199 | : |
199 | : |
200 | : "r"(pt) |
200 | : "r"(pt) |
201 | ); |
201 | ); |
202 | } |
202 | } |
203 | 203 | ||
204 | 204 | ||
205 | /** Returns level 0 page table entry flags. |
205 | /** Returns level 0 page table entry flags. |
206 | * |
206 | * |
207 | * @param pt Level 0 page table. |
207 | * @param pt Level 0 page table. |
208 | * @param i Index of the entry to return. |
208 | * @param i Index of the entry to return. |
209 | */ |
209 | */ |
210 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
210 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
211 | { |
211 | { |
212 | pte_level0_t *p = &pt[i]; |
212 | pte_level0_t *p = &pt[i]; |
213 | int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
213 | int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); |
214 | 214 | ||
215 | return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
215 | return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | |
216 | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
216 | (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | |
217 | (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
217 | (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); |
218 | } |
218 | } |
219 | 219 | ||
220 | /** Returns level 1 page table entry flags. |
220 | /** Returns level 1 page table entry flags. |
221 | * |
221 | * |
222 | * @param pt Level 1 page table. |
222 | * @param pt Level 1 page table. |
223 | * @param i Index of the entry to return. |
223 | * @param i Index of the entry to return. |
224 | */ |
224 | */ |
225 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
225 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
226 | { |
226 | { |
227 | pte_level1_t *p = &pt[i]; |
227 | pte_level1_t *p = &pt[i]; |
228 | 228 | ||
229 | int dt = p->descriptor_type; |
229 | int dt = p->descriptor_type; |
230 | int ap = p->access_permission_0; |
230 | int ap = p->access_permission_0; |
231 | 231 | ||
232 | return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
232 | return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | |
233 | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
233 | ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | |
234 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
234 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | |
235 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
235 | ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
236 | ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
236 | ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | |
237 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
237 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | |
238 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
238 | ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | |
239 | (1 << PAGE_EXEC_SHIFT) | |
239 | (1 << PAGE_EXEC_SHIFT) | |
240 | (p->bufferable << PAGE_CACHEABLE); |
240 | (p->bufferable << PAGE_CACHEABLE); |
241 | } |
241 | } |
242 | 242 | ||
243 | 243 | ||
244 | /** Sets flags of level 0 page table entry. |
244 | /** Sets flags of level 0 page table entry. |
245 | * |
245 | * |
246 | * @param pt level 0 page table |
246 | * @param pt level 0 page table |
247 | * @param i index of the entry to be changed |
247 | * @param i index of the entry to be changed |
248 | * @param flags new flags |
248 | * @param flags new flags |
249 | */ |
249 | */ |
250 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
250 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
251 | { |
251 | { |
252 | pte_level0_t *p = &pt[i]; |
252 | pte_level0_t *p = &pt[i]; |
253 | 253 | ||
254 | if (flags & PAGE_NOT_PRESENT) { |
254 | if (flags & PAGE_NOT_PRESENT) { |
255 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
255 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
256 | /* |
256 | /* |
257 | * Ensures that the entry will be recognized as valid when |
257 | * Ensures that the entry will be recognized as valid when |
258 | * PTE_VALID_ARCH applied. |
258 | * PTE_VALID_ARCH applied. |
259 | */ |
259 | */ |
260 | p->should_be_zero = 1; |
260 | p->should_be_zero = 1; |
261 | } else { |
261 | } else { |
262 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
262 | p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; |
263 | p->should_be_zero = 0; |
263 | p->should_be_zero = 0; |
264 | } |
264 | } |
265 | } |
265 | } |
266 | 266 | ||
267 | 267 | ||
268 | /** Sets flags of level 1 page table entry. |
268 | /** Sets flags of level 1 page table entry. |
269 | * |
269 | * |
270 | * We use same access rights for the whole page. When page is not preset we |
270 | * We use same access rights for the whole page. When page is not preset we |
271 | * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
271 | * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct |
272 | * page entry, see #PAGE_VALID_ARCH). |
272 | * page entry, see #PAGE_VALID_ARCH). |
273 | * |
273 | * |
274 | * @param pt Level 1 page table. |
274 | * @param pt Level 1 page table. |
275 | * @param i Index of the entry to be changed. |
275 | * @param i Index of the entry to be changed. |
276 | * @param flags New flags. |
276 | * @param flags New flags. |
277 | */ |
277 | */ |
278 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
278 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
279 | { |
279 | { |
280 | pte_level1_t *p = &pt[i]; |
280 | pte_level1_t *p = &pt[i]; |
281 | 281 | ||
282 | if (flags & PAGE_NOT_PRESENT) { |
282 | if (flags & PAGE_NOT_PRESENT) { |
283 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
283 | p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; |
284 | p->access_permission_3 = 1; |
284 | p->access_permission_3 = 1; |
285 | } else { |
285 | } else { |
286 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
286 | p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; |
287 | p->access_permission_3 = p->access_permission_0; |
287 | p->access_permission_3 = p->access_permission_0; |
288 | } |
288 | } |
289 | 289 | ||
290 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
290 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
291 | 291 | ||
292 | /* default access permission */ |
292 | /* default access permission */ |
293 | p->access_permission_0 = p->access_permission_1 = |
293 | p->access_permission_0 = p->access_permission_1 = |
294 | p->access_permission_2 = p->access_permission_3 = |
294 | p->access_permission_2 = p->access_permission_3 = |
295 | PTE_AP_USER_NO_KERNEL_RW; |
295 | PTE_AP_USER_NO_KERNEL_RW; |
296 | 296 | ||
297 | if (flags & PAGE_USER) { |
297 | if (flags & PAGE_USER) { |
298 | if (flags & PAGE_READ) { |
298 | if (flags & PAGE_READ) { |
299 | p->access_permission_0 = p->access_permission_1 = |
299 | p->access_permission_0 = p->access_permission_1 = |
300 | p->access_permission_2 = p->access_permission_3 = |
300 | p->access_permission_2 = p->access_permission_3 = |
301 | PTE_AP_USER_RO_KERNEL_RW; |
301 | PTE_AP_USER_RO_KERNEL_RW; |
302 | } |
302 | } |
303 | if (flags & PAGE_WRITE) { |
303 | if (flags & PAGE_WRITE) { |
304 | p->access_permission_0 = p->access_permission_1 = |
304 | p->access_permission_0 = p->access_permission_1 = |
305 | p->access_permission_2 = p->access_permission_3 = |
305 | p->access_permission_2 = p->access_permission_3 = |
306 | PTE_AP_USER_RW_KERNEL_RW; |
306 | PTE_AP_USER_RW_KERNEL_RW; |
307 | } |
307 | } |
308 | } |
308 | } |
309 | } |
309 | } |
310 | 310 | ||
311 | 311 | ||
312 | extern void page_arch_init(void); |
312 | extern void page_arch_init(void); |
313 | 313 | ||
314 | 314 | ||
315 | #endif /* __ASM__ */ |
315 | #endif /* __ASM__ */ |
316 | 316 | ||
317 | #endif /* KERNEL */ |
317 | #endif /* KERNEL */ |
318 | 318 | ||
319 | #endif |
319 | #endif |
320 | 320 | ||
321 | /** @} |
321 | /** @} |
322 | */ |
322 | */ |
323 | 323 |