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1
/*
1
/*
2
 * Copyright (C) 2001-2004 Jakub Jermar
2
 * Copyright (C) 2001-2004 Jakub Jermar
3
 * Copyright (C) 2005-2006 Ondrej Palkovsky
3
 * Copyright (C) 2005-2006 Ondrej Palkovsky
4
 * All rights reserved.
4
 * All rights reserved.
5
 *
5
 *
6
 * Redistribution and use in source and binary forms, with or without
6
 * Redistribution and use in source and binary forms, with or without
7
 * modification, are permitted provided that the following conditions
7
 * modification, are permitted provided that the following conditions
8
 * are met:
8
 * are met:
9
 *
9
 *
10
 * - Redistributions of source code must retain the above copyright
10
 * - Redistributions of source code must retain the above copyright
11
 *   notice, this list of conditions and the following disclaimer.
11
 *   notice, this list of conditions and the following disclaimer.
12
 * - Redistributions in binary form must reproduce the above copyright
12
 * - Redistributions in binary form must reproduce the above copyright
13
 *   notice, this list of conditions and the following disclaimer in the
13
 *   notice, this list of conditions and the following disclaimer in the
14
 *   documentation and/or other materials provided with the distribution.
14
 *   documentation and/or other materials provided with the distribution.
15
 * - The name of the author may not be used to endorse or promote products
15
 * - The name of the author may not be used to endorse or promote products
16
 *   derived from this software without specific prior written permission.
16
 *   derived from this software without specific prior written permission.
17
 *
17
 *
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
 */
28
 */
29
 
29
 
-
 
30
 /** @addtogroup amd64 
-
 
31
 * @{
-
 
32
 */
-
 
33
/** @file
-
 
34
 */
-
 
35
 
30
#include <arch/pm.h>
36
#include <arch/pm.h>
31
#include <arch/mm/page.h>
37
#include <arch/mm/page.h>
32
#include <arch/types.h>
38
#include <arch/types.h>
33
#include <arch/interrupt.h>
39
#include <arch/interrupt.h>
34
#include <arch/asm.h>
40
#include <arch/asm.h>
35
#include <interrupt.h>
41
#include <interrupt.h>
36
#include <mm/as.h>
42
#include <mm/as.h>
37
 
43
 
38
#include <config.h>
44
#include <config.h>
39
 
45
 
40
#include <memstr.h>
46
#include <memstr.h>
41
#include <mm/slab.h>
47
#include <mm/slab.h>
42
#include <debug.h>
48
#include <debug.h>
43
 
49
 
44
/*
50
/*
45
 * There is no segmentation in long mode so we set up flat mode. In this
51
 * There is no segmentation in long mode so we set up flat mode. In this
46
 * mode, we use, for each privilege level, two segments spanning the
52
 * mode, we use, for each privilege level, two segments spanning the
47
 * whole memory. One is for code and one is for data.
53
 * whole memory. One is for code and one is for data.
48
 */
54
 */
49
 
55
 
50
descriptor_t gdt[GDT_ITEMS] = {
56
descriptor_t gdt[GDT_ITEMS] = {
51
    /* NULL descriptor */
57
    /* NULL descriptor */
52
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
58
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
53
    /* KTEXT descriptor */
59
    /* KTEXT descriptor */
54
    { .limit_0_15  = 0xffff,
60
    { .limit_0_15  = 0xffff,
55
      .base_0_15   = 0,
61
      .base_0_15   = 0,
56
      .base_16_23  = 0,
62
      .base_16_23  = 0,
57
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
63
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
58
      .limit_16_19 = 0xf,
64
      .limit_16_19 = 0xf,
59
      .available   = 0,
65
      .available   = 0,
60
      .longmode    = 1,
66
      .longmode    = 1,
61
      .special     = 0,
67
      .special     = 0,
62
      .granularity = 1,
68
      .granularity = 1,
63
      .base_24_31  = 0 },
69
      .base_24_31  = 0 },
64
    /* KDATA descriptor */
70
    /* KDATA descriptor */
65
    { .limit_0_15  = 0xffff,
71
    { .limit_0_15  = 0xffff,
66
      .base_0_15   = 0,
72
      .base_0_15   = 0,
67
      .base_16_23  = 0,
73
      .base_16_23  = 0,
68
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
74
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
69
      .limit_16_19 = 0xf,
75
      .limit_16_19 = 0xf,
70
      .available   = 0,
76
      .available   = 0,
71
      .longmode    = 0,
77
      .longmode    = 0,
72
      .special     = 0,
78
      .special     = 0,
73
      .granularity = 1,
79
      .granularity = 1,
74
      .base_24_31  = 0 },
80
      .base_24_31  = 0 },
75
    /* UDATA descriptor */
81
    /* UDATA descriptor */
76
    { .limit_0_15  = 0xffff,
82
    { .limit_0_15  = 0xffff,
77
      .base_0_15   = 0,
83
      .base_0_15   = 0,
78
      .base_16_23  = 0,
84
      .base_16_23  = 0,
79
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
85
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
80
      .limit_16_19 = 0xf,
86
      .limit_16_19 = 0xf,
81
      .available   = 0,
87
      .available   = 0,
82
      .longmode    = 0,
88
      .longmode    = 0,
83
      .special     = 1,
89
      .special     = 1,
84
      .granularity = 1,
90
      .granularity = 1,
85
      .base_24_31  = 0 },
91
      .base_24_31  = 0 },
86
    /* UTEXT descriptor */
92
    /* UTEXT descriptor */
87
    { .limit_0_15  = 0xffff,
93
    { .limit_0_15  = 0xffff,
88
      .base_0_15   = 0,
94
      .base_0_15   = 0,
89
      .base_16_23  = 0,
95
      .base_16_23  = 0,
90
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
96
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
91
      .limit_16_19 = 0xf,
97
      .limit_16_19 = 0xf,
92
      .available   = 0,
98
      .available   = 0,
93
      .longmode    = 1,
99
      .longmode    = 1,
94
      .special     = 0,
100
      .special     = 0,
95
      .granularity = 1,
101
      .granularity = 1,
96
      .base_24_31  = 0 },
102
      .base_24_31  = 0 },
97
    /* KTEXT 32-bit protected, for protected mode before long mode */
103
    /* KTEXT 32-bit protected, for protected mode before long mode */
98
    { .limit_0_15  = 0xffff,
104
    { .limit_0_15  = 0xffff,
99
      .base_0_15   = 0,
105
      .base_0_15   = 0,
100
      .base_16_23  = 0,
106
      .base_16_23  = 0,
101
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
107
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
102
      .limit_16_19 = 0xf,
108
      .limit_16_19 = 0xf,
103
      .available   = 0,
109
      .available   = 0,
104
      .longmode    = 0,
110
      .longmode    = 0,
105
      .special     = 1,
111
      .special     = 1,
106
      .granularity = 1,
112
      .granularity = 1,
107
      .base_24_31  = 0 },
113
      .base_24_31  = 0 },
108
    /* TSS descriptor - set up will be completed later,
114
    /* TSS descriptor - set up will be completed later,
109
     * on AMD64 it is 64-bit - 2 items in table */
115
     * on AMD64 it is 64-bit - 2 items in table */
110
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
116
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
111
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
117
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
112
    /* VESA Init descriptor */
118
    /* VESA Init descriptor */
113
#ifdef CONFIG_FB    
119
#ifdef CONFIG_FB    
114
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
120
    { 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
115
#endif
121
#endif
116
};
122
};
117
 
123
 
118
idescriptor_t idt[IDT_ITEMS];
124
idescriptor_t idt[IDT_ITEMS];
119
 
125
 
120
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
126
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
121
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
127
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
122
 
128
 
123
static tss_t tss;
129
static tss_t tss;
124
tss_t *tss_p = NULL;
130
tss_t *tss_p = NULL;
125
 
131
 
126
void gdt_tss_setbase(descriptor_t *d, __address base)
132
void gdt_tss_setbase(descriptor_t *d, __address base)
127
{
133
{
128
    tss_descriptor_t *td = (tss_descriptor_t *) d;
134
    tss_descriptor_t *td = (tss_descriptor_t *) d;
129
 
135
 
130
    td->base_0_15 = base & 0xffff;
136
    td->base_0_15 = base & 0xffff;
131
    td->base_16_23 = ((base) >> 16) & 0xff;
137
    td->base_16_23 = ((base) >> 16) & 0xff;
132
    td->base_24_31 = ((base) >> 24) & 0xff;
138
    td->base_24_31 = ((base) >> 24) & 0xff;
133
    td->base_32_63 = ((base) >> 32);
139
    td->base_32_63 = ((base) >> 32);
134
}
140
}
135
 
141
 
136
void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
142
void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
137
{
143
{
138
    struct tss_descriptor *td = (tss_descriptor_t *) d;
144
    struct tss_descriptor *td = (tss_descriptor_t *) d;
139
 
145
 
140
    td->limit_0_15 = limit & 0xffff;
146
    td->limit_0_15 = limit & 0xffff;
141
    td->limit_16_19 = (limit >> 16) & 0xf;
147
    td->limit_16_19 = (limit >> 16) & 0xf;
142
}
148
}
143
 
149
 
144
void idt_setoffset(idescriptor_t *d, __address offset)
150
void idt_setoffset(idescriptor_t *d, __address offset)
145
{
151
{
146
    /*
152
    /*
147
     * Offset is a linear address.
153
     * Offset is a linear address.
148
     */
154
     */
149
    d->offset_0_15 = offset & 0xffff;
155
    d->offset_0_15 = offset & 0xffff;
150
    d->offset_16_31 = offset >> 16 & 0xffff;
156
    d->offset_16_31 = offset >> 16 & 0xffff;
151
    d->offset_32_63 = offset >> 32;
157
    d->offset_32_63 = offset >> 32;
152
}
158
}
153
 
159
 
154
void tss_initialize(tss_t *t)
160
void tss_initialize(tss_t *t)
155
{
161
{
156
    memsetb((__address) t, sizeof(tss_t), 0);
162
    memsetb((__address) t, sizeof(tss_t), 0);
157
}
163
}
158
 
164
 
159
/*
165
/*
160
 * This function takes care of proper setup of IDT and IDTR.
166
 * This function takes care of proper setup of IDT and IDTR.
161
 */
167
 */
162
void idt_init(void)
168
void idt_init(void)
163
{
169
{
164
    idescriptor_t *d;
170
    idescriptor_t *d;
165
    int i;
171
    int i;
166
 
172
 
167
    for (i = 0; i < IDT_ITEMS; i++) {
173
    for (i = 0; i < IDT_ITEMS; i++) {
168
        d = &idt[i];
174
        d = &idt[i];
169
 
175
 
170
        d->unused = 0;
176
        d->unused = 0;
171
        d->selector = gdtselector(KTEXT_DES);
177
        d->selector = gdtselector(KTEXT_DES);
172
 
178
 
173
        d->present = 1;
179
        d->present = 1;
174
        d->type = AR_INTERRUPT; /* masking interrupt */
180
        d->type = AR_INTERRUPT; /* masking interrupt */
175
 
181
 
176
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
182
        idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
177
        exc_register(i, "undef", (iroutine)null_interrupt);
183
        exc_register(i, "undef", (iroutine)null_interrupt);
178
    }
184
    }
179
 
185
 
180
    exc_register( 7, "nm_fault", nm_fault);
186
    exc_register( 7, "nm_fault", nm_fault);
181
    exc_register(12, "ss_fault", ss_fault);
187
    exc_register(12, "ss_fault", ss_fault);
182
    exc_register(13, "gp_fault", gp_fault);
188
    exc_register(13, "gp_fault", gp_fault);
183
    exc_register(14, "ident_mapper", ident_page_fault);
189
    exc_register(14, "ident_mapper", ident_page_fault);
184
}
190
}
185
 
191
 
186
/** Initialize segmentation - code/data/idt tables
192
/** Initialize segmentation - code/data/idt tables
187
 *
193
 *
188
 */
194
 */
189
void pm_init(void)
195
void pm_init(void)
190
{
196
{
191
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
197
    descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
192
    tss_descriptor_t *tss_desc;
198
    tss_descriptor_t *tss_desc;
193
 
199
 
194
    /*
200
    /*
195
     * Each CPU has its private GDT and TSS.
201
     * Each CPU has its private GDT and TSS.
196
     * All CPUs share one IDT.
202
     * All CPUs share one IDT.
197
     */
203
     */
198
 
204
 
199
    if (config.cpu_active == 1) {
205
    if (config.cpu_active == 1) {
200
        idt_init();
206
        idt_init();
201
        /*
207
        /*
202
         * NOTE: bootstrap CPU has statically allocated TSS, because
208
         * NOTE: bootstrap CPU has statically allocated TSS, because
203
         * the heap hasn't been initialized so far.
209
         * the heap hasn't been initialized so far.
204
         */
210
         */
205
        tss_p = &tss;
211
        tss_p = &tss;
206
    }
212
    }
207
    else {
213
    else {
208
        /* We are going to use malloc, which may return
214
        /* We are going to use malloc, which may return
209
         * non boot-mapped pointer, initialize the CR3 register
215
         * non boot-mapped pointer, initialize the CR3 register
210
         * ahead of page_init */
216
         * ahead of page_init */
211
        write_cr3((__address) AS_KERNEL->page_table);
217
        write_cr3((__address) AS_KERNEL->page_table);
212
 
218
 
213
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
219
        tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
214
        if (!tss_p)
220
        if (!tss_p)
215
            panic("could not allocate TSS\n");
221
            panic("could not allocate TSS\n");
216
    }
222
    }
217
 
223
 
218
    tss_initialize(tss_p);
224
    tss_initialize(tss_p);
219
 
225
 
220
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
226
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
221
    tss_desc->present = 1;
227
    tss_desc->present = 1;
222
    tss_desc->type = AR_TSS;
228
    tss_desc->type = AR_TSS;
223
    tss_desc->dpl = PL_KERNEL;
229
    tss_desc->dpl = PL_KERNEL;
224
   
230
   
225
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
231
    gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
226
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
232
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
227
 
233
 
228
    gdtr_load(&gdtr);
234
    gdtr_load(&gdtr);
229
    idtr_load(&idtr);
235
    idtr_load(&idtr);
230
    /*
236
    /*
231
     * As of this moment, the current CPU has its own GDT pointing
237
     * As of this moment, the current CPU has its own GDT pointing
232
     * to its own TSS. We just need to load the TR register.
238
     * to its own TSS. We just need to load the TR register.
233
     */
239
     */
234
    tr_load(gdtselector(TSS_DES));
240
    tr_load(gdtselector(TSS_DES));
235
}
241
}
-
 
242
 
-
 
243
 /** @}
-
 
244
 */
-
 
245
 
236
 
246