WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/amd64/src/cpu/cpu.c


/*
 * Copyright (c) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64
 * @{
 */
/** @file
 */
 
#include <cpu.h>
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
 
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <fpu_context.h>
 
/*
 * Identification of CPUs.
 * Contains only non-MP-Specification specific SMP code.
 */
#define AMD_CPUID_EBX   0x68747541
#define AMD_CPUID_ECX   0x444d4163
#define AMD_CPUID_EDX   0x69746e65
 
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
 
 
enum vendor {
    VendorUnknown = 0,
    VendorAMD,
    VendorIntel
};
 
static char *vendor_str[] = {
    "Unknown Vendor",
    "AuthenticAMD",
    "GenuineIntel"
};
 
 
/** Setup flags on processor so that we can use the FPU
 *
 * cr0.osfxsr = 1 -> we do support fxstor/fxrestor
 * cr0.em = 0 -> we do not emulate coprocessor
 * cr0.mp = 1 -> we do want lazy context switch
 */
void cpu_setup_fpu(void)
{
    asm volatile (
        "movq %%cr0, %%rax;"
        "btsq $1, %%rax;" /* cr0.mp */
        "btrq $2, %%rax;"  /* cr0.em */
        "movq %%rax, %%cr0;"
 
        "movq %%cr4, %%rax;"
        "bts $9, %%rax;" /* cr4.osfxsr */
        "movq %%rax, %%cr4;"
        :
        :
        :"%rax"
        );
}
 
/** Set the TS flag to 1.
 *
 * If a thread accesses coprocessor, exception is run, which
 * does a lazy fpu context switch.
 *
 */
void fpu_disable(void)
{
    asm volatile (
        "mov %%cr0,%%rax;"
        "bts $3,%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
        );
}
 
void fpu_enable(void)
{
    asm volatile (
        "mov %%cr0,%%rax;"
        "btr $3,%%rax;"
        "mov %%rax,%%cr0;"
        :
        :
        :"%rax"
        ); 
}
 
void cpu_arch_init(void)
{
    CPU->arch.tss = tss_p;
    CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
        ((uint8_t *) CPU->arch.tss);
    CPU->fpu_owner = NULL;
}
 
void cpu_identify(void)
{
    cpu_info_t info;
 
    CPU->arch.vendor = VendorUnknown;
    if (has_cpuid()) {
        cpuid(0, &info);
 
        /*
         * Check for AMD processor.
         */
        if (info.cpuid_ebx == AMD_CPUID_EBX &&
            info.cpuid_ecx == AMD_CPUID_ECX &&
            info.cpuid_edx == AMD_CPUID_EDX) {
            CPU->arch.vendor = VendorAMD;
        }
 
        /*
         * Check for Intel processor.
         */    
        if (info.cpuid_ebx == INTEL_CPUID_EBX &&
            info.cpuid_ecx == INTEL_CPUID_ECX &&
            info.cpuid_edx == INTEL_CPUID_EDX) {
            CPU->arch.vendor = VendorIntel;
        }
               
        cpuid(1, &info);
        CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
        CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
        CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;                      
    }
}
 
void cpu_print_report(cpu_t* m)
{
    printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
        m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
        m->arch.stepping, m->frequency_mhz);
}
 
/** @}
 */
 

Rev 2783	Rev 2927
1	/*	1	/*
2	* Copyright (c) 2001-2004 Jakub Jermar	2	* Copyright (c) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup amd64	29	/** @addtogroup amd64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <cpu.h>	35	#include <cpu.h>
36	#include <arch/cpu.h>	36	#include <arch/cpu.h>
37	#include <arch/cpuid.h>	37	#include <arch/cpuid.h>
38	#include <arch/pm.h>	38	#include <arch/pm.h>
39		39
40	#include <arch.h>	40	#include <arch.h>
41	#include <arch/types.h>	41	#include <arch/types.h>
42	#include <print.h>	42	#include <print.h>
43	#include <fpu_context.h>	43	#include <fpu_context.h>
44		44
45	/*	45	/*
46	* Identification of CPUs.	46	* Identification of CPUs.
47	* Contains only non-MP-Specification specific SMP code.	47	* Contains only non-MP-Specification specific SMP code.
48	*/	48	*/
49	#define AMD_CPUID_EBX 0x68747541	49	#define AMD_CPUID_EBX 0x68747541
50	#define AMD_CPUID_ECX 0x444d4163	50	#define AMD_CPUID_ECX 0x444d4163
51	#define AMD_CPUID_EDX 0x69746e65	51	#define AMD_CPUID_EDX 0x69746e65
52		52
53	#define INTEL_CPUID_EBX 0x756e6547	53	#define INTEL_CPUID_EBX 0x756e6547
54	#define INTEL_CPUID_ECX 0x6c65746e	54	#define INTEL_CPUID_ECX 0x6c65746e
55	#define INTEL_CPUID_EDX 0x49656e69	55	#define INTEL_CPUID_EDX 0x49656e69
56		56
57		57
58	enum vendor {	58	enum vendor {
59	VendorUnknown = 0,	59	VendorUnknown = 0,
60	VendorAMD,	60	VendorAMD,
61	VendorIntel	61	VendorIntel
62	};	62	};
63		63
64	static char *vendor_str[] = {	64	static char *vendor_str[] = {
65	"Unknown Vendor",	65	"Unknown Vendor",
66	"AuthenticAMD",	66	"AuthenticAMD",
67	"GenuineIntel"	67	"GenuineIntel"
68	};	68	};
69		69
70		70
71	/** Setup flags on processor so that we can use the FPU	71	/** Setup flags on processor so that we can use the FPU
72	*	72	*
73	* cr0.osfxsr = 1 -> we do support fxstor/fxrestor	73	* cr0.osfxsr = 1 -> we do support fxstor/fxrestor
74	* cr0.em = 0 -> we do not emulate coprocessor	74	* cr0.em = 0 -> we do not emulate coprocessor
75	* cr0.mp = 1 -> we do want lazy context switch	75	* cr0.mp = 1 -> we do want lazy context switch
76	*/	76	*/
77	void cpu_setup_fpu(void)	77	void cpu_setup_fpu(void)
78	{	78	{
79	asm volatile (	79	asm volatile (
80	"movq %%cr0, %%rax;"	80	"movq %%cr0, %%rax;"
81	"btsq $1, %%rax;" /* cr0.mp */	81	"btsq $1, %%rax;" /* cr0.mp */
82	"btrq $2, %%rax;" /* cr0.em */	82	"btrq $2, %%rax;" /* cr0.em */
83	"movq %%rax, %%cr0;"	83	"movq %%rax, %%cr0;"
84		84
85	"movq %%cr4, %%rax;"	85	"movq %%cr4, %%rax;"
86	"bts $9, %%rax;" /* cr4.osfxsr */	86	"bts $9, %%rax;" /* cr4.osfxsr */
87	"movq %%rax, %%cr4;"	87	"movq %%rax, %%cr4;"
88	:	88	:
89	:	89	:
90	:"%rax"	90	:"%rax"
91	);	91	);
92	}	92	}
93		93
94	/** Set the TS flag to 1.	94	/** Set the TS flag to 1.
95	*	95	*
96	* If a thread accesses coprocessor, exception is run, which	96	* If a thread accesses coprocessor, exception is run, which
97	* does a lazy fpu context switch.	97	* does a lazy fpu context switch.
98	*	98	*
99	*/	99	*/
100	void fpu_disable(void)	100	void fpu_disable(void)
101	{	101	{
102	asm volatile (	102	asm volatile (
103	"mov %%cr0,%%rax;"	103	"mov %%cr0,%%rax;"
104	"bts $3,%%rax;"	104	"bts $3,%%rax;"
105	"mov %%rax,%%cr0;"	105	"mov %%rax,%%cr0;"
106	:	106	:
107	:	107	:
108	:"%rax"	108	:"%rax"
109	);	109	);
110	}	110	}
111		111
112	void fpu_enable(void)	112	void fpu_enable(void)
113	{	113	{
114	asm volatile (	114	asm volatile (
115	"mov %%cr0,%%rax;"	115	"mov %%cr0,%%rax;"
116	"btr $3,%%rax;"	116	"btr $3,%%rax;"
117	"mov %%rax,%%cr0;"	117	"mov %%rax,%%cr0;"
118	:	118	:
119	:	119	:
120	:"%rax"	120	:"%rax"
121	);	121	);
122	}	122	}
123		123
124	void cpu_arch_init(void)	124	void cpu_arch_init(void)
125	{	125	{
126	CPU->arch.tss = tss_p;	126	CPU->arch.tss = tss_p;
127	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -	127	CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] -
128	((uint8_t *) CPU->arch.tss);	128	((uint8_t *) CPU->arch.tss);
129	CPU->fpu_owner = NULL;	129	CPU->fpu_owner = NULL;
130	}	130	}
131		131
132	void cpu_identify(void)	132	void cpu_identify(void)
133	{	133	{
134	cpu_info_t info;	134	cpu_info_t info;
135		135
136	CPU->arch.vendor = VendorUnknown;	136	CPU->arch.vendor = VendorUnknown;
137	if (has_cpuid()) {	137	if (has_cpuid()) {
138	cpuid(0, &info);	138	cpuid(0, &info);
139		139
140	/*	140	/*
141	* Check for AMD processor.	141	* Check for AMD processor.
142	*/	142	*/
143	if (info.cpuid_ebx == AMD_CPUID_EBX &&	143	if (info.cpuid_ebx == AMD_CPUID_EBX &&
144	info.cpuid_ecx == AMD_CPUID_ECX &&	144	info.cpuid_ecx == AMD_CPUID_ECX &&
145	info.cpuid_edx == AMD_CPUID_EDX) {	145	info.cpuid_edx == AMD_CPUID_EDX) {
146	CPU->arch.vendor = VendorAMD;	146	CPU->arch.vendor = VendorAMD;
147	}	147	}
148		148
149	/*	149	/*
150	* Check for Intel processor.	150	* Check for Intel processor.
151	*/	151	*/
152	if (info.cpuid_ebx == INTEL_CPUID_EBX &&	152	if (info.cpuid_ebx == INTEL_CPUID_EBX &&
153	info.cpuid_ecx == INTEL_CPUID_ECX &&	153	info.cpuid_ecx == INTEL_CPUID_ECX &&
154	info.cpuid_edx == INTEL_CPUID_EDX) {	154	info.cpuid_edx == INTEL_CPUID_EDX) {
155	CPU->arch.vendor = VendorIntel;	155	CPU->arch.vendor = VendorIntel;
156	}	156	}
157		157
158	cpuid(1, &info);	158	cpuid(1, &info);
159	CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;	159	CPU->arch.family = (info.cpuid_eax >> 8) & 0xf;
160	CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;	160	CPU->arch.model = (info.cpuid_eax >> 4) & 0xf;
161	CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;	161	CPU->arch.stepping = (info.cpuid_eax >> 0) & 0xf;
162	}	162	}
163	}	163	}
164		164
165	void cpu_print_report(cpu_t* m)	165	void cpu_print_report(cpu_t* m)
166	{	166	{
167	printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",	167	printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
168	m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,	168	m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model,
169	m->arch.stepping, m->frequency_mhz);	169	m->arch.stepping, m->frequency_mhz);
170	}	170	}
171		171
172	/** @}	172	/** @}
173	*/	173	*/
174		174

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(root)/branches/dynload/kernel/arch/amd64/src/cpu/cpu.c @ 4345 – Rev 2783 → 2927