WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/amd64/src/asm_utils.S


#
# Copyright (C) 2005 Ondrej Palkovsky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
 
#  Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
 
	
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
 
#define __ASM__
#include <arch/pm.h>
	
.text
.global interrupt_handlers
.global panic_printf
 
panic_printf:
	movq $halt, (%rsp)
	jmp printf
 
.global has_cpuid
.global rdtsc
 
 
## Determine CPUID support
#
# Return 0 in EAX if CPUID is not support, 1 if supported.
#
has_cpuid:
	pushq %rbx
	
	pushfq			# store flags
	popq %rax		# read flags
	movq %rax,%rbx		# copy flags
	btcl $21,%ebx		# swap the ID bit
	pushq %rbx
	popfq			# propagate the change into flags
	pushfq
	popq %rbx		# read flags	
	andl $(1<<21),%eax	# interested only in ID bit
	andl $(1<<21),%ebx
	xorl %ebx,%eax		# 0 if not supported, 1 if supported
	
	popq %rbx
	ret
 
 
rdtsc:
	xorq %rax,%rax
	rdtsc
	ret
	
 
# Push all general purpose registers on stack except %rbp, %rsp
.macro push_all_gpr
	pushq %rax 
	pushq %rbx
	pushq %rcx
	pushq %rdx
	pushq %rsi
	pushq %rdi
	pushq %r8
	pushq %r9
	pushq %r10
	pushq %r11
	pushq %r12
	pushq %r13
	pushq %r14
	pushq %r15
.endm
 
.macro pop_all_gpr
	popq %r15
	popq %r14
	popq %r13
	popq %r12
	popq %r11
	popq %r10
	popq %r9
	popq %r8
	popq %rdi
	popq %rsi
	popq %rdx
	popq %rcx
	popq %rbx
	popq %rax
.endm
	
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call trap_dispatcher().
#
.macro handler i n
	pushq %rbp
	movq %rsp,%rbp
	
	push_all_gpr
 
	# trap_dispatcher(i, stack)
	movq $(\i),%rdi   # %rdi - first parameter
	movq %rbp, %rsi
	addq $8, %rsi     # %rsi - second parameter - original stack
	call trap_dispatcher
 
# Test if this is interrupt with error word or not
	mov $\i,%cl;
	movl $1,%eax;
	test $0xe0,%cl;
	jnz 0f;
	and $0x1f,%cl;
	shl %cl,%eax;
	and $ERROR_WORD_INTERRUPT_LIST,%eax;
	jz 0f;
 
 
# Return with error word
	pop_all_gpr
	
	popq %rbp;
	add $8,%esp;    # Skip error word
	iretq
 
0:
# Return with no error word
	pop_all_gpr
	
	popq %rbp
	iretq
 
	.if (\n-\i)-1
	handler "(\i+1)",\n
	.endif
.endm
	
interrupt_handlers:
h_start:
	handler 0 IDT_ITEMS
#	handler 64 128	
#	handler 128 192
#	handler 192 256
h_end:
	
	
.data
.global interrupt_handler_size
 
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
 

Rev 224	Rev 242
1	#	1	#
2	# Copyright (C) 2005 Ondrej Palkovsky	2	# Copyright (C) 2005 Ondrej Palkovsky
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29		29
30	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word	30	# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
31	# and 1 means interrupt with error word	31	# and 1 means interrupt with error word
32		32
33		33
34	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00	34	#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
35		35
36	#define __ASM__	36	#define __ASM__
37	#include <arch/pm.h>	37	#include <arch/pm.h>
38		38
39	.text	39	.text
40	.global interrupt_handlers	40	.global interrupt_handlers
41	.global panic_printf	41	.global panic_printf
42		42
43	panic_printf:	43	panic_printf:
44	movq $halt, (%rsp)	44	movq $halt, (%rsp)
45	jmp printf	45	jmp printf
46		46
-		47	.global has_cpuid
-		48	.global rdtsc
-		49
-		50
-		51	## Determine CPUID support
-		52	#
-		53	# Return 0 in EAX if CPUID is not support, 1 if supported.
-		54	#
-		55	has_cpuid:
-		56	pushq %rbx
-		57
-		58	pushfq # store flags
-		59	popq %rax # read flags
-		60	movq %rax,%rbx # copy flags
-		61	btcl $21,%ebx # swap the ID bit
-		62	pushq %rbx
-		63	popfq # propagate the change into flags
-		64	pushfq
-		65	popq %rbx # read flags
-		66	andl $(1<<21),%eax # interested only in ID bit
-		67	andl $(1<<21),%ebx
-		68	xorl %ebx,%eax # 0 if not supported, 1 if supported
-		69
-		70	popq %rbx
-		71	ret
-		72
-		73
-		74	rdtsc:
-		75	xorq %rax,%rax
-		76	rdtsc
-		77	ret
-		78
-		79
47	# Push all general purpose registers on stack except %rbp, %rsp	80	# Push all general purpose registers on stack except %rbp, %rsp
48	.macro push_all_gpr	81	.macro push_all_gpr
49	pushq %rax	82	pushq %rax
50	pushq %rbx	83	pushq %rbx
51	pushq %rcx	84	pushq %rcx
52	pushq %rdx	85	pushq %rdx
53	pushq %rsi	86	pushq %rsi
54	pushq %rdi	87	pushq %rdi
55	pushq %r8	88	pushq %r8
56	pushq %r9	89	pushq %r9
57	pushq %r10	90	pushq %r10
58	pushq %r11	91	pushq %r11
59	pushq %r12	92	pushq %r12
60	pushq %r13	93	pushq %r13
61	pushq %r14	94	pushq %r14
62	pushq %r15	95	pushq %r15
63	.endm	96	.endm
64		97
65	.macro pop_all_gpr	98	.macro pop_all_gpr
66	popq %r15	99	popq %r15
67	popq %r14	100	popq %r14
68	popq %r13	101	popq %r13
69	popq %r12	102	popq %r12
70	popq %r11	103	popq %r11
71	popq %r10	104	popq %r10
72	popq %r9	105	popq %r9
73	popq %r8	106	popq %r8
74	popq %rdi	107	popq %rdi
75	popq %rsi	108	popq %rsi
76	popq %rdx	109	popq %rdx
77	popq %rcx	110	popq %rcx
78	popq %rbx	111	popq %rbx
79	popq %rax	112	popq %rax
80	.endm	113	.endm
81		114
82	## Declare interrupt handlers	115	## Declare interrupt handlers
83	#	116	#
84	# Declare interrupt handlers for n interrupt	117	# Declare interrupt handlers for n interrupt
85	# vectors starting at vector i.	118	# vectors starting at vector i.
86	#	119	#
87	# The handlers setup data segment registers	120	# The handlers setup data segment registers
88	# and call trap_dispatcher().	121	# and call trap_dispatcher().
89	#	122	#
90	.macro handler i n	123	.macro handler i n
91	pushq %rbp	124	pushq %rbp
92	movq %rsp,%rbp	125	movq %rsp,%rbp
93		126
94	push_all_gpr	127	push_all_gpr
95		128
96	# trap_dispatcher(i, stack)	129	# trap_dispatcher(i, stack)
97	movq $(\i),%rdi # %rdi - first parameter	130	movq $(\i),%rdi # %rdi - first parameter
98	movq %rbp, %rsi	131	movq %rbp, %rsi
99	addq $8, %rsi # %rsi - second parameter - original stack	132	addq $8, %rsi # %rsi - second parameter - original stack
100	call trap_dispatcher	133	call trap_dispatcher
101		134
102	# Test if this is interrupt with error word or not	135	# Test if this is interrupt with error word or not
103	mov $\i,%cl;	136	mov $\i,%cl;
104	movl $1,%eax;	137	movl $1,%eax;
105	test $0xe0,%cl;	138	test $0xe0,%cl;
106	jnz 0f;	139	jnz 0f;
107	and $0x1f,%cl;	140	and $0x1f,%cl;
108	shl %cl,%eax;	141	shl %cl,%eax;
109	and $ERROR_WORD_INTERRUPT_LIST,%eax;	142	and $ERROR_WORD_INTERRUPT_LIST,%eax;
110	jz 0f;	143	jz 0f;
111		144
112		145
113	# Return with error word	146	# Return with error word
114	pop_all_gpr	147	pop_all_gpr
115		148
116	popq %rbp;	149	popq %rbp;
117	add $8,%esp; # Skip error word	150	add $8,%esp; # Skip error word
118	iretq	151	iretq
119		152
120	0:	153	0:
121	# Return with no error word	154	# Return with no error word
122	pop_all_gpr	155	pop_all_gpr
123		156
124	popq %rbp	157	popq %rbp
125	iretq	158	iretq
126		159
127	.if (\n-\i)-1	160	.if (\n-\i)-1
128	handler "(\i+1)",\n	161	handler "(\i+1)",\n
129	.endif	162	.endif
130	.endm	163	.endm
131		164
132	interrupt_handlers:	165	interrupt_handlers:
133	h_start:	166	h_start:
134	handler 0 IDT_ITEMS	167	handler 0 IDT_ITEMS
135	# handler 64 128	168	# handler 64 128
136	# handler 128 192	169	# handler 128 192
137	# handler 192 256	170	# handler 192 256
138	h_end:	171	h_end:
139		172
140		173
141	.data	174	.data
142	.global interrupt_handler_size	175	.global interrupt_handler_size
143		176
144	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS	177	interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS
145		178

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(root)/branches/dynload/kernel/arch/amd64/src/asm_utils.S @ 4342 – Rev 224 → 242