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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __amd64_ASM_H__ |
29 | #ifndef __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
30 | #define __amd64_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | 34 | ||
35 | 35 | ||
36 | void asm_delay_loop(__u32 t); |
36 | void asm_delay_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
37 | void asm_fake_loop(__u32 t); |
38 | 38 | ||
39 | /** Return base address of current stack. |
39 | /** Return base address of current stack. |
40 | * |
40 | * |
41 | * Return the base address of the current stack. |
41 | * Return the base address of the current stack. |
42 | * The stack is assumed to be STACK_SIZE bytes long. |
42 | * The stack is assumed to be STACK_SIZE bytes long. |
43 | * The stack must start on page boundary. |
43 | * The stack must start on page boundary. |
44 | */ |
44 | */ |
45 | static inline __address get_stack_base(void) |
45 | static inline __address get_stack_base(void) |
46 | { |
46 | { |
47 | __address v; |
47 | __address v; |
48 | 48 | ||
49 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
49 | __asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1))); |
50 | 50 | ||
51 | return v; |
51 | return v; |
52 | } |
52 | } |
53 | 53 | ||
54 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
54 | static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); }; |
55 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
55 | static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); }; |
56 | 56 | ||
57 | 57 | ||
58 | static inline __u8 inb(__u16 port) |
58 | static inline __u8 inb(__u16 port) |
59 | { |
59 | { |
60 | __u8 out; |
60 | __u8 out; |
61 | 61 | ||
62 | __asm__ volatile ( |
62 | __asm__ volatile ( |
63 | "mov %1, %%dx\n" |
63 | "mov %1, %%dx\n" |
64 | "inb %%dx,%%al\n" |
64 | "inb %%dx,%%al\n" |
65 | "mov %%al, %0\n" |
65 | "mov %%al, %0\n" |
66 | :"=m"(out) |
66 | :"=m"(out) |
67 | :"m"(port) |
67 | :"m"(port) |
68 | :"%rdx","%rax" |
68 | :"%rdx","%rax" |
69 | ); |
69 | ); |
70 | return out; |
70 | return out; |
71 | } |
71 | } |
72 | 72 | ||
73 | static inline __u8 outb(__u16 port,__u8 b) |
73 | static inline __u8 outb(__u16 port,__u8 b) |
74 | { |
74 | { |
75 | __asm__ volatile ( |
75 | __asm__ volatile ( |
76 | "mov %0,%%dx\n" |
76 | "mov %0,%%dx\n" |
77 | "mov %1,%%al\n" |
77 | "mov %1,%%al\n" |
78 | "outb %%al,%%dx\n" |
78 | "outb %%al,%%dx\n" |
79 | : |
79 | : |
80 | :"m"( port), "m" (b) |
80 | :"m"( port), "m" (b) |
81 | :"%rdx","%rax" |
81 | :"%rdx","%rax" |
82 | ); |
82 | ); |
83 | } |
83 | } |
84 | 84 | ||
85 | /** Set priority level low |
85 | /** Enable interrupts. |
86 | * |
86 | * |
87 | * Enable interrupts and return previous |
87 | * Enable interrupts and return previous |
88 | * value of EFLAGS. |
88 | * value of EFLAGS. |
- | 89 | * |
|
- | 90 | * @return Old interrupt priority level. |
|
89 | */ |
91 | */ |
90 | static inline pri_t cpu_priority_low(void) { |
92 | static inline ipl_t interrupts_enable(void) { |
91 | pri_t v; |
93 | ipl_t v; |
92 | __asm__ volatile ( |
94 | __asm__ volatile ( |
93 | "pushfq\n" |
95 | "pushfq\n" |
94 | "popq %0\n" |
96 | "popq %0\n" |
95 | "sti\n" |
97 | "sti\n" |
96 | : "=r" (v) |
98 | : "=r" (v) |
97 | ); |
99 | ); |
98 | return v; |
100 | return v; |
99 | } |
101 | } |
100 | 102 | ||
101 | /** Set priority level high |
103 | /** Disable interrupts. |
102 | * |
104 | * |
103 | * Disable interrupts and return previous |
105 | * Disable interrupts and return previous |
104 | * value of EFLAGS. |
106 | * value of EFLAGS. |
- | 107 | * |
|
- | 108 | * @return Old interrupt priority level. |
|
105 | */ |
109 | */ |
106 | static inline pri_t cpu_priority_high(void) { |
110 | static inline ipl_t interrupts_disable(void) { |
107 | pri_t v; |
111 | ipl_t v; |
108 | __asm__ volatile ( |
112 | __asm__ volatile ( |
109 | "pushfq\n" |
113 | "pushfq\n" |
110 | "popq %0\n" |
114 | "popq %0\n" |
111 | "cli\n" |
115 | "cli\n" |
112 | : "=r" (v) |
116 | : "=r" (v) |
113 | ); |
117 | ); |
114 | return v; |
118 | return v; |
115 | } |
119 | } |
116 | 120 | ||
117 | /** Restore priority level |
121 | /** Restore interrupt priority level. |
118 | * |
122 | * |
119 | * Restore EFLAGS. |
123 | * Restore EFLAGS. |
- | 124 | * |
|
- | 125 | * @param ipl Saved interrupt priority level. |
|
120 | */ |
126 | */ |
121 | static inline void cpu_priority_restore(pri_t pri) { |
127 | static inline void interrupts_restore(ipl_t ipl) { |
122 | __asm__ volatile ( |
128 | __asm__ volatile ( |
123 | "pushq %0\n" |
129 | "pushq %0\n" |
124 | "popfq\n" |
130 | "popfq\n" |
125 | : : "r" (pri) |
131 | : : "r" (ipl) |
126 | ); |
132 | ); |
127 | } |
133 | } |
128 | 134 | ||
129 | /** Return raw priority level |
135 | /** Return interrupt priority level. |
130 | * |
136 | * |
131 | * Return EFLAFS. |
137 | * Return EFLAFS. |
- | 138 | * |
|
- | 139 | * @return Current interrupt priority level. |
|
132 | */ |
140 | */ |
133 | static inline pri_t cpu_priority_read(void) { |
141 | static inline ipl_t interrupts_read(void) { |
134 | pri_t v; |
142 | ipl_t v; |
135 | __asm__ volatile ( |
143 | __asm__ volatile ( |
136 | "pushfq\n" |
144 | "pushfq\n" |
137 | "popq %0\n" |
145 | "popq %0\n" |
138 | : "=r" (v) |
146 | : "=r" (v) |
139 | ); |
147 | ); |
140 | return v; |
148 | return v; |
141 | } |
149 | } |
142 | 150 | ||
143 | /** Read CR0 |
151 | /** Read CR0 |
144 | * |
152 | * |
145 | * Return value in CR0 |
153 | * Return value in CR0 |
146 | * |
154 | * |
147 | * @return Value read. |
155 | * @return Value read. |
148 | */ |
156 | */ |
149 | static inline __u64 read_cr0(void) |
157 | static inline __u64 read_cr0(void) |
150 | { |
158 | { |
151 | __u64 v; |
159 | __u64 v; |
152 | __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v)); |
160 | __asm__ volatile ("movq %%cr0,%0\n" : "=r" (v)); |
153 | return v; |
161 | return v; |
154 | } |
162 | } |
155 | 163 | ||
156 | /** Read CR2 |
164 | /** Read CR2 |
157 | * |
165 | * |
158 | * Return value in CR2 |
166 | * Return value in CR2 |
159 | * |
167 | * |
160 | * @return Value read. |
168 | * @return Value read. |
161 | */ |
169 | */ |
162 | static inline __u64 read_cr2(void) |
170 | static inline __u64 read_cr2(void) |
163 | { |
171 | { |
164 | __u64 v; |
172 | __u64 v; |
165 | __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v)); |
173 | __asm__ volatile ("movq %%cr2,%0\n" : "=r" (v)); |
166 | return v; |
174 | return v; |
167 | } |
175 | } |
168 | 176 | ||
169 | /** Write CR3 |
177 | /** Write CR3 |
170 | * |
178 | * |
171 | * Write value to CR3. |
179 | * Write value to CR3. |
172 | * |
180 | * |
173 | * @param v Value to be written. |
181 | * @param v Value to be written. |
174 | */ |
182 | */ |
175 | static inline void write_cr3(__u64 v) |
183 | static inline void write_cr3(__u64 v) |
176 | { |
184 | { |
177 | __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); |
185 | __asm__ volatile ("movq %0,%%cr3\n" : : "r" (v)); |
178 | } |
186 | } |
179 | 187 | ||
180 | /** Read CR3 |
188 | /** Read CR3 |
181 | * |
189 | * |
182 | * Return value in CR3 |
190 | * Return value in CR3 |
183 | * |
191 | * |
184 | * @return Value read. |
192 | * @return Value read. |
185 | */ |
193 | */ |
186 | static inline __u64 read_cr3(void) |
194 | static inline __u64 read_cr3(void) |
187 | { |
195 | { |
188 | __u64 v; |
196 | __u64 v; |
189 | __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); |
197 | __asm__ volatile ("movq %%cr3,%0" : "=r" (v)); |
190 | return v; |
198 | return v; |
191 | } |
199 | } |
192 | 200 | ||
193 | 201 | ||
194 | /** Enable local APIC |
202 | /** Enable local APIC |
195 | * |
203 | * |
196 | * Enable local APIC in MSR. |
204 | * Enable local APIC in MSR. |
197 | */ |
205 | */ |
198 | static inline void enable_l_apic_in_msr() |
206 | static inline void enable_l_apic_in_msr() |
199 | { |
207 | { |
200 | __asm__ volatile ( |
208 | __asm__ volatile ( |
201 | "movl $0x1b, %%ecx\n" |
209 | "movl $0x1b, %%ecx\n" |
202 | "rdmsr\n" |
210 | "rdmsr\n" |
203 | "orl $(1<<11),%%eax\n" |
211 | "orl $(1<<11),%%eax\n" |
204 | "orl $(0xfee00000),%%eax\n" |
212 | "orl $(0xfee00000),%%eax\n" |
205 | "wrmsr\n" |
213 | "wrmsr\n" |
206 | : |
214 | : |
207 | : |
215 | : |
208 | :"%eax","%ecx","%edx" |
216 | :"%eax","%ecx","%edx" |
209 | ); |
217 | ); |
210 | } |
218 | } |
211 | 219 | ||
212 | extern size_t interrupt_handler_size; |
220 | extern size_t interrupt_handler_size; |
213 | extern void interrupt_handlers(void); |
221 | extern void interrupt_handlers(void); |
214 | 222 | ||
215 | #endif |
223 | #endif |
216 | 224 |