WebSVN – HelenOS – Diff – /branches/dd/uspace/srv/pci/libpci/i386-ports.c


/*
 *  The PCI Library -- Direct Configuration access via i386 Ports
 *
 *  Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
 *
 *  May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar.
 *
 *  Can be freely distributed and used under the terms of the GNU GPL.
 */
 
#include <unistd.h>
#include <ddi.h>
#include <libarch/ddi.h>
 
#include "internal.h"
 
#define PCI_CONF1   0xcf8
#define PCI_CONF1_SIZE  8
 
 
static void conf12_init(struct pci_access *a)
{  
}
 
static void conf12_cleanup(struct pci_access *a UNUSED)
{
}
 
/*
 * Before we decide to use direct hardware access mechanisms, we try to do some
 * trivial checks to ensure it at least _seems_ to be working -- we just test
 * whether bus 00 contains a host bridge (this is similar to checking
 * techniques used in XFree86, but ours should be more reliable since we
 * attempt to make use of direct access hints provided by the PCI BIOS).
 *
 * This should be close to trivial, but it isn't, because there are buggy
 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
 */
 
static int intel_sanity_check(struct pci_access *a, struct pci_methods *m)
{
    struct pci_dev d;
 
    a->debug("...sanity check");
    d.bus = 0;
    d.func = 0;
    for (d.dev = 0; d.dev < 32; d.dev++) {
        u16 class, vendor;
        if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,
             sizeof(class))
            && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)
            || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))
            || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,
                   sizeof(vendor))
            && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)
            || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {
            a->debug("...outside the Asylum at 0/%02x/0",
                 d.dev);
            return 1;
        }
    }
    a->debug("...insane");
    return 0;
}
 
/*
 *  Configuration type 1
 */
 
#define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
 
static int conf1_detect(struct pci_access *a)
{
    unsigned int tmp;
    int res = 0;
   
    /*
     * Gain control over PCI configuration ports.
     */
    void * addr;
    if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) {
        return 0;
    }
 
    pio_write_8(0xCFB, 0x01);
    tmp = pio_read_32(0xCF8);
    pio_write_32(0xCF8, 0x80000000);
    if (pio_read_32(0xCF8) == 0x80000000) {
        res = 1;
    }
    pio_write_32(0xCF8, tmp);
    if (res) {
        res = intel_sanity_check(a, &pm_intel_conf1);
    }
    return res;
}
 
static int conf1_read(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xcfc + (pos & 3);
 
    if (pos >= 256)
        return 0;
 
    pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) |
         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3));
 
    switch (len) {
    case 1:
        buf[0] = pio_read_8(addr);
        break;
    case 2:
        ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
        break;
    case 4:
        ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
        break;
    default:
        return pci_generic_block_read(d, pos, buf, len);
    }
    return 1;
}
 
static int conf1_write(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xcfc + (pos & 3);
 
    if (pos >= 256)
        return 0;
 
    pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) |
         (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3));
 
    switch (len) {
    case 1:
        pio_write_8(addr, buf[0]);
        break;
    case 2:
        pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0]));
        break;
    case 4:
        pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0]));
        break;
    default:
        return pci_generic_block_write(d, pos, buf, len);
    }
    return 1;
}
 
/*
 *  Configuration type 2. Obsolete and brain-damaged, but existing.
 */
 
static int conf2_detect(struct pci_access *a)
{
    /*
     * Gain control over PCI configuration ports.
     */
    void * addr;
    if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) {
        return 0;
    }
    if (pio_enable((void *)0xC000, 0x1000, &addr)) {
        return 0;
    }  
   
    /* This is ugly and tends to produce false positives. Beware. */
    pio_write_8(0xCFB, 0x00);
    pio_write_8(0xCF8, 0x00);
    pio_write_8(0xCFA, 0x00);
    if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00)
        return intel_sanity_check(a, &pm_intel_conf2);
    else
        return 0;
}
 
static int conf2_read(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xc000 | (d->dev << 8) | pos;
 
    if (pos >= 256)
        return 0;
 
    if (d->dev >= 16)
        /* conf2 supports only 16 devices per bus */
        return 0;
    pio_write_8(0xcf8, (d->func << 1) | 0xf0);
    pio_write_8(0xcfa, d->bus);
    switch (len) {
    case 1:
        buf[0] = pio_read_8(addr);
        break;
    case 2:
        ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
        break;
    case 4:
        ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
        break;
    default:
        pio_write_8(0xcf8, 0);
        return pci_generic_block_read(d, pos, buf, len);
    }
    pio_write_8(0xcf8, 0);
    return 1;
}
 
static int conf2_write(struct pci_dev *d, int pos, byte * buf, int len)
{
    int addr = 0xc000 | (d->dev << 8) | pos;
 
    if (pos >= 256)
        return 0;
 
    if (d->dev >= 16)
        d->access->error("conf2_write: only first 16 devices exist.");
    pio_write_8(0xcf8, (d->func << 1) | 0xf0);
    pio_write_8(0xcfa, d->bus);
    switch (len) {
    case 1:
        pio_write_8(addr, buf[0]);
        break;
    case 2:
        pio_write_16(addr, le16_to_cpu(*(u16 *) buf));
        break;
    case 4:
        pio_write_32(addr, le32_to_cpu(*(u32 *) buf));
        break;
    default:
        pio_write_8(0xcf8, 0);
        return pci_generic_block_write(d, pos, buf, len);
    }
    pio_write_8(0xcf8, 0);
    return 1;
}
 
struct pci_methods pm_intel_conf1 = {
    "Intel-conf1",
    NULL,           /* config */
    conf1_detect,
    conf12_init,
    conf12_cleanup,
    pci_generic_scan,
    pci_generic_fill_info,
    conf1_read,
    conf1_write,
    NULL,           /* init_dev */
    NULL            /* cleanup_dev */
};
 
struct pci_methods pm_intel_conf2 = {
    "Intel-conf2",
    NULL,           /* config */
    conf2_detect,
    conf12_init,
    conf12_cleanup,
    pci_generic_scan,
    pci_generic_fill_info,
    conf2_read,
    conf2_write,
    NULL,           /* init_dev */
    NULL            /* cleanup_dev */
};
 

Rev 4204	Rev 4221
1	/*	1	/*
2	* The PCI Library -- Direct Configuration access via i386 Ports	2	* The PCI Library -- Direct Configuration access via i386 Ports
3	*	3	*
4	* Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>	4	* Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
5	*	5	*
6	* May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar.	6	* May 8, 2006 - Modified and ported to HelenOS by Jakub Jermar.
7	*	7	*
8	* Can be freely distributed and used under the terms of the GNU GPL.	8	* Can be freely distributed and used under the terms of the GNU GPL.
9	*/	9	*/
10		10
11	#include <unistd.h>	11	#include <unistd.h>
12	#include <ddi.h>	12	#include <ddi.h>
13	#include <libarch/ddi.h>	13	#include <libarch/ddi.h>
14		14
15	#include "internal.h"	15	#include "internal.h"
16		16
-		17	#define PCI_CONF1 0xcf8
-		18	#define PCI_CONF1_SIZE 8
-		19
17		20
18	static void conf12_init(struct pci_access *a)	21	static void conf12_init(struct pci_access *a)
19	{	22	{
20	}	23	}
21		24
22	static void conf12_cleanup(struct pci_access *a UNUSED)	25	static void conf12_cleanup(struct pci_access *a UNUSED)
23	{	26	{
24	}	27	}
25		28
26	/*	29	/*
27	* Before we decide to use direct hardware access mechanisms, we try to do some	30	* Before we decide to use direct hardware access mechanisms, we try to do some
28	* trivial checks to ensure it at least _seems_ to be working -- we just test	31	* trivial checks to ensure it at least _seems_ to be working -- we just test
29	* whether bus 00 contains a host bridge (this is similar to checking	32	* whether bus 00 contains a host bridge (this is similar to checking
30	* techniques used in XFree86, but ours should be more reliable since we	33	* techniques used in XFree86, but ours should be more reliable since we
31	* attempt to make use of direct access hints provided by the PCI BIOS).	34	* attempt to make use of direct access hints provided by the PCI BIOS).
32	*	35	*
33	* This should be close to trivial, but it isn't, because there are buggy	36	* This should be close to trivial, but it isn't, because there are buggy
34	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.	37	* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
35	*/	38	*/
36		39
37	static int intel_sanity_check(struct pci_access a, struct pci_methods m)	40	static int intel_sanity_check(struct pci_access a, struct pci_methods m)
38	{	41	{
39	struct pci_dev d;	42	struct pci_dev d;
40		43
41	a->debug("...sanity check");	44	a->debug("...sanity check");
42	d.bus = 0;	45	d.bus = 0;
43	d.func = 0;	46	d.func = 0;
44	for (d.dev = 0; d.dev < 32; d.dev++) {	47	for (d.dev = 0; d.dev < 32; d.dev++) {
45	u16 class, vendor;	48	u16 class, vendor;
46	if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,	49	if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,
47	sizeof(class))	50	sizeof(class))
48	&& (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)	51	&& (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST)
49	\|\| class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))	52	\|\| class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA))
50	\|\| m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,	53	\|\| m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,
51	sizeof(vendor))	54	sizeof(vendor))
52	&& (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)	55	&& (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL)
53	\|\| vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {	56	\|\| vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) {
54	a->debug("...outside the Asylum at 0/%02x/0",	57	a->debug("...outside the Asylum at 0/%02x/0",
55	d.dev);	58	d.dev);
56	return 1;	59	return 1;
57	}	60	}
58	}	61	}
59	a->debug("...insane");	62	a->debug("...insane");
60	return 0;	63	return 0;
61	}	64	}
62		65
63	/*	66	/*
64	* Configuration type 1	67	* Configuration type 1
65	*/	68	*/
66		69
67	#define CONFIG_CMD(bus, device_fn, where) (0x80000000 \| (bus << 16) \| (device_fn << 8) \| (where & ~3))	70	#define CONFIG_CMD(bus, device_fn, where) (0x80000000 \| (bus << 16) \| (device_fn << 8) \| (where & ~3))
68		71
69	static int conf1_detect(struct pci_access *a)	72	static int conf1_detect(struct pci_access *a)
70	{	73	{
71	unsigned int tmp;	74	unsigned int tmp;
72	int res = 0;	75	int res = 0;
-		76
-		77	/*
-		78	* Gain control over PCI configuration ports.
-		79	*/
-		80	void * addr;
-		81	if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) {
-		82	return 0;
-		83	}
73		84
74	pio_write_8(0xCFB, 0x01);	85	pio_write_8(0xCFB, 0x01);
75	tmp = pio_read_32(0xCF8);	86	tmp = pio_read_32(0xCF8);
76	pio_write_32(0xCF8, 0x80000000);	87	pio_write_32(0xCF8, 0x80000000);
77	if (pio_read_32(0xCF8) == 0x80000000) {	88	if (pio_read_32(0xCF8) == 0x80000000) {
78	res = 1;	89	res = 1;
79	}	90	}
80	pio_write_32(0xCF8, tmp);	91	pio_write_32(0xCF8, tmp);
81	if (res) {	92	if (res) {
82	res = intel_sanity_check(a, &pm_intel_conf1);	93	res = intel_sanity_check(a, &pm_intel_conf1);
83	}	94	}
84	return res;	95	return res;
85	}	96	}
86		97
87	static int conf1_read(struct pci_dev d, int pos, byte buf, int len)	98	static int conf1_read(struct pci_dev d, int pos, byte buf, int len)
88	{	99	{
89	int addr = 0xcfc + (pos & 3);	100	int addr = 0xcfc + (pos & 3);
90		101
91	if (pos >= 256)	102	if (pos >= 256)
92	return 0;	103	return 0;
93		104
94	pio_write_32(0xcf8, 0x80000000 \| ((d->bus & 0xff) << 16) \|	105	pio_write_32(0xcf8, 0x80000000 \| ((d->bus & 0xff) << 16) \|
95	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3));	106	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3));
96		107
97	switch (len) {	108	switch (len) {
98	case 1:	109	case 1:
99	buf[0] = pio_read_8(addr);	110	buf[0] = pio_read_8(addr);
100	break;	111	break;
101	case 2:	112	case 2:
102	((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));	113	((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
103	break;	114	break;
104	case 4:	115	case 4:
105	((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));	116	((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
106	break;	117	break;
107	default:	118	default:
108	return pci_generic_block_read(d, pos, buf, len);	119	return pci_generic_block_read(d, pos, buf, len);
109	}	120	}
110	return 1;	121	return 1;
111	}	122	}
112		123
113	static int conf1_write(struct pci_dev d, int pos, byte buf, int len)	124	static int conf1_write(struct pci_dev d, int pos, byte buf, int len)
114	{	125	{
115	int addr = 0xcfc + (pos & 3);	126	int addr = 0xcfc + (pos & 3);
116		127
117	if (pos >= 256)	128	if (pos >= 256)
118	return 0;	129	return 0;
119		130
120	pio_write_32(0xcf8, 0x80000000 \| ((d->bus & 0xff) << 16) \|	131	pio_write_32(0xcf8, 0x80000000 \| ((d->bus & 0xff) << 16) \|
121	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3));	132	(PCI_DEVFN(d->dev, d->func) << 8) \| (pos & ~3));
122		133
123	switch (len) {	134	switch (len) {
124	case 1:	135	case 1:
125	pio_write_8(addr, buf[0]);	136	pio_write_8(addr, buf[0]);
126	break;	137	break;
127	case 2:	138	case 2:
128	pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0]));	139	pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0]));
129	break;	140	break;
130	case 4:	141	case 4:
131	pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0]));	142	pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0]));
132	break;	143	break;
133	default:	144	default:
134	return pci_generic_block_write(d, pos, buf, len);	145	return pci_generic_block_write(d, pos, buf, len);
135	}	146	}
136	return 1;	147	return 1;
137	}	148	}
138		149
139	/*	150	/*
140	* Configuration type 2. Obsolete and brain-damaged, but existing.	151	* Configuration type 2. Obsolete and brain-damaged, but existing.
141	*/	152	*/
142		153
143	static int conf2_detect(struct pci_access *a)	154	static int conf2_detect(struct pci_access *a)
144	{	155	{
-		156	/*
-		157	* Gain control over PCI configuration ports.
-		158	*/
-		159	void * addr;
-		160	if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) {
-		161	return 0;
-		162	}
-		163	if (pio_enable((void *)0xC000, 0x1000, &addr)) {
-		164	return 0;
-		165	}
-		166
145	/* This is ugly and tends to produce false positives. Beware. */	167	/* This is ugly and tends to produce false positives. Beware. */
146	pio_write_8(0xCFB, 0x00);	168	pio_write_8(0xCFB, 0x00);
147	pio_write_8(0xCF8, 0x00);	169	pio_write_8(0xCF8, 0x00);
148	pio_write_8(0xCFA, 0x00);	170	pio_write_8(0xCFA, 0x00);
149	if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00)	171	if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00)
150	return intel_sanity_check(a, &pm_intel_conf2);	172	return intel_sanity_check(a, &pm_intel_conf2);
151	else	173	else
152	return 0;	174	return 0;
153	}	175	}
154		176
155	static int conf2_read(struct pci_dev d, int pos, byte buf, int len)	177	static int conf2_read(struct pci_dev d, int pos, byte buf, int len)
156	{	178	{
157	int addr = 0xc000 \| (d->dev << 8) \| pos;	179	int addr = 0xc000 \| (d->dev << 8) \| pos;
158		180
159	if (pos >= 256)	181	if (pos >= 256)
160	return 0;	182	return 0;
161		183
162	if (d->dev >= 16)	184	if (d->dev >= 16)
163	/* conf2 supports only 16 devices per bus */	185	/* conf2 supports only 16 devices per bus */
164	return 0;	186	return 0;
165	pio_write_8(0xcf8, (d->func << 1) \| 0xf0);	187	pio_write_8(0xcf8, (d->func << 1) \| 0xf0);
166	pio_write_8(0xcfa, d->bus);	188	pio_write_8(0xcfa, d->bus);
167	switch (len) {	189	switch (len) {
168	case 1:	190	case 1:
169	buf[0] = pio_read_8(addr);	191	buf[0] = pio_read_8(addr);
170	break;	192	break;
171	case 2:	193	case 2:
172	((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));	194	((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
173	break;	195	break;
174	case 4:	196	case 4:
175	((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));	197	((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
176	break;	198	break;
177	default:	199	default:
178	pio_write_8(0xcf8, 0);	200	pio_write_8(0xcf8, 0);
179	return pci_generic_block_read(d, pos, buf, len);	201	return pci_generic_block_read(d, pos, buf, len);
180	}	202	}
181	pio_write_8((void *)0xcf8, 0);	203	pio_write_8(0xcf8, 0);
182	return 1;	204	return 1;
183	}	205	}
184		206
185	static int conf2_write(struct pci_dev d, int pos, byte buf, int len)	207	static int conf2_write(struct pci_dev d, int pos, byte buf, int len)
186	{	208	{
187	int addr = 0xc000 \| (d->dev << 8) \| pos;	209	int addr = 0xc000 \| (d->dev << 8) \| pos;
188		210
189	if (pos >= 256)	211	if (pos >= 256)
190	return 0;	212	return 0;
191		213
192	if (d->dev >= 16)	214	if (d->dev >= 16)
193	d->access->error("conf2_write: only first 16 devices exist.");	215	d->access->error("conf2_write: only first 16 devices exist.");
194	pio_write_8(0xcf8, (d->func << 1) \| 0xf0);	216	pio_write_8(0xcf8, (d->func << 1) \| 0xf0);
195	pio_write_8(0xcfa, d->bus);	217	pio_write_8(0xcfa, d->bus);
196	switch (len) {	218	switch (len) {
197	case 1:	219	case 1:
198	pio_write_8(addr, buf[0]);	220	pio_write_8(addr, buf[0]);
199	break;	221	break;
200	case 2:	222	case 2:
201	pio_write_16(addr, le16_to_cpu((u16 ) buf));	223	pio_write_16(addr, le16_to_cpu((u16 ) buf));
202	break;	224	break;
203	case 4:	225	case 4:
204	pio_write_32(addr, le32_to_cpu((u32 ) buf));	226	pio_write_32(addr, le32_to_cpu((u32 ) buf));
205	break;	227	break;
206	default:	228	default:
207	pio_write_8(0xcf8, 0);	229	pio_write_8(0xcf8, 0);
208	return pci_generic_block_write(d, pos, buf, len);	230	return pci_generic_block_write(d, pos, buf, len);
209	}	231	}
210	pio_write_8(0xcf8, 0);	232	pio_write_8(0xcf8, 0);
211	return 1;	233	return 1;
212	}	234	}
213		235
214	struct pci_methods pm_intel_conf1 = {	236	struct pci_methods pm_intel_conf1 = {
215	"Intel-conf1",	237	"Intel-conf1",
216	NULL, /* config */	238	NULL, /* config */
217	conf1_detect,	239	conf1_detect,
218	conf12_init,	240	conf12_init,
219	conf12_cleanup,	241	conf12_cleanup,
220	pci_generic_scan,	242	pci_generic_scan,
221	pci_generic_fill_info,	243	pci_generic_fill_info,
222	conf1_read,	244	conf1_read,
223	conf1_write,	245	conf1_write,
224	NULL, /* init_dev */	246	NULL, /* init_dev */
225	NULL /* cleanup_dev */	247	NULL /* cleanup_dev */
226	};	248	};
227		249
228	struct pci_methods pm_intel_conf2 = {	250	struct pci_methods pm_intel_conf2 = {
229	"Intel-conf2",	251	"Intel-conf2",
230	NULL, /* config */	252	NULL, /* config */
231	conf2_detect,	253	conf2_detect,
232	conf12_init,	254	conf12_init,
233	conf12_cleanup,	255	conf12_cleanup,
234	pci_generic_scan,	256	pci_generic_scan,
235	pci_generic_fill_info,	257	pci_generic_fill_info,
236	conf2_read,	258	conf2_read,
237	conf2_write,	259	conf2_write,
238	NULL, /* init_dev */	260	NULL, /* init_dev */
239	NULL /* cleanup_dev */	261	NULL /* cleanup_dev */
240	};	262	};
241		263

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(root)/branches/dd/uspace/srv/pci/libpci/i386-ports.c – Rev 4204 → 4221