WebSVN – HelenOS – Diff – /branches/dd/kernel/genarch/src/drivers/z8530/z8530.c


/*
 * Copyright (c) 2009 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup genarch
 * @{
 */
/**
 * @file
 * @brief   Zilog 8530 serial controller driver.
 */
 
#include <genarch/drivers/z8530/z8530.h>
#include <console/chardev.h>
#include <ddi/irq.h>
#include <arch/asm.h>
#include <mm/slab.h>
 
static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)
{
    /*
     * Registers 8-15 will automatically issue the Point High
     * command as their bit 3 is 1.
     */
    pio_write_8(ctl, reg);  /* select register */
    pio_write_8(ctl, val);  /* write value */
}
 
static inline uint8_t z8530_read(ioport8_t *ctl, uint8_t reg)
{
    /*
     * Registers 8-15 will automatically issue the Point High
     * command as their bit 3 is 1.
     */
    pio_write_8(ctl, reg);  /* select register */
    return pio_read_8(ctl);
}
 
/** Initialize z8530. */
bool
z8530_init(z8530_t *dev, devno_t devno, inr_t inr, cir_t cir, void *cir_arg,
    chardev_t *devout)
{
    z8530_instance_t *instance;
 
    instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
    if (!instance)
        return false;
 
    instance->devno = devno;
    instance->z8530 = dev;
    instance->devout = devout;
 
    irq_initialize(&instance->irq);
    instance->irq.devno = devno;
    instance->irq.inr = inr;
    instance->irq.claim = z8530_claim;
    instance->irq.handler = z8530_irq_handler;
    instance->irq.instance = instance;
    instance->irq.cir = cir;
    instance->irq.cir_arg = cir_arg;
    irq_register(&instance->irq);
 
    (void) z8530_read(&dev->ctl_a, RR8);
 
    /*
     * Clear any pending TX interrupts or we never manage
     * to set FHC UART interrupt state to idle.
     */
    z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST);
 
    /* interrupt on all characters */
    z8530_write(&dev->ctl_a, WR1, WR1_IARCSC);
 
    /* 8 bits per character and enable receiver */
    z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
   
    /* Master Interrupt Enable. */
    z8530_write(&dev->ctl_a, WR9, WR9_MIE);
 
    return true;
}
 
irq_ownership_t z8530_claim(irq_t *irq)
{
    z8530_instance_t *instance = irq->instance;
    z8530_t *dev = instance->z8530;
 
    if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA)
        return IRQ_ACCEPT;
    else
        return IRQ_DECLINE;
}
 
void z8530_irq_handler(irq_t *irq)
{
    z8530_instance_t *instance = irq->instance;
    z8530_t *dev = instance->z8530;
    uint8_t x;
 
    if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
        x = z8530_read(&dev->ctl_a, RR8);
        if (instance->devout)
            chardev_push_character(instance->devout, x);
    }
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/dd/kernel/genarch/src/drivers/z8530/z8530.c @ 4646 – Rev 4042 → 4055

Rev 4042		Rev 4055
1	/*	1	/*
2	* Copyright (c) 2009 Jakub Jermar	2	* Copyright (c) 2009 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup genarch	29	/** @addtogroup genarch
30	* @{	30	* @{
31	*/	31	*/
32	/**	32	/**
33	* @file	33	* @file
34	* @brief Zilog 8530 serial controller driver.	34	* @brief Zilog 8530 serial controller driver.
35	*/	35	*/
36		36
37	#include <genarch/drivers/z8530/z8530.h>	37	#include <genarch/drivers/z8530/z8530.h>
38	#include <console/chardev.h>	38	#include <console/chardev.h>
39	#include <ddi/irq.h>	39	#include <ddi/irq.h>
40	#include <arch/asm.h>	40	#include <arch/asm.h>
41	#include <mm/slab.h>	41	#include <mm/slab.h>
42		42
43	static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)	43	static inline void z8530_write(ioport8_t *ctl, uint8_t reg, uint8_t val)
44	{	44	{
45	/*	45	/*
46	* Registers 8-15 will automatically issue the Point High	46	* Registers 8-15 will automatically issue the Point High
47	* command as their bit 3 is 1.	47	* command as their bit 3 is 1.
48	*/	48	*/
49	pio_write_8(ctl, reg); /* select register */	49	pio_write_8(ctl, reg); /* select register */
50	pio_write_8(ctl, val); /* write value */	50	pio_write_8(ctl, val); /* write value */
51	}	51	}
52		52
53	static inline uint8_t z8530_read(ioport8_t *ctl, uint8_t reg)	53	static inline uint8_t z8530_read(ioport8_t *ctl, uint8_t reg)
54	{	54	{
55	/*	55	/*
56	* Registers 8-15 will automatically issue the Point High	56	* Registers 8-15 will automatically issue the Point High
57	* command as their bit 3 is 1.	57	* command as their bit 3 is 1.
58	*/	58	*/
59	pio_write_8(ctl, reg); /* select register */	59	pio_write_8(ctl, reg); /* select register */
60	return pio_read_8(ctl);	60	return pio_read_8(ctl);
61	}	61	}
62		62
63	/** Initialize z8530. */	63	/** Initialize z8530. */
64	bool	64	bool
65	z8530_init(z8530_t dev, devno_t devno, inr_t inr, cir_t cir, void cir_arg,	65	z8530_init(z8530_t dev, devno_t devno, inr_t inr, cir_t cir, void cir_arg,
66	chardev_t *devout)	66	chardev_t *devout)
67	{	67	{
68	z8530_instance_t *instance;	68	z8530_instance_t *instance;
69		69
70	instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);	70	instance = malloc(sizeof(z8530_instance_t), FRAME_ATOMIC);
71	if (!instance)	71	if (!instance)
72	return false;	72	return false;
73		73
74	instance->devno = devno;	74	instance->devno = devno;
75	instance->z8530 = dev;	75	instance->z8530 = dev;
76	instance->devout = devout;	76	instance->devout = devout;
77		77
78	irq_initialize(&instance->irq);	78	irq_initialize(&instance->irq);
79	instance->irq.devno = devno;	79	instance->irq.devno = devno;
80	instance->irq.inr = inr;	80	instance->irq.inr = inr;
81	instance->irq.claim = z8530_claim;	81	instance->irq.claim = z8530_claim;
82	instance->irq.handler = z8530_irq_handler;	82	instance->irq.handler = z8530_irq_handler;
83	instance->irq.instance = instance;	83	instance->irq.instance = instance;
84	instance->irq.cir = cir;	84	instance->irq.cir = cir;
85	instance->irq.cir_arg = cir_arg;	85	instance->irq.cir_arg = cir_arg;
86	irq_register(&instance->irq);	86	irq_register(&instance->irq);
87		87
88	(void) z8530_read(&dev->ctl_a, RR8);	88	(void) z8530_read(&dev->ctl_a, RR8);
89		89
90	/*	90	/*
91	* Clear any pending TX interrupts or we never manage	91	* Clear any pending TX interrupts or we never manage
92	* to set FHC UART interrupt state to idle.	92	* to set FHC UART interrupt state to idle.
93	*/	93	*/
94	z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST);	94	z8530_write(&dev->ctl_a, WR0, WR0_TX_IP_RST);
95		95
96	/* interrupt on all characters */	96	/* interrupt on all characters */
97	z8530_write(&dev->ctl_a, WR1, WR1_IARCSC);	97	z8530_write(&dev->ctl_a, WR1, WR1_IARCSC);
98		98
99	/* 8 bits per character and enable receiver */	99	/* 8 bits per character and enable receiver */
100	z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH \| WR3_RX_ENABLE);	100	z8530_write(&dev->ctl_a, WR3, WR3_RX8BITSCH \| WR3_RX_ENABLE);
101		101
102	/* Master Interrupt Enable. */	102	/* Master Interrupt Enable. */
103	z8530_write(&dev->ctl_a, WR9, WR9_MIE);	103	z8530_write(&dev->ctl_a, WR9, WR9_MIE);
104		104
105	return true;	105	return true;
106	}	106	}
107		107
108	irq_ownership_t z8530_claim(irq_t *irq)	108	irq_ownership_t z8530_claim(irq_t *irq)
109	{	109	{
110	z8530_instance_t *instance = irq->instance;	110	z8530_instance_t *instance = irq->instance;
111	z8530_t *dev = instance->z8530;	111	z8530_t *dev = instance->z8530;
112		112
113	if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA)	113	if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA)
114	return IRQ_ACCEPT;	114	return IRQ_ACCEPT;
115	else	115	else
116	return IRQ_DECLINE;	116	return IRQ_DECLINE;
117	}	117	}
118		118
119	void z8530_irq_handler(irq_t *irq)	119	void z8530_irq_handler(irq_t *irq)
120	{	120	{
121	z8530_instance_t *instance = irq->instance;	121	z8530_instance_t *instance = irq->instance;
122	z8530_t *dev = instance->z8530;	122	z8530_t *dev = instance->z8530;
123	uint8_t x;	123	uint8_t x;
124		124
125	if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {	125	if (z8530_read(&dev->ctl_a, RR0) & RR0_RCA) {
126	x = z8530_read(&dev->ctl_a, RR8);	126	x = z8530_read(&dev->ctl_a, RR8);
127	if (instance->devout)	127	if (instance->devout)
128	chardev_push_character(instance->devout, x);	128	chardev_push_character(instance->devout, x);
129	}	129	}
130	}	130	}
131		131
132	/** @}	132	/** @}
133	*/	133	*/
134		134