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1 | /* |
1 | /* |
2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (c) 2005 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup sparc64 |
29 | /** @addtogroup sparc64 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_sparc64_REGISTER_H_ |
35 | #ifndef KERN_sparc64_REGISTER_H_ |
36 | #define KERN_sparc64_REGISTER_H_ |
36 | #define KERN_sparc64_REGISTER_H_ |
37 | 37 | ||
38 | #include <arch/regdef.h> |
38 | #include <arch/regdef.h> |
39 | #include <arch/types.h> |
39 | #include <arch/types.h> |
40 | 40 | ||
41 | /** Version Register. */ |
41 | /** Version Register. */ |
42 | union ver_reg { |
42 | union ver_reg { |
43 | uint64_t value; |
43 | uint64_t value; |
44 | struct { |
44 | struct { |
45 | uint16_t manuf; /**< Manufacturer code. */ |
45 | uint16_t manuf; /**< Manufacturer code. */ |
46 | uint16_t impl; /**< Implementation code. */ |
46 | uint16_t impl; /**< Implementation code. */ |
47 | uint8_t mask; /**< Mask set revision. */ |
47 | uint8_t mask; /**< Mask set revision. */ |
48 | unsigned : 8; |
48 | unsigned : 8; |
49 | uint8_t maxtl; |
49 | uint8_t maxtl; |
50 | unsigned : 3; |
50 | unsigned : 3; |
51 | unsigned maxwin : 5; |
51 | unsigned maxwin : 5; |
52 | } __attribute__ ((packed)); |
52 | } __attribute__ ((packed)); |
53 | }; |
53 | }; |
54 | typedef union ver_reg ver_reg_t; |
54 | typedef union ver_reg ver_reg_t; |
55 | 55 | ||
56 | /** Processor State Register. */ |
56 | /** Processor State Register. */ |
57 | union pstate_reg { |
57 | union pstate_reg { |
58 | uint64_t value; |
58 | uint64_t value; |
59 | struct { |
59 | struct { |
60 | uint64_t : 52; |
60 | uint64_t : 52; |
61 | unsigned ig : 1; /**< Interrupt Globals. */ |
61 | unsigned ig : 1; /**< Interrupt Globals. */ |
62 | unsigned mg : 1; /**< MMU Globals. */ |
62 | unsigned mg : 1; /**< MMU Globals. */ |
63 | unsigned cle : 1; /**< Current Little Endian. */ |
63 | unsigned cle : 1; /**< Current Little Endian. */ |
64 | unsigned tle : 1; /**< Trap Little Endian. */ |
64 | unsigned tle : 1; /**< Trap Little Endian. */ |
65 | unsigned mm : 2; /**< Memory Model. */ |
65 | unsigned mm : 2; /**< Memory Model. */ |
66 | unsigned red : 1; /**< RED state. */ |
66 | unsigned red : 1; /**< RED state. */ |
67 | unsigned pef : 1; /**< Enable floating-point. */ |
67 | unsigned pef : 1; /**< Enable floating-point. */ |
68 | unsigned am : 1; /**< 32-bit Address Mask. */ |
68 | unsigned am : 1; /**< 32-bit Address Mask. */ |
69 | unsigned priv : 1; /**< Privileged Mode. */ |
69 | unsigned priv : 1; /**< Privileged Mode. */ |
70 | unsigned ie : 1; /**< Interrupt Enable. */ |
70 | unsigned ie : 1; /**< Interrupt Enable. */ |
71 | unsigned ag : 1; /**< Alternate Globals*/ |
71 | unsigned ag : 1; /**< Alternate Globals*/ |
72 | } __attribute__ ((packed)); |
72 | } __attribute__ ((packed)); |
73 | }; |
73 | }; |
74 | typedef union pstate_reg pstate_reg_t; |
74 | typedef union pstate_reg pstate_reg_t; |
75 | 75 | ||
76 | /** TICK Register. */ |
76 | /** TICK Register. */ |
77 | union tick_reg { |
77 | union tick_reg { |
78 | uint64_t value; |
78 | uint64_t value; |
79 | struct { |
79 | struct { |
80 | unsigned npt : 1; /**< Non-privileged Trap enable. */ |
80 | unsigned npt : 1; /**< Non-privileged Trap enable. */ |
81 | uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */ |
81 | uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */ |
82 | } __attribute__ ((packed)); |
82 | } __attribute__ ((packed)); |
83 | }; |
83 | }; |
84 | typedef union tick_reg tick_reg_t; |
84 | typedef union tick_reg tick_reg_t; |
85 | 85 | ||
86 | /** TICK_compare Register. */ |
86 | /** TICK_compare Register. */ |
87 | union tick_compare_reg { |
87 | union tick_compare_reg { |
88 | uint64_t value; |
88 | uint64_t value; |
89 | struct { |
89 | struct { |
90 | unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ |
90 | unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ |
91 | uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ |
91 | uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ |
92 | } __attribute__ ((packed)); |
92 | } __attribute__ ((packed)); |
93 | }; |
93 | }; |
94 | typedef union tick_compare_reg tick_compare_reg_t; |
94 | typedef union tick_compare_reg tick_compare_reg_t; |
95 | 95 | ||
96 | /** SOFTINT Register. */ |
96 | /** SOFTINT Register. */ |
97 | union softint_reg { |
97 | union softint_reg { |
98 | uint64_t value; |
98 | uint64_t value; |
99 | struct { |
99 | struct { |
100 | uint64_t : 47; |
100 | uint64_t : 47; |
101 | unsigned stick_int : 1; |
101 | unsigned stick_int : 1; |
102 | unsigned int_level : 15; |
102 | unsigned int_level : 15; |
103 | unsigned tick_int : 1; |
103 | unsigned tick_int : 1; |
104 | } __attribute__ ((packed)); |
104 | } __attribute__ ((packed)); |
105 | }; |
105 | }; |
106 | typedef union softint_reg softint_reg_t; |
106 | typedef union softint_reg softint_reg_t; |
107 | 107 | ||
108 | /** Floating-point Registers State Register. */ |
108 | /** Floating-point Registers State Register. */ |
109 | union fprs_reg { |
109 | union fprs_reg { |
110 | uint64_t value; |
110 | uint64_t value; |
111 | struct { |
111 | struct { |
112 | uint64_t : 61; |
112 | uint64_t : 61; |
113 | unsigned fef : 1; |
113 | unsigned fef : 1; |
114 | unsigned du : 1; |
114 | unsigned du : 1; |
115 | unsigned dl : 1; |
115 | unsigned dl : 1; |
116 | } __attribute__ ((packed)); |
116 | } __attribute__ ((packed)); |
117 | }; |
117 | }; |
118 | typedef union fprs_reg fprs_reg_t; |
118 | typedef union fprs_reg fprs_reg_t; |
119 | 119 | ||
120 | /** UPA_CONFIG register. |
120 | /** UPA_CONFIG register. |
121 | * |
121 | * |
122 | * Note that format of this register differs significantly from |
122 | * Note that format of this register differs significantly from |
123 | * processor version to version. The format defined here |
123 | * processor version to version. The format defined here |
124 | * is the common subset for all supported processor versions. |
124 | * is the common subset for all supported processor versions. |
125 | */ |
125 | */ |
126 | union upa_config { |
126 | union upa_config { |
127 | uint64_t value; |
127 | uint64_t value; |
128 | struct { |
128 | struct { |
129 | uint64_t : 34; |
129 | uint64_t : 34; |
130 | unsigned pcon : 8; /**< Processor configuration. */ |
130 | unsigned pcon : 8; /**< Processor configuration. */ |
131 | unsigned mid : 5; /**< Module (processor) ID register. */ |
131 | unsigned mid : 5; /**< Module (processor) ID register. */ |
132 | unsigned pcap : 17; /**< Processor capabilities. */ |
132 | unsigned pcap : 17; /**< Processor capabilities. */ |
133 | } __attribute__ ((packed)); |
133 | } __attribute__ ((packed)); |
134 | }; |
134 | }; |
135 | typedef union upa_config upa_config_t; |
135 | typedef union upa_config upa_config_t; |
136 | 136 | ||
137 | #endif |
137 | #endif |
138 | 138 | ||
139 | /** @} |
139 | /** @} |
140 | */ |
140 | */ |
141 | 141 |