WebSVN – HelenOS – Diff – /branches/dd/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
static inline void pio_write_8(ioport8_t *port, uint8_t v)
{
    *port = v;
    memory_barrier();
}
 
static inline void pio_write_16(ioport16_t *port, uint16_t v)
{
    *port = v;
    memory_barrier();
}
 
static inline void pio_write_32(ioport32_t *port, uint32_t v)
{
    *port = v;
    memory_barrier();
}
 
static inline uint8_t pio_read_8(ioport8_t *port)
{
    uint8_t rv;
 
    rv = *port;
    memory_barrier();
 
    return rv;
}
 
static inline uint16_t pio_read_16(ioport16_t *port)
{
    uint16_t rv;
 
    rv = *port;
    memory_barrier();
 
    return rv;
}
 
static inline uint32_t pio_read_32(ioport32_t *port)
{
    uint32_t rv;
 
    rv = *port;
    memory_barrier();
 
    return rv;
}
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read STICK_compare Register.
 *
 * @return Value of STICK_compare register.
 */
static inline uint64_t stick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write STICK_compare Register.
 *
 * @param v New value of STICK_comapre register.
 */
static inline void stick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
 
 
 
 
 
 
 
 
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Rev 3022	Rev 4055
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
-		40	#include <typedefs.h>
40	#include <align.h>	41	#include <align.h>
41	#include <arch/register.h>	42	#include <arch/register.h>
42	#include <config.h>	43	#include <config.h>
43	#include <arch/stack.h>	44	#include <arch/stack.h>
-		45	#include <arch/barrier.h>
-		46
-		47	static inline void pio_write_8(ioport8_t *port, uint8_t v)
-		48	{
-		49	*port = v;
-		50	memory_barrier();
-		51	}
-		52
-		53	static inline void pio_write_16(ioport16_t *port, uint16_t v)
-		54	{
-		55	*port = v;
-		56	memory_barrier();
-		57	}
-		58
-		59	static inline void pio_write_32(ioport32_t *port, uint32_t v)
-		60	{
-		61	*port = v;
-		62	memory_barrier();
-		63	}
-		64
-		65	static inline uint8_t pio_read_8(ioport8_t *port)
-		66	{
-		67	uint8_t rv;
-		68
-		69	rv = *port;
-		70	memory_barrier();
-		71
-		72	return rv;
-		73	}
-		74
-		75	static inline uint16_t pio_read_16(ioport16_t *port)
-		76	{
-		77	uint16_t rv;
-		78
-		79	rv = *port;
-		80	memory_barrier();
-		81
-		82	return rv;
-		83	}
-		84
-		85	static inline uint32_t pio_read_32(ioport32_t *port)
-		86	{
-		87	uint32_t rv;
-		88
-		89	rv = *port;
-		90	memory_barrier();
-		91
-		92	return rv;
-		93	}
44		94
45	/** Read Processor State register.	95	/** Read Processor State register.
46	*	96	*
47	* @return Value of PSTATE register.	97	* @return Value of PSTATE register.
48	*/	98	*/
49	static inline uint64_t pstate_read(void)	99	static inline uint64_t pstate_read(void)
50	{	100	{
51	uint64_t v;	101	uint64_t v;
52		102
53	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
54		104
55	return v;	105	return v;
56	}	106	}
57		107
58	/** Write Processor State register.	108	/** Write Processor State register.
59	*	109	*
60	* @param v New value of PSTATE register.	110	* @param v New value of PSTATE register.
61	*/	111	*/
62	static inline void pstate_write(uint64_t v)	112	static inline void pstate_write(uint64_t v)
63	{	113	{
64	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
65	}	115	}
66		116
67	/** Read TICK_compare Register.	117	/** Read TICK_compare Register.
68	*	118	*
69	* @return Value of TICK_comapre register.	119	* @return Value of TICK_comapre register.
70	*/	120	*/
71	static inline uint64_t tick_compare_read(void)	121	static inline uint64_t tick_compare_read(void)
72	{	122	{
73	uint64_t v;	123	uint64_t v;
74		124
75	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
76		126
77	return v;	127	return v;
78	}	128	}
79		129
80	/** Write TICK_compare Register.	130	/** Write TICK_compare Register.
81	*	131	*
82	* @param v New value of TICK_comapre register.	132	* @param v New value of TICK_comapre register.
83	*/	133	*/
84	static inline void tick_compare_write(uint64_t v)	134	static inline void tick_compare_write(uint64_t v)
85	{	135	{
86	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
87	}	137	}
88		138
-		139	/** Read STICK_compare Register.
-		140	*
-		141	* @return Value of STICK_compare register.
-		142	*/
-		143	static inline uint64_t stick_compare_read(void)
-		144	{
-		145	uint64_t v;
-		146
-		147	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
-		148
-		149	return v;
-		150	}
-		151
-		152	/** Write STICK_compare Register.
-		153	*
-		154	* @param v New value of STICK_comapre register.
-		155	*/
-		156	static inline void stick_compare_write(uint64_t v)
-		157	{
-		158	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
-		159	}
-		160
89	/** Read TICK Register.	161	/** Read TICK Register.
90	*	162	*
91	* @return Value of TICK register.	163	* @return Value of TICK register.
92	*/	164	*/
93	static inline uint64_t tick_read(void)	165	static inline uint64_t tick_read(void)
94	{	166	{
95	uint64_t v;	167	uint64_t v;
96		168
97	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	169	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
98		170
99	return v;	171	return v;
100	}	172	}
101		173
102	/** Write TICK Register.	174	/** Write TICK Register.
103	*	175	*
104	* @param v New value of TICK register.	176	* @param v New value of TICK register.
105	*/	177	*/
106	static inline void tick_write(uint64_t v)	178	static inline void tick_write(uint64_t v)
107	{	179	{
108	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	180	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
109	}	181	}
110		182
111	/** Read FPRS Register.	183	/** Read FPRS Register.
112	*	184	*
113	* @return Value of FPRS register.	185	* @return Value of FPRS register.
114	*/	186	*/
115	static inline uint64_t fprs_read(void)	187	static inline uint64_t fprs_read(void)
116	{	188	{
117	uint64_t v;	189	uint64_t v;
118		190
119	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	191	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
120		192
121	return v;	193	return v;
122	}	194	}
123		195
124	/** Write FPRS Register.	196	/** Write FPRS Register.
125	*	197	*
126	* @param v New value of FPRS register.	198	* @param v New value of FPRS register.
127	*/	199	*/
128	static inline void fprs_write(uint64_t v)	200	static inline void fprs_write(uint64_t v)
129	{	201	{
130	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	202	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
131	}	203	}
132		204
133	/** Read SOFTINT Register.	205	/** Read SOFTINT Register.
134	*	206	*
135	* @return Value of SOFTINT register.	207	* @return Value of SOFTINT register.
136	*/	208	*/
137	static inline uint64_t softint_read(void)	209	static inline uint64_t softint_read(void)
138	{	210	{
139	uint64_t v;	211	uint64_t v;
140		212
141	asm volatile ("rd %%softint, %0\n" : "=r" (v));	213	asm volatile ("rd %%softint, %0\n" : "=r" (v));
142		214
143	return v;	215	return v;
144	}	216	}
145		217
146	/** Write SOFTINT Register.	218	/** Write SOFTINT Register.
147	*	219	*
148	* @param v New value of SOFTINT register.	220	* @param v New value of SOFTINT register.
149	*/	221	*/
150	static inline void softint_write(uint64_t v)	222	static inline void softint_write(uint64_t v)
151	{	223	{
152	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	224	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
153	}	225	}
154		226
155	/** Write CLEAR_SOFTINT Register.	227	/** Write CLEAR_SOFTINT Register.
156	*	228	*
157	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	229	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
158	*	230	*
159	* @param v New value of CLEAR_SOFTINT register.	231	* @param v New value of CLEAR_SOFTINT register.
160	*/	232	*/
161	static inline void clear_softint_write(uint64_t v)	233	static inline void clear_softint_write(uint64_t v)
162	{	234	{
163	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	235	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
164	}	236	}
165		237
166	/** Write SET_SOFTINT Register.	238	/** Write SET_SOFTINT Register.
167	*	239	*
168	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	240	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
169	*	241	*
170	* @param v New value of SET_SOFTINT register.	242	* @param v New value of SET_SOFTINT register.
171	*/	243	*/
172	static inline void set_softint_write(uint64_t v)	244	static inline void set_softint_write(uint64_t v)
173	{	245	{
174	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	246	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
175	}	247	}
176		248
177	/** Enable interrupts.	249	/** Enable interrupts.
178	*	250	*
179	* Enable interrupts and return previous	251	* Enable interrupts and return previous
180	* value of IPL.	252	* value of IPL.
181	*	253	*
182	* @return Old interrupt priority level.	254	* @return Old interrupt priority level.
183	*/	255	*/
184	static inline ipl_t interrupts_enable(void) {	256	static inline ipl_t interrupts_enable(void) {
185	pstate_reg_t pstate;	257	pstate_reg_t pstate;
186	uint64_t value;	258	uint64_t value;
187		259
188	value = pstate_read();	260	value = pstate_read();
189	pstate.value = value;	261	pstate.value = value;
190	pstate.ie = true;	262	pstate.ie = true;
191	pstate_write(pstate.value);	263	pstate_write(pstate.value);
192		264
193	return (ipl_t) value;	265	return (ipl_t) value;
194	}	266	}
195		267
196	/** Disable interrupts.	268	/** Disable interrupts.
197	*	269	*
198	* Disable interrupts and return previous	270	* Disable interrupts and return previous
199	* value of IPL.	271	* value of IPL.
200	*	272	*
201	* @return Old interrupt priority level.	273	* @return Old interrupt priority level.
202	*/	274	*/
203	static inline ipl_t interrupts_disable(void) {	275	static inline ipl_t interrupts_disable(void) {
204	pstate_reg_t pstate;	276	pstate_reg_t pstate;
205	uint64_t value;	277	uint64_t value;
206		278
207	value = pstate_read();	279	value = pstate_read();
208	pstate.value = value;	280	pstate.value = value;
209	pstate.ie = false;	281	pstate.ie = false;
210	pstate_write(pstate.value);	282	pstate_write(pstate.value);
211		283
212	return (ipl_t) value;	284	return (ipl_t) value;
213	}	285	}
214		286
215	/** Restore interrupt priority level.	287	/** Restore interrupt priority level.
216	*	288	*
217	* Restore IPL.	289	* Restore IPL.
218	*	290	*
219	* @param ipl Saved interrupt priority level.	291	* @param ipl Saved interrupt priority level.
220	*/	292	*/
221	static inline void interrupts_restore(ipl_t ipl) {	293	static inline void interrupts_restore(ipl_t ipl) {
222	pstate_reg_t pstate;	294	pstate_reg_t pstate;
223		295
224	pstate.value = pstate_read();	296	pstate.value = pstate_read();
225	pstate.ie = ((pstate_reg_t) ipl).ie;	297	pstate.ie = ((pstate_reg_t) ipl).ie;
226	pstate_write(pstate.value);	298	pstate_write(pstate.value);
227	}	299	}
228		300
229	/** Return interrupt priority level.	301	/** Return interrupt priority level.
230	*	302	*
231	* Return IPL.	303	* Return IPL.
232	*	304	*
233	* @return Current interrupt priority level.	305	* @return Current interrupt priority level.
234	*/	306	*/
235	static inline ipl_t interrupts_read(void) {	307	static inline ipl_t interrupts_read(void) {
236	return (ipl_t) pstate_read();	308	return (ipl_t) pstate_read();
237	}	309	}
238		310
239	/** Return base address of current stack.	311	/** Return base address of current stack.
240	*	312	*
241	* Return the base address of the current stack.	313	* Return the base address of the current stack.
242	* The stack is assumed to be STACK_SIZE bytes long.	314	* The stack is assumed to be STACK_SIZE bytes long.
243	* The stack must start on page boundary.	315	* The stack must start on page boundary.
244	*/	316	*/
245	static inline uintptr_t get_stack_base(void)	317	static inline uintptr_t get_stack_base(void)
246	{	318	{
247	uintptr_t unbiased_sp;	319	uintptr_t unbiased_sp;
248		320
249	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	321	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
250		322
251	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	323	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
252	}	324	}
253		325
254	/** Read Version Register.	326	/** Read Version Register.
255	*	327	*
256	* @return Value of VER register.	328	* @return Value of VER register.
257	*/	329	*/
258	static inline uint64_t ver_read(void)	330	static inline uint64_t ver_read(void)
259	{	331	{
260	uint64_t v;	332	uint64_t v;
261		333
262	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	334	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
263		335
264	return v;	336	return v;
265	}	337	}
266		338
267	/** Read Trap Program Counter register.	339	/** Read Trap Program Counter register.
268	*	340	*
269	* @return Current value in TPC.	341	* @return Current value in TPC.
270	*/	342	*/
271	static inline uint64_t tpc_read(void)	343	static inline uint64_t tpc_read(void)
272	{	344	{
273	uint64_t v;	345	uint64_t v;
274		346
275	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	347	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
276		348
277	return v;	349	return v;
278	}	350	}
279		351
280	/** Read Trap Level register.	352	/** Read Trap Level register.
281	*	353	*
282	* @return Current value in TL.	354	* @return Current value in TL.
283	*/	355	*/
284	static inline uint64_t tl_read(void)	356	static inline uint64_t tl_read(void)
285	{	357	{
286	uint64_t v;	358	uint64_t v;
287		359
288	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	360	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
289		361
290	return v;	362	return v;
291	}	363	}
292		364
293	/** Read Trap Base Address register.	365	/** Read Trap Base Address register.
294	*	366	*
295	* @return Current value in TBA.	367	* @return Current value in TBA.
296	*/	368	*/
297	static inline uint64_t tba_read(void)	369	static inline uint64_t tba_read(void)
298	{	370	{
299	uint64_t v;	371	uint64_t v;
300		372
301	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	373	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
302		374
303	return v;	375	return v;
304	}	376	}
305		377
306	/** Write Trap Base Address register.	378	/** Write Trap Base Address register.
307	*	379	*
308	* @param v New value of TBA.	380	* @param v New value of TBA.
309	*/	381	*/
310	static inline void tba_write(uint64_t v)	382	static inline void tba_write(uint64_t v)
311	{	383	{
312	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	384	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
313	}	385	}
314		386
315	/** Load uint64_t from alternate space.	387	/** Load uint64_t from alternate space.
316	*	388	*
317	* @param asi ASI determining the alternate space.	389	* @param asi ASI determining the alternate space.
318	* @param va Virtual address within the ASI.	390	* @param va Virtual address within the ASI.
319	*	391	*
320	* @return Value read from the virtual address in the specified address space.	392	* @return Value read from the virtual address in the specified address space.
321	*/	393	*/
322	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	394	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
323	{	395	{
324	uint64_t v;	396	uint64_t v;
325		397
326	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	398	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
327		399
328	return v;	400	return v;
329	}	401	}
330		402
331	/** Store uint64_t to alternate space.	403	/** Store uint64_t to alternate space.
332	*	404	*
333	* @param asi ASI determining the alternate space.	405	* @param asi ASI determining the alternate space.
334	* @param va Virtual address within the ASI.	406	* @param va Virtual address within the ASI.
335	* @param v Value to be written.	407	* @param v Value to be written.
336	*/	408	*/
337	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	409	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
338	{	410	{
339	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	411	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
340	}	412	}
341		413
342	/** Flush all valid register windows to memory. */	414	/** Flush all valid register windows to memory. */
343	static inline void flushw(void)	415	static inline void flushw(void)
344	{	416	{
345	asm volatile ("flushw\n");	417	asm volatile ("flushw\n");
346	}	418	}
347		419
348	/** Switch to nucleus by setting TL to 1. */	420	/** Switch to nucleus by setting TL to 1. */
349	static inline void nucleus_enter(void)	421	static inline void nucleus_enter(void)
350	{	422	{
351	asm volatile ("wrpr %g0, 1, %tl\n");	423	asm volatile ("wrpr %g0, 1, %tl\n");
352	}	424	}
353		425
354	/** Switch from nucleus by setting TL to 0. */	426	/** Switch from nucleus by setting TL to 0. */
355	static inline void nucleus_leave(void)	427	static inline void nucleus_leave(void)
356	{	428	{
357	asm volatile ("wrpr %g0, %g0, %tl\n");	429	asm volatile ("wrpr %g0, %g0, %tl\n");
358	}	430	}
359		-
360	/** Read UPA_CONFIG register.	-
361	*	-
362	* @return Value of the UPA_CONFIG register.	-
363	*/	-
364	static inline uint64_t upa_config_read(void)	-
365	{	-
366	return asi_u64_read(ASI_UPA_CONFIG, 0);	-
367	}	-
368		431
369	extern void cpu_halt(void);	432	extern void cpu_halt(void);
370	extern void cpu_sleep(void);	433	extern void cpu_sleep(void);
371	extern void asm_delay_loop(const uint32_t usec);	434	extern void asm_delay_loop(const uint32_t usec);
372		435
373	extern uint64_t read_from_ag_g7(void);	436	extern uint64_t read_from_ag_g7(void);
374	extern void write_to_ag_g6(uint64_t val);	437	extern void write_to_ag_g6(uint64_t val);
375	extern void write_to_ag_g7(uint64_t val);	438	extern void write_to_ag_g7(uint64_t val);
376	extern void write_to_ig_g6(uint64_t val);	439	extern void write_to_ig_g6(uint64_t val);
377		440
378	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	441	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
379		442
380	#endif	443	#endif
381		444
382	/** @}	445	/** @}
383	*/	446	*/
384		447

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