WebSVN – HelenOS – Diff – /branches/dd/kernel/arch/mips32/src/mm/tlb.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/mutex.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
 
static void tlb_refill_fail(istate_t *);
static void tlb_invalid_fail(istate_t *);
static void tlb_modified_fail(istate_t *);
 
static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *, int *);
 
 
 
 
/** Initialize TLB.
 *
 
 * Invalidate all entries and mark wired entries.
 */
void tlb_arch_init(void)
{
    int i;
 
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    cp0_entry_hi_write(0);
    cp0_entry_lo0_write(0);
    cp0_entry_lo1_write(0);
 
    /* Clear and initialize TLB. */
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbwi();
    }
 
       
    /*
     * The kernel is going to make use of some wired
     * entries (e.g. mapping kernel stacks in kseg3).
     */
    cp0_wired_write(TLB_WIRED);
}
 
/** Process TLB Refill Exception.
 
 
 *
 * @param istate    Interrupted register context.
 */
void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
   
    badvaddr = cp0_badvaddr_read();
   
    mutex_lock(&AS->lock);
    asid = AS->asid;
    mutex_unlock(&AS->lock);
   
    page_table_lock(AS, true);
   
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_hi(&hi, asid, badvaddr);
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
        pte->pfn);
 
    /*
     * New entry is to be inserted into TLB
     */
    cp0_entry_hi_write(hi.value);
    if ((badvaddr / PAGE_SIZE) % 2 == 0) {
        cp0_entry_lo0_write(lo.value);
        cp0_entry_lo1_write(0);
    }
    else {
        cp0_entry_lo0_write(0);
        cp0_entry_lo1_write(lo.value);
    }
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwr();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_refill_fail(istate);
}
 
/** Process TLB Invalid Exception.
 
 
 *
 * @param istate    Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access to PTE.
     */
    pte->a = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
        pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_invalid_fail(istate);
}
 
/** Process TLB Modified Exception.
 
 
 *
 * @param istate    Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 
    /*
     * Locate the faulting entry in TLB.
     */
    hi.value = cp0_entry_hi_read();
    tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
    cp0_entry_hi_write(hi.value);
    tlbp();
    index.value = cp0_index_read();
 
    page_table_lock(AS, true); 
   
    /*
     * Fail if the entry is not in TLB.
     */
    if (index.p) {
        printf("TLB entry not found.\n");
        goto fail;
    }
 
    pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
    if (!pte) {
        switch (pfrc) {
        case AS_PF_FAULT:
            goto fail;
            break;
        case AS_PF_DEFER:
            /*
             * The page fault came during copy_from_uspace()
             * or copy_to_uspace().
             */
            page_table_unlock(AS, true);             
            return;
        default:
            panic("Unexpected pfrc (%d).", pfrc);
        }
    }
 
    /*
 
 
 
 
 
 
     * Read the faulting TLB entry.
     */
    tlbr();
 
    /*
     * Record access and write to PTE.
     */
    pte->a = 1;
    pte->d = 1;
 
    tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
        pte->pfn);
 
    /*
     * The entry is to be updated in TLB.
     */
    if ((badvaddr / PAGE_SIZE) % 2 == 0)
        cp0_entry_lo0_write(lo.value);
    else
        cp0_entry_lo1_write(lo.value);
    cp0_pagemask_write(TLB_PAGE_MASK_16K);
    tlbwi();
 
    page_table_unlock(AS, true);
    return;
   
fail:
    page_table_unlock(AS, true);
    tlb_modified_fail(istate);
}
 
void tlb_refill_fail(istate_t *istate)
{
    char *symbol = "";
    char *sym2 = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    s = get_symtab_entry(istate->ra);
    if (s)
        sym2 = s;
 
    fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Refill Exception at %x(%s<-%s).", cp0_badvaddr_read(),
        istate->epc, symbol, sym2);
}
 
 
void tlb_invalid_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Invalid Exception at %x(%s).", cp0_badvaddr_read(),
        istate->epc, symbol);
}
 
void tlb_modified_fail(istate_t *istate)
{
    char *symbol = "";
 
    char *s = get_symtab_entry(istate->epc);
    if (s)
        symbol = s;
    fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
        cp0_badvaddr_read());
    panic("%x: TLB Modified Exception at %x(%s).", cp0_badvaddr_read(),
        istate->epc, symbol);
}
 
/** Try to find PTE for faulting address.
 *
 
 * The AS->lock must be held on entry to this function.
 *
 * @param badvaddr  Faulting virtual address.
 * @param access    Access mode that caused the fault.
 * @param istate    Pointer to interrupted state.
 * @param pfrc      Pointer to variable where as_page_fault() return code
 *          will be stored.
 *
 * @return      PTE on success, NULL otherwise.
 */
pte_t *
find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
    int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();
 
    /*
     * Handler cannot succeed if the ASIDs don't match.
     */
    if (hi.asid != AS->asid) {
        printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
        return NULL;
    }
 
    /*
     * Check if the mapping exists in page tables.
     */
    pte = page_mapping_find(AS, badvaddr);
    if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) {
        /*
         * Mapping found in page tables.
         * Immediately succeed.
         */
        return pte;
    } else {
        int rc;
       
        /*
         * Mapping not found in page tables.
         * Resort to higher-level page fault handler.
         */
        page_table_unlock(AS, true);
        switch (rc = as_page_fault(badvaddr, access, istate)) {
        case AS_PF_OK:
            /*
             * The higher-level page fault handler succeeded,
             * The mapping ought to be in place.
             */
            page_table_lock(AS, true);
            pte = page_mapping_find(AS, badvaddr);
            ASSERT(pte && pte->p);
            ASSERT(pte->w || access != PF_ACCESS_WRITE);
            return pte;
            break;
        case AS_PF_DEFER:
            page_table_lock(AS, true);
            *pfrc = AS_PF_DEFER;
            return NULL;
            break;
        case AS_PF_FAULT:
            page_table_lock(AS, true);
 
            *pfrc = AS_PF_FAULT;
            return NULL;
            break;
        default:
            panic("Unexpected rc (%d).", rc);
        }
       
    }
}
 
void
tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
    uintptr_t pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 
/** Print contents of TLB. */
void tlb_print(void)
{
    page_mask_t mask;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    unsigned int i;
 
    hi_save.value = cp0_entry_hi_read();
   
    printf("#  ASID VPN2   MASK G V D C PFN\n");
    printf("-- ---- ------ ---- - - - - ------\n");
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        mask.value = cp0_pagemask_read();
        hi.value = cp0_entry_hi_read();
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
       
        printf("%-2u %-4u %#6x %#4x %1u %1u %1u %1u %#6x\n",
            i, hi.asid, hi.vpn2, mask.mask,
            lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);
        printf("                    %1u %1u %1u %1u %#6x\n",
            lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
    }
   
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi_save;
    int i;
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
 
        lo0.value = cp0_entry_lo0_read();
        lo1.value = cp0_entry_lo1_read();
 
        lo0.v = 0;
        lo1.v = 0;
 
        cp0_entry_lo0_write(lo0.value);
        cp0_entry_lo1_write(lo1.value);
               
        tlbwi();
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate all TLB entries belonging to specified address space.
 *
 * @param asid Address space identifier.
 */
void tlb_invalidate_asid(asid_t asid)
{
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    int i;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
   
    for (i = 0; i < TLB_ENTRY_COUNT; i++) {
        cp0_index_write(i);
        tlbr();
       
        hi.value = cp0_entry_hi_read();
       
        if (hi.asid == asid) {
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** Invalidate TLB entries for specified page range belonging to specified
 * address space.
 *
 * @param asid      Address space identifier.
 * @param page      First page whose TLB entry is to be invalidated.
 * @param cnt       Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    unsigned int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;
    tlb_index_t index;
 
    ASSERT(asid != ASID_INVALID);
 
    hi_save.value = cp0_entry_hi_read();
    ipl = interrupts_disable();
 
    for (i = 0; i < cnt + 1; i += 2) {
        hi.value = 0;
        tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
        cp0_entry_hi_write(hi.value);
 
        tlbp();
        index.value = cp0_index_read();
 
        if (!index.p) {
            /*
             * Entry was found, index register contains valid
             * index.
             */
            tlbr();
 
            lo0.value = cp0_entry_lo0_read();
            lo1.value = cp0_entry_lo1_read();
 
            lo0.v = 0;
            lo1.v = 0;
 
            cp0_entry_lo0_write(lo0.value);
            cp0_entry_lo1_write(lo1.value);
 
            tlbwi();
        }
    }
   
    interrupts_restore(ipl);
    cp0_entry_hi_write(hi_save.value);
}
 
/** @}
 */
 

Rev 3022	Rev 4055
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32mm	29	/** @addtogroup mips32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/tlb.h>	35	#include <arch/mm/tlb.h>
36	#include <mm/asid.h>	36	#include <mm/asid.h>
37	#include <mm/tlb.h>	37	#include <mm/tlb.h>
38	#include <mm/page.h>	38	#include <mm/page.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <arch/cp0.h>	40	#include <arch/cp0.h>
41	#include <panic.h>	41	#include <panic.h>
42	#include <arch.h>	42	#include <arch.h>
43	#include <symtab.h>	43	#include <symtab.h>
44	#include <synch/spinlock.h>	44	#include <synch/mutex.h>
45	#include <print.h>	45	#include <print.h>
46	#include <debug.h>	46	#include <debug.h>
47	#include <align.h>	47	#include <align.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49		49
50	static void tlb_refill_fail(istate_t *istate);	50	static void tlb_refill_fail(istate_t *);
51	static void tlb_invalid_fail(istate_t *istate);	51	static void tlb_invalid_fail(istate_t *);
52	static void tlb_modified_fail(istate_t *istate);	52	static void tlb_modified_fail(istate_t *);
53		53
54	static pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc);	54	static pte_t find_mapping_and_check(uintptr_t, int, istate_t , int *);
55		55
56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);	-
57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);	-
58		-
59	/** Initialize TLB	56	/** Initialize TLB.
60	*	57	*
61	* Initialize TLB.	-
62	* Invalidate all entries and mark wired entries.	58	* Invalidate all entries and mark wired entries.
63	*/	59	*/
64	void tlb_arch_init(void)	60	void tlb_arch_init(void)
65	{	61	{
66	int i;	62	int i;
67		63
68	cp0_pagemask_write(TLB_PAGE_MASK_16K);	64	cp0_pagemask_write(TLB_PAGE_MASK_16K);
69	cp0_entry_hi_write(0);	65	cp0_entry_hi_write(0);
70	cp0_entry_lo0_write(0);	66	cp0_entry_lo0_write(0);
71	cp0_entry_lo1_write(0);	67	cp0_entry_lo1_write(0);
72		68
73	/* Clear and initialize TLB. */	69	/* Clear and initialize TLB. */
74		70
75	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	71	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
76	cp0_index_write(i);	72	cp0_index_write(i);
77	tlbwi();	73	tlbwi();
78	}	74	}
79		-
80		75
81	/*	76	/*
82	* The kernel is going to make use of some wired	77	* The kernel is going to make use of some wired
83	* entries (e.g. mapping kernel stacks in kseg3).	78	* entries (e.g. mapping kernel stacks in kseg3).
84	*/	79	*/
85	cp0_wired_write(TLB_WIRED);	80	cp0_wired_write(TLB_WIRED);
86	}	81	}
87		82
88	/** Process TLB Refill Exception	83	/** Process TLB Refill Exception.
89	*	-
90	* Process TLB Refill Exception.	-
91	*	84	*
92	* @param istate Interrupted register context.	85	* @param istate Interrupted register context.
93	*/	86	*/
94	void tlb_refill(istate_t *istate)	87	void tlb_refill(istate_t *istate)
95	{	88	{
96	entry_lo_t lo;	89	entry_lo_t lo;
97	entry_hi_t hi;	90	entry_hi_t hi;
98	asid_t asid;	91	asid_t asid;
99	uintptr_t badvaddr;	92	uintptr_t badvaddr;
100	pte_t *pte;	93	pte_t *pte;
101	int pfrc;	94	int pfrc;
102		95
103	badvaddr = cp0_badvaddr_read();	96	badvaddr = cp0_badvaddr_read();
104		97
105	spinlock_lock(&AS->lock);	98	mutex_lock(&AS->lock);
106	asid = AS->asid;	99	asid = AS->asid;
107	spinlock_unlock(&AS->lock);	100	mutex_unlock(&AS->lock);
108		101
109	page_table_lock(AS, true);	102	page_table_lock(AS, true);
110		103
111	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	104	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
112	if (!pte) {	105	if (!pte) {
113	switch (pfrc) {	106	switch (pfrc) {
114	case AS_PF_FAULT:	107	case AS_PF_FAULT:
115	goto fail;	108	goto fail;
116	break;	109	break;
117	case AS_PF_DEFER:	110	case AS_PF_DEFER:
118	/*	111	/*
119	* The page fault came during copy_from_uspace()	112	* The page fault came during copy_from_uspace()
120	* or copy_to_uspace().	113	* or copy_to_uspace().
121	*/	114	*/
122	page_table_unlock(AS, true);	115	page_table_unlock(AS, true);
123	return;	116	return;
124	default:	117	default:
125	panic("unexpected pfrc (%d)\n", pfrc);	118	panic("Unexpected pfrc (%d).", pfrc);
126	}	119	}
127	}	120	}
128		121
129	/*	122	/*
130	* Record access to PTE.	123	* Record access to PTE.
131	*/	124	*/
132	pte->a = 1;	125	pte->a = 1;
133		126
134	prepare_entry_hi(&hi, asid, badvaddr);	127	tlb_prepare_entry_hi(&hi, asid, badvaddr);
135	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	128	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
-		129	pte->pfn);
136		130
137	/*	131	/*
138	* New entry is to be inserted into TLB	132	* New entry is to be inserted into TLB
139	*/	133	*/
140	cp0_entry_hi_write(hi.value);	134	cp0_entry_hi_write(hi.value);
141	if ((badvaddr/PAGE_SIZE) % 2 == 0) {	135	if ((badvaddr / PAGE_SIZE) % 2 == 0) {
142	cp0_entry_lo0_write(lo.value);	136	cp0_entry_lo0_write(lo.value);
143	cp0_entry_lo1_write(0);	137	cp0_entry_lo1_write(0);
144	}	138	}
145	else {	139	else {
146	cp0_entry_lo0_write(0);	140	cp0_entry_lo0_write(0);
147	cp0_entry_lo1_write(lo.value);	141	cp0_entry_lo1_write(lo.value);
148	}	142	}
149	cp0_pagemask_write(TLB_PAGE_MASK_16K);	143	cp0_pagemask_write(TLB_PAGE_MASK_16K);
150	tlbwr();	144	tlbwr();
151		145
152	page_table_unlock(AS, true);	146	page_table_unlock(AS, true);
153	return;	147	return;
154		148
155	fail:	149	fail:
156	page_table_unlock(AS, true);	150	page_table_unlock(AS, true);
157	tlb_refill_fail(istate);	151	tlb_refill_fail(istate);
158	}	152	}
159		153
160	/** Process TLB Invalid Exception	154	/** Process TLB Invalid Exception.
161	*	-
162	* Process TLB Invalid Exception.	-
163	*	155	*
164	* @param istate Interrupted register context.	156	* @param istate Interrupted register context.
165	*/	157	*/
166	void tlb_invalid(istate_t *istate)	158	void tlb_invalid(istate_t *istate)
167	{	159	{
168	tlb_index_t index;	160	tlb_index_t index;
169	uintptr_t badvaddr;	161	uintptr_t badvaddr;
170	entry_lo_t lo;	162	entry_lo_t lo;
171	entry_hi_t hi;	163	entry_hi_t hi;
172	pte_t *pte;	164	pte_t *pte;
173	int pfrc;	165	int pfrc;
174		166
175	badvaddr = cp0_badvaddr_read();	167	badvaddr = cp0_badvaddr_read();
176		168
177	/*	169	/*
178	* Locate the faulting entry in TLB.	170	* Locate the faulting entry in TLB.
179	*/	171	*/
180	hi.value = cp0_entry_hi_read();	172	hi.value = cp0_entry_hi_read();
181	prepare_entry_hi(&hi, hi.asid, badvaddr);	173	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
182	cp0_entry_hi_write(hi.value);	174	cp0_entry_hi_write(hi.value);
183	tlbp();	175	tlbp();
184	index.value = cp0_index_read();	176	index.value = cp0_index_read();
185		177
186	page_table_lock(AS, true);	178	page_table_lock(AS, true);
187		179
188	/*	180	/*
189	* Fail if the entry is not in TLB.	181	* Fail if the entry is not in TLB.
190	*/	182	*/
191	if (index.p) {	183	if (index.p) {
192	printf("TLB entry not found.\n");	184	printf("TLB entry not found.\n");
193	goto fail;	185	goto fail;
194	}	186	}
195		187
196	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);	188	pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
197	if (!pte) {	189	if (!pte) {
198	switch (pfrc) {	190	switch (pfrc) {
199	case AS_PF_FAULT:	191	case AS_PF_FAULT:
200	goto fail;	192	goto fail;
201	break;	193	break;
202	case AS_PF_DEFER:	194	case AS_PF_DEFER:
203	/*	195	/*
204	* The page fault came during copy_from_uspace()	196	* The page fault came during copy_from_uspace()
205	* or copy_to_uspace().	197	* or copy_to_uspace().
206	*/	198	*/
207	page_table_unlock(AS, true);	199	page_table_unlock(AS, true);
208	return;	200	return;
209	default:	201	default:
210	panic("unexpected pfrc (%d)\n", pfrc);	202	panic("Unexpected pfrc (%d).", pfrc);
211	}	203	}
212	}	204	}
213		205
214	/*	206	/*
215	* Read the faulting TLB entry.	207	* Read the faulting TLB entry.
216	*/	208	*/
217	tlbr();	209	tlbr();
218		210
219	/*	211	/*
220	* Record access to PTE.	212	* Record access to PTE.
221	*/	213	*/
222	pte->a = 1;	214	pte->a = 1;
223		215
224	prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);	216	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable,
-		217	pte->pfn);
225		218
226	/*	219	/*
227	* The entry is to be updated in TLB.	220	* The entry is to be updated in TLB.
228	*/	221	*/
229	if ((badvaddr/PAGE_SIZE) % 2 == 0)	222	if ((badvaddr / PAGE_SIZE) % 2 == 0)
230	cp0_entry_lo0_write(lo.value);	223	cp0_entry_lo0_write(lo.value);
231	else	224	else
232	cp0_entry_lo1_write(lo.value);	225	cp0_entry_lo1_write(lo.value);
233	cp0_pagemask_write(TLB_PAGE_MASK_16K);	226	cp0_pagemask_write(TLB_PAGE_MASK_16K);
234	tlbwi();	227	tlbwi();
235		228
236	page_table_unlock(AS, true);	229	page_table_unlock(AS, true);
237	return;	230	return;
238		231
239	fail:	232	fail:
240	page_table_unlock(AS, true);	233	page_table_unlock(AS, true);
241	tlb_invalid_fail(istate);	234	tlb_invalid_fail(istate);
242	}	235	}
243		236
244	/** Process TLB Modified Exception	237	/** Process TLB Modified Exception.
245	*	-
246	* Process TLB Modified Exception.	-
247	*	238	*
248	* @param istate Interrupted register context.	239	* @param istate Interrupted register context.
249	*/	240	*/
250	void tlb_modified(istate_t *istate)	241	void tlb_modified(istate_t *istate)
251	{	242	{
252	tlb_index_t index;	243	tlb_index_t index;
253	uintptr_t badvaddr;	244	uintptr_t badvaddr;
254	entry_lo_t lo;	245	entry_lo_t lo;
255	entry_hi_t hi;	246	entry_hi_t hi;
256	pte_t *pte;	247	pte_t *pte;
257	int pfrc;	248	int pfrc;
258		249
259	badvaddr = cp0_badvaddr_read();	250	badvaddr = cp0_badvaddr_read();
260		251
261	/*	252	/*
262	* Locate the faulting entry in TLB.	253	* Locate the faulting entry in TLB.
263	*/	254	*/
264	hi.value = cp0_entry_hi_read();	255	hi.value = cp0_entry_hi_read();
265	prepare_entry_hi(&hi, hi.asid, badvaddr);	256	tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
266	cp0_entry_hi_write(hi.value);	257	cp0_entry_hi_write(hi.value);
267	tlbp();	258	tlbp();
268	index.value = cp0_index_read();	259	index.value = cp0_index_read();
269		260
270	page_table_lock(AS, true);	261	page_table_lock(AS, true);
271		262
272	/*	263	/*
273	* Fail if the entry is not in TLB.	264	* Fail if the entry is not in TLB.
274	*/	265	*/
275	if (index.p) {	266	if (index.p) {
276	printf("TLB entry not found.\n");	267	printf("TLB entry not found.\n");
277	goto fail;	268	goto fail;
278	}	269	}
279		270
280	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);	271	pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
281	if (!pte) {	272	if (!pte) {
282	switch (pfrc) {	273	switch (pfrc) {
283	case AS_PF_FAULT:	274	case AS_PF_FAULT:
284	goto fail;	275	goto fail;
285	break;	276	break;
286	case AS_PF_DEFER:	277	case AS_PF_DEFER:
287	/*	278	/*
288	* The page fault came during copy_from_uspace()	279	* The page fault came during copy_from_uspace()
289	* or copy_to_uspace().	280	* or copy_to_uspace().
290	*/	281	*/
291	page_table_unlock(AS, true);	282	page_table_unlock(AS, true);
292	return;	283	return;
293	default:	284	default:
294	panic("unexpected pfrc (%d)\n", pfrc);	285	panic("Unexpected pfrc (%d).", pfrc);
295	}	286	}
296	}	287	}
297		288
298	/*	289	/*
299	* Fail if the page is not writable.	-
300	*/	-
301	if (!pte->w)	-
302	goto fail;	-
303		-
304	/*	-
305	* Read the faulting TLB entry.	290	* Read the faulting TLB entry.
306	*/	291	*/
307	tlbr();	292	tlbr();
308		293
309	/*	294	/*
310	* Record access and write to PTE.	295	* Record access and write to PTE.
311	*/	296	*/
312	pte->a = 1;	297	pte->a = 1;
313	pte->d = 1;	298	pte->d = 1;
314		299
315	prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);	300	tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable,
-		301	pte->pfn);
316		302
317	/*	303	/*
318	* The entry is to be updated in TLB.	304	* The entry is to be updated in TLB.
319	*/	305	*/
320	if ((badvaddr/PAGE_SIZE) % 2 == 0)	306	if ((badvaddr / PAGE_SIZE) % 2 == 0)
321	cp0_entry_lo0_write(lo.value);	307	cp0_entry_lo0_write(lo.value);
322	else	308	else
323	cp0_entry_lo1_write(lo.value);	309	cp0_entry_lo1_write(lo.value);
324	cp0_pagemask_write(TLB_PAGE_MASK_16K);	310	cp0_pagemask_write(TLB_PAGE_MASK_16K);
325	tlbwi();	311	tlbwi();
326		312
327	page_table_unlock(AS, true);	313	page_table_unlock(AS, true);
328	return;	314	return;
329		315
330	fail:	316	fail:
331	page_table_unlock(AS, true);	317	page_table_unlock(AS, true);
332	tlb_modified_fail(istate);	318	tlb_modified_fail(istate);
333	}	319	}
334		320
335	void tlb_refill_fail(istate_t *istate)	321	void tlb_refill_fail(istate_t *istate)
336	{	322	{
337	char *symbol = "";	323	char *symbol = "";
338	char *sym2 = "";	324	char *sym2 = "";
339		325
340	char *s = get_symtab_entry(istate->epc);	326	char *s = get_symtab_entry(istate->epc);
341	if (s)	327	if (s)
342	symbol = s;	328	symbol = s;
343	s = get_symtab_entry(istate->ra);	329	s = get_symtab_entry(istate->ra);
344	if (s)	330	if (s)
345	sym2 = s;	331	sym2 = s;
346		332
347	fault_if_from_uspace(istate, "TLB Refill Exception on %p", cp0_badvaddr_read());	333	fault_if_from_uspace(istate, "TLB Refill Exception on %p.",
-		334	cp0_badvaddr_read());
348	panic("%x: TLB Refill Exception at %x(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);	335	panic("%x: TLB Refill Exception at %x(%s<-%s).", cp0_badvaddr_read(),
-		336	istate->epc, symbol, sym2);
349	}	337	}
350		338
351		339
352	void tlb_invalid_fail(istate_t *istate)	340	void tlb_invalid_fail(istate_t *istate)
353	{	341	{
354	char *symbol = "";	342	char *symbol = "";
355		343
356	char *s = get_symtab_entry(istate->epc);	344	char *s = get_symtab_entry(istate->epc);
357	if (s)	345	if (s)
358	symbol = s;	346	symbol = s;
359	fault_if_from_uspace(istate, "TLB Invalid Exception on %p", cp0_badvaddr_read());	347	fault_if_from_uspace(istate, "TLB Invalid Exception on %p.",
-		348	cp0_badvaddr_read());
360	panic("%x: TLB Invalid Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	349	panic("%x: TLB Invalid Exception at %x(%s).", cp0_badvaddr_read(),
-		350	istate->epc, symbol);
361	}	351	}
362		352
363	void tlb_modified_fail(istate_t *istate)	353	void tlb_modified_fail(istate_t *istate)
364	{	354	{
365	char *symbol = "";	355	char *symbol = "";
366		356
367	char *s = get_symtab_entry(istate->epc);	357	char *s = get_symtab_entry(istate->epc);
368	if (s)	358	if (s)
369	symbol = s;	359	symbol = s;
370	fault_if_from_uspace(istate, "TLB Modified Exception on %p", cp0_badvaddr_read());	360	fault_if_from_uspace(istate, "TLB Modified Exception on %p.",
-		361	cp0_badvaddr_read());
371	panic("%x: TLB Modified Exception at %x(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);	362	panic("%x: TLB Modified Exception at %x(%s).", cp0_badvaddr_read(),
-		363	istate->epc, symbol);
372	}	364	}
373		365
374	/** Try to find PTE for faulting address	366	/** Try to find PTE for faulting address.
375	*	367	*
376	* Try to find PTE for faulting address.	-
377	* The AS->lock must be held on entry to this function.	368	* The AS->lock must be held on entry to this function.
378	*	369	*
379	* @param badvaddr Faulting virtual address.	370	* @param badvaddr Faulting virtual address.
380	* @param access Access mode that caused the fault.	371	* @param access Access mode that caused the fault.
381	* @param istate Pointer to interrupted state.	372	* @param istate Pointer to interrupted state.
382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	373	* @param pfrc Pointer to variable where as_page_fault() return code
-		374	* will be stored.
383	*	375	*
384	* @return PTE on success, NULL otherwise.	376	* @return PTE on success, NULL otherwise.
385	*/	377	*/
-		378	pte_t *
386	pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc)	379	find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate,
-		380	int *pfrc)
387	{	381	{
388	entry_hi_t hi;	382	entry_hi_t hi;
389	pte_t *pte;	383	pte_t *pte;
390		384
391	hi.value = cp0_entry_hi_read();	385	hi.value = cp0_entry_hi_read();
392		386
393	/*	387	/*
394	* Handler cannot succeed if the ASIDs don't match.	388	* Handler cannot succeed if the ASIDs don't match.
395	*/	389	*/
396	if (hi.asid != AS->asid) {	390	if (hi.asid != AS->asid) {
397	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);	391	printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
398	return NULL;	392	return NULL;
399	}	393	}
400		394
401	/*	395	/*
402	* Check if the mapping exists in page tables.	396	* Check if the mapping exists in page tables.
403	*/	397	*/
404	pte = page_mapping_find(AS, badvaddr);	398	pte = page_mapping_find(AS, badvaddr);
405	if (pte && pte->p) {	399	if (pte && pte->p && (pte->w \|\| access != PF_ACCESS_WRITE)) {
406	/*	400	/*
407	* Mapping found in page tables.	401	* Mapping found in page tables.
408	* Immediately succeed.	402	* Immediately succeed.
409	*/	403	*/
410	return pte;	404	return pte;
411	} else {	405	} else {
412	int rc;	406	int rc;
413		407
414	/*	408	/*
415	* Mapping not found in page tables.	409	* Mapping not found in page tables.
416	* Resort to higher-level page fault handler.	410	* Resort to higher-level page fault handler.
417	*/	411	*/
418	page_table_unlock(AS, true);	412	page_table_unlock(AS, true);
419	switch (rc = as_page_fault(badvaddr, access, istate)) {	413	switch (rc = as_page_fault(badvaddr, access, istate)) {
420	case AS_PF_OK:	414	case AS_PF_OK:
421	/*	415	/*
422	* The higher-level page fault handler succeeded,	416	* The higher-level page fault handler succeeded,
423	* The mapping ought to be in place.	417	* The mapping ought to be in place.
424	*/	418	*/
425	page_table_lock(AS, true);	419	page_table_lock(AS, true);
426	pte = page_mapping_find(AS, badvaddr);	420	pte = page_mapping_find(AS, badvaddr);
427	ASSERT(pte && pte->p);	421	ASSERT(pte && pte->p);
-		422	ASSERT(pte->w \|\| access != PF_ACCESS_WRITE);
428	return pte;	423	return pte;
429	break;	424	break;
430	case AS_PF_DEFER:	425	case AS_PF_DEFER:
431	page_table_lock(AS, true);	426	page_table_lock(AS, true);
432	*pfrc = AS_PF_DEFER;	427	*pfrc = AS_PF_DEFER;
433	return NULL;	428	return NULL;
434	break;	429	break;
435	case AS_PF_FAULT:	430	case AS_PF_FAULT:
436	page_table_lock(AS, true);	431	page_table_lock(AS, true);
437	printf("Page fault.\n");	-
438	*pfrc = AS_PF_FAULT;	432	*pfrc = AS_PF_FAULT;
439	return NULL;	433	return NULL;
440	break;	434	break;
441	default:	435	default:
442	panic("unexpected rc (%d)\n", rc);	436	panic("Unexpected rc (%d).", rc);
443	}	437	}
444		438
445	}	439	}
446	}	440	}
447		441
-		442	void
448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)	443	tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable,
-		444	uintptr_t pfn)
449	{	445	{
450	lo->value = 0;	446	lo->value = 0;
451	lo->g = g;	447	lo->g = g;
452	lo->v = v;	448	lo->v = v;
453	lo->d = d;	449	lo->d = d;
454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	450	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
455	lo->pfn = pfn;	451	lo->pfn = pfn;
456	}	452	}
457		453
458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)	454	void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
459	{	455	{
460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	456	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
461	hi->asid = asid;	457	hi->asid = asid;
462	}	458	}
463		459
464	/** Print contents of TLB. */	460	/** Print contents of TLB. */
465	void tlb_print(void)	461	void tlb_print(void)
466	{	462	{
467	page_mask_t mask;	463	page_mask_t mask;
468	entry_lo_t lo0, lo1;	464	entry_lo_t lo0, lo1;
469	entry_hi_t hi, hi_save;	465	entry_hi_t hi, hi_save;
470	unsigned int i;	466	unsigned int i;
471		467
472	hi_save.value = cp0_entry_hi_read();	468	hi_save.value = cp0_entry_hi_read();
473		469
474	printf("# ASID VPN2 MASK G V D C PFN\n");	470	printf("# ASID VPN2 MASK G V D C PFN\n");
475	printf("-- ---- ------ ---- - - - - ------\n");	471	printf("-- ---- ------ ---- - - - - ------\n");
476		472
477	for (i = 0; i < TLB_ENTRY_COUNT; i++) {	473	for (i = 0; i < TLB_ENTRY_COUNT; i++) {
478	cp0_index_write(i);	474	cp0_index_write(i);
479	tlbr();	475	tlbr();
480		476
481	mask.value = cp0_pagemask_read();	477	mask.value = cp0_pagemask_read();
482	hi.value = cp0_entry_hi_read();	478	hi.value = cp0_entry_hi_read();
483	lo0.value = cp0_entry_lo0_read();	479	lo0.value = cp0_entry_lo0_read();
484	lo1.value = cp0_entry_lo1_read();	480	lo1.value = cp0_entry_lo1_read();
485		481

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(root)/branches/dd/kernel/arch/mips32/src/mm/tlb.c – Rev 3022 → 4055