WebSVN – HelenOS – Diff – /branches/dd/kernel/arch/mips32/src/interrupt.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32interrupt
 * @{
 */
/** @file
 */
 
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <arch/cp0.h>
#include <time/clock.h>
 
#include <ipc/sysipc.h>
#include <ddi/device.h>
 
#define IRQ_COUNT   8
#define TIMER_IRQ   7
#define DORDER_IRQ  5
 
function virtual_timer_fnc = NULL;
static irq_t timer_irq;
 
/** Disable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_disable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Enable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_enable(void)
{
    ipl_t ipl = (ipl_t) cp0_status_read();
    cp0_status_write(ipl | cp0_status_ie_enabled_bit);
    return ipl;
}
 
/** Restore interrupt priority level.
 *
 * @param ipl Saved interrupt priority level.
 */
void interrupts_restore(ipl_t ipl)
{
    cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
}
 
/** Read interrupt priority level.
 *
 * @return Current interrupt priority level.
 */
ipl_t interrupts_read(void)
{
    return cp0_status_read();
}
 
/* TODO: This is SMP unsafe!!! */
uint32_t count_hi = 0;
static unsigned long nextcount;
static unsigned long lastcount;
 
/** Start hardware clock */
static void timer_start(void)
{
    lastcount = cp0_count_read();
    nextcount = cp0_compare_value + cp0_count_read();
    cp0_compare_write(nextcount);
}
 
static irq_ownership_t timer_claim(irq_t *irq)
{
    return IRQ_ACCEPT;
}
 
static void timer_irq_handler(irq_t *irq)
{
    unsigned long drift;
   
    if (cp0_count_read() < lastcount)
        /* Count overflow detected */
        count_hi++;
    lastcount = cp0_count_read();
   
    drift = cp0_count_read() - nextcount;
    while (drift > cp0_compare_value) {
        drift -= cp0_compare_value;
        CPU->missed_clock_ticks++;
    }
    nextcount = cp0_count_read() + cp0_compare_value - drift;
    cp0_compare_write(nextcount);
   
    /*
     * We are holding a lock which prevents preemption.
     * Release the lock, call clock() and reacquire the lock again.
     */
    spinlock_unlock(&irq->lock);
    clock();
    spinlock_lock(&irq->lock);
   
    if (virtual_timer_fnc != NULL)
        virtual_timer_fnc();
}
 
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
    irq_init(IRQ_COUNT, IRQ_COUNT);
   
    irq_initialize(&timer_irq);
    timer_irq.devno = device_assign_devno();
    timer_irq.inr = TIMER_IRQ;
    timer_irq.claim = timer_claim;
    timer_irq.handler = timer_irq_handler;
    irq_register(&timer_irq);
   
    timer_start();
    cp0_unmask_int(TIMER_IRQ);
}
 
/** @}
 */
 

Rev 3022	Rev 4055
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32interrupt	29	/** @addtogroup mips32interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <interrupt.h>	35	#include <interrupt.h>
36	#include <arch/interrupt.h>	36	#include <arch/interrupt.h>
37	#include <arch/types.h>	37	#include <arch/types.h>
38	#include <arch.h>	38	#include <arch.h>
39	#include <arch/cp0.h>	39	#include <arch/cp0.h>
40	#include <time/clock.h>	40	#include <time/clock.h>
41	#include <arch/drivers/arc.h>	-
42	#include <ipc/sysipc.h>	41	#include <ipc/sysipc.h>
43	#include <ddi/device.h>	42	#include <ddi/device.h>
44		43
45	#define IRQ_COUNT 8	44	#define IRQ_COUNT 8
46	#define TIMER_IRQ 7	45	#define TIMER_IRQ 7
-		46	#define DORDER_IRQ 5
47		47
48	function virtual_timer_fnc = NULL;	48	function virtual_timer_fnc = NULL;
49	static irq_t timer_irq;	49	static irq_t timer_irq;
50		50
51	/** Disable interrupts.	51	/** Disable interrupts.
52	*	52	*
53	* @return Old interrupt priority level.	53	* @return Old interrupt priority level.
54	*/	54	*/
55	ipl_t interrupts_disable(void)	55	ipl_t interrupts_disable(void)
56	{	56	{
57	ipl_t ipl = (ipl_t) cp0_status_read();	57	ipl_t ipl = (ipl_t) cp0_status_read();
58	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);	58	cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
59	return ipl;	59	return ipl;
60	}	60	}
61		61
62	/** Enable interrupts.	62	/** Enable interrupts.
63	*	63	*
64	* @return Old interrupt priority level.	64	* @return Old interrupt priority level.
65	*/	65	*/
66	ipl_t interrupts_enable(void)	66	ipl_t interrupts_enable(void)
67	{	67	{
68	ipl_t ipl = (ipl_t) cp0_status_read();	68	ipl_t ipl = (ipl_t) cp0_status_read();
69	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);	69	cp0_status_write(ipl \| cp0_status_ie_enabled_bit);
70	return ipl;	70	return ipl;
71	}	71	}
72		72
73	/** Restore interrupt priority level.	73	/** Restore interrupt priority level.
74	*	74	*
75	* @param ipl Saved interrupt priority level.	75	* @param ipl Saved interrupt priority level.
76	*/	76	*/
77	void interrupts_restore(ipl_t ipl)	77	void interrupts_restore(ipl_t ipl)
78	{	78	{
79	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));	79	cp0_status_write(cp0_status_read() \| (ipl & cp0_status_ie_enabled_bit));
80	}	80	}
81		81
82	/** Read interrupt priority level.	82	/** Read interrupt priority level.
83	*	83	*
84	* @return Current interrupt priority level.	84	* @return Current interrupt priority level.
85	*/	85	*/
86	ipl_t interrupts_read(void)	86	ipl_t interrupts_read(void)
87	{	87	{
88	return cp0_status_read();	88	return cp0_status_read();
89	}	89	}
90		90
91	/* TODO: This is SMP unsafe!!! */	91	/* TODO: This is SMP unsafe!!! */
92	uint32_t count_hi = 0;	92	uint32_t count_hi = 0;
93	static unsigned long nextcount;	93	static unsigned long nextcount;
94	static unsigned long lastcount;	94	static unsigned long lastcount;
95		95
96	/** Start hardware clock */	96	/** Start hardware clock */
97	static void timer_start(void)	97	static void timer_start(void)
98	{	98	{
99	lastcount = cp0_count_read();	99	lastcount = cp0_count_read();
100	nextcount = cp0_compare_value + cp0_count_read();	100	nextcount = cp0_compare_value + cp0_count_read();
101	cp0_compare_write(nextcount);	101	cp0_compare_write(nextcount);
102	}	102	}
103		103
104	static irq_ownership_t timer_claim(void)	104	static irq_ownership_t timer_claim(irq_t *irq)
105	{	105	{
106	return IRQ_ACCEPT;	106	return IRQ_ACCEPT;
107	}	107	}
108		108
109	static void timer_irq_handler(irq_t irq, void arg, ...)	109	static void timer_irq_handler(irq_t *irq)
110	{	110	{
111	unsigned long drift;	111	unsigned long drift;
112		112
113	if (cp0_count_read() < lastcount)	113	if (cp0_count_read() < lastcount)
114	/* Count overflow detected */	114	/* Count overflow detected */
115	count_hi++;	115	count_hi++;
116	lastcount = cp0_count_read();	116	lastcount = cp0_count_read();
117		117
118	drift = cp0_count_read() - nextcount;	118	drift = cp0_count_read() - nextcount;
119	while (drift > cp0_compare_value) {	119	while (drift > cp0_compare_value) {
120	drift -= cp0_compare_value;	120	drift -= cp0_compare_value;
121	CPU->missed_clock_ticks++;	121	CPU->missed_clock_ticks++;
122	}	122	}
123	nextcount = cp0_count_read() + cp0_compare_value - drift;	123	nextcount = cp0_count_read() + cp0_compare_value - drift;
124	cp0_compare_write(nextcount);	124	cp0_compare_write(nextcount);
125		125
126	/*	126	/*
127	* We are holding a lock which prevents preemption.	127	* We are holding a lock which prevents preemption.
128	* Release the lock, call clock() and reacquire the lock again.	128	* Release the lock, call clock() and reacquire the lock again.
129	*/	129	*/
130	spinlock_unlock(&irq->lock);	130	spinlock_unlock(&irq->lock);
131	clock();	131	clock();
132	spinlock_lock(&irq->lock);	132	spinlock_lock(&irq->lock);
133		133
134	if (virtual_timer_fnc != NULL)	134	if (virtual_timer_fnc != NULL)
135	virtual_timer_fnc();	135	virtual_timer_fnc();
136	}	136	}
137		137
138	/* Initialize basic tables for exception dispatching */	138	/* Initialize basic tables for exception dispatching */
139	void interrupt_init(void)	139	void interrupt_init(void)
140	{	140	{
141	irq_init(IRQ_COUNT, IRQ_COUNT);	141	irq_init(IRQ_COUNT, IRQ_COUNT);
142		142
143	irq_initialize(&timer_irq);	143	irq_initialize(&timer_irq);
144	timer_irq.devno = device_assign_devno();	144	timer_irq.devno = device_assign_devno();
145	timer_irq.inr = TIMER_IRQ;	145	timer_irq.inr = TIMER_IRQ;
146	timer_irq.claim = timer_claim;	146	timer_irq.claim = timer_claim;
147	timer_irq.handler = timer_irq_handler;	147	timer_irq.handler = timer_irq_handler;
148	irq_register(&timer_irq);	148	irq_register(&timer_irq);
149		149
150	timer_start();	150	timer_start();
151	cp0_unmask_int(TIMER_IRQ);	151	cp0_unmask_int(TIMER_IRQ);
152	}	152	}
153		153
154	/** @}	154	/** @}
155	*/	155	*/
156		156

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(root)/branches/dd/kernel/arch/mips32/src/interrupt.c – Rev 3022 → 4055