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1 | /* |
1 | /* |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
2 | * Copyright (C) 2001-2004 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | #ifndef __ia32_ASM_H__ |
29 | #ifndef __ia32_ASM_H__ |
30 | #define __ia32_ASM_H__ |
30 | #define __ia32_ASM_H__ |
31 | 31 | ||
32 | #include <arch/types.h> |
32 | #include <arch/types.h> |
33 | #include <config.h> |
33 | #include <config.h> |
34 | 34 | ||
35 | extern __u32 interrupt_handler_size; |
35 | extern __u32 interrupt_handler_size; |
36 | 36 | ||
37 | extern void paging_on(void); |
37 | extern void paging_on(void); |
38 | 38 | ||
39 | extern void interrupt_handlers(void); |
39 | extern void interrupt_handlers(void); |
40 | 40 | ||
41 | extern __u8 inb(int port); |
41 | extern __u8 inb(int port); |
42 | extern __u16 inw(int port); |
42 | extern __u16 inw(int port); |
43 | extern __u32 inl(int port); |
43 | extern __u32 inl(int port); |
44 | 44 | ||
45 | extern void outw(int port, __u16 w); |
- | |
46 | extern void outl(int port, __u32 l); |
- | |
47 | - | ||
48 | extern void enable_l_apic_in_msr(void); |
45 | extern void enable_l_apic_in_msr(void); |
49 | 46 | ||
50 | 47 | ||
51 | void asm_delay_loop(__u32 t); |
48 | void asm_delay_loop(__u32 t); |
52 | void asm_fake_loop(__u32 t); |
49 | void asm_fake_loop(__u32 t); |
53 | 50 | ||
54 | 51 | ||
55 | /** Halt CPU |
52 | /** Halt CPU |
56 | * |
53 | * |
57 | * Halt the current CPU until interrupt event. |
54 | * Halt the current CPU until interrupt event. |
58 | */ |
55 | */ |
59 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
56 | static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
60 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
57 | static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
61 | 58 | ||
62 | /** Read CR2 |
59 | /** Read CR2 |
63 | * |
60 | * |
64 | * Return value in CR2 |
61 | * Return value in CR2 |
65 | * |
62 | * |
66 | * @return Value read. |
63 | * @return Value read. |
67 | */ |
64 | */ |
68 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
65 | static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; } |
69 | 66 | ||
70 | /** Write CR3 |
67 | /** Write CR3 |
71 | * |
68 | * |
72 | * Write value to CR3. |
69 | * Write value to CR3. |
73 | * |
70 | * |
74 | * @param v Value to be written. |
71 | * @param v Value to be written. |
75 | */ |
72 | */ |
76 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
73 | static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } |
77 | 74 | ||
78 | /** Read CR3 |
75 | /** Read CR3 |
79 | * |
76 | * |
80 | * Return value in CR3 |
77 | * Return value in CR3 |
81 | * |
78 | * |
82 | * @return Value read. |
79 | * @return Value read. |
83 | */ |
80 | */ |
84 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
81 | static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; } |
85 | 82 | ||
86 | /** Byte to port |
83 | /** Byte to port |
87 | * |
84 | * |
88 | * Output byte to port |
85 | * Output byte to port |
89 | * |
86 | * |
90 | * @param port Port to write to |
87 | * @param port Port to write to |
91 | * @param val Value to write |
88 | * @param val Value to write |
92 | */ |
89 | */ |
93 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
90 | static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
94 | 91 | ||
- | 92 | /** Word to port |
|
- | 93 | * |
|
- | 94 | * Output word to port |
|
- | 95 | * |
|
- | 96 | * @param port Port to write to |
|
- | 97 | * @param val Value to write |
|
- | 98 | */ |
|
- | 99 | static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
|
- | 100 | ||
- | 101 | ||
- | 102 | ||
- | 103 | /** Double word to port |
|
- | 104 | * |
|
- | 105 | * Output double word to port |
|
- | 106 | * |
|
- | 107 | * @param port Port to write to |
|
- | 108 | * @param val Value to write |
|
- | 109 | */ |
|
- | 110 | static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
|
95 | 111 | ||
96 | /** Set priority level low |
112 | /** Set priority level low |
97 | * |
113 | * |
98 | * Enable interrupts and return previous |
114 | * Enable interrupts and return previous |
99 | * value of EFLAGS. |
115 | * value of EFLAGS. |
100 | */ |
116 | */ |
101 | static inline pri_t cpu_priority_low(void) { |
117 | static inline pri_t cpu_priority_low(void) { |
102 | pri_t v; |
118 | pri_t v; |
103 | __asm__ volatile ( |
119 | __asm__ volatile ( |
104 | "pushf\n" |
120 | "pushf\n" |
105 | "popl %0\n" |
121 | "popl %0\n" |
106 | "sti\n" |
122 | "sti\n" |
107 | : "=r" (v) |
123 | : "=r" (v) |
108 | ); |
124 | ); |
109 | return v; |
125 | return v; |
110 | } |
126 | } |
111 | 127 | ||
112 | /** Set priority level high |
128 | /** Set priority level high |
113 | * |
129 | * |
114 | * Disable interrupts and return previous |
130 | * Disable interrupts and return previous |
115 | * value of EFLAGS. |
131 | * value of EFLAGS. |
116 | */ |
132 | */ |
117 | static inline pri_t cpu_priority_high(void) { |
133 | static inline pri_t cpu_priority_high(void) { |
118 | pri_t v; |
134 | pri_t v; |
119 | __asm__ volatile ( |
135 | __asm__ volatile ( |
120 | "pushf\n" |
136 | "pushf\n" |
121 | "popl %0\n" |
137 | "popl %0\n" |
122 | "cli\n" |
138 | "cli\n" |
123 | : "=r" (v) |
139 | : "=r" (v) |
124 | ); |
140 | ); |
125 | return v; |
141 | return v; |
126 | } |
142 | } |
127 | 143 | ||
128 | /** Restore priority level |
144 | /** Restore priority level |
129 | * |
145 | * |
130 | * Restore EFLAGS. |
146 | * Restore EFLAGS. |
131 | */ |
147 | */ |
132 | static inline void cpu_priority_restore(pri_t pri) { |
148 | static inline void cpu_priority_restore(pri_t pri) { |
133 | __asm__ volatile ( |
149 | __asm__ volatile ( |
134 | "pushl %0\n" |
150 | "pushl %0\n" |
135 | "popf\n" |
151 | "popf\n" |
136 | : : "r" (pri) |
152 | : : "r" (pri) |
137 | ); |
153 | ); |
138 | } |
154 | } |
139 | 155 | ||
140 | /** Return raw priority level |
156 | /** Return raw priority level |
141 | * |
157 | * |
142 | * Return EFLAFS. |
158 | * Return EFLAFS. |
143 | */ |
159 | */ |
144 | static inline pri_t cpu_priority_read(void) { |
160 | static inline pri_t cpu_priority_read(void) { |
145 | pri_t v; |
161 | pri_t v; |
146 | __asm__ volatile ( |
162 | __asm__ volatile ( |
147 | "pushf\n" |
163 | "pushf\n" |
148 | "popl %0\n" |
164 | "popl %0\n" |
149 | : "=r" (v) |
165 | : "=r" (v) |
150 | ); |
166 | ); |
151 | return v; |
167 | return v; |
152 | } |
168 | } |
153 | 169 | ||
154 | /** Return base address of current stack |
170 | /** Return base address of current stack |
155 | * |
171 | * |
156 | * Return the base address of the current stack. |
172 | * Return the base address of the current stack. |
157 | * The stack is assumed to be STACK_SIZE bytes long. |
173 | * The stack is assumed to be STACK_SIZE bytes long. |
158 | * The stack must start on page boundary. |
174 | * The stack must start on page boundary. |
159 | */ |
175 | */ |
160 | static inline __address get_stack_base(void) |
176 | static inline __address get_stack_base(void) |
161 | { |
177 | { |
162 | __address v; |
178 | __address v; |
163 | 179 | ||
164 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
180 | __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
165 | 181 | ||
166 | return v; |
182 | return v; |
167 | } |
183 | } |
168 | 184 | ||
169 | static inline __u64 rdtsc(void) |
185 | static inline __u64 rdtsc(void) |
170 | { |
186 | { |
171 | __u64 v; |
187 | __u64 v; |
172 | 188 | ||
173 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
189 | __asm__ volatile("rdtsc\n" : "=A" (v)); |
174 | 190 | ||
175 | return v; |
191 | return v; |
176 | } |
192 | } |
177 | 193 | ||
178 | 194 | ||
179 | #endif |
195 | #endif |
180 | 196 |