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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | * @brief Page fault related functions. |
33 | * @brief Page fault related functions. |
34 | */ |
34 | */ |
35 | #include <panic.h> |
35 | #include <panic.h> |
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug/print.h> |
- | |
38 | #include <arch/mm/page_fault.h> |
37 | #include <arch/mm/page_fault.h> |
39 | #include <mm/as.h> |
38 | #include <mm/as.h> |
40 | #include <genarch/mm/page_pt.h> |
39 | #include <genarch/mm/page_pt.h> |
41 | #include <arch.h> |
40 | #include <arch.h> |
42 | #include <interrupt.h> |
41 | #include <interrupt.h> |
43 | #include <print.h> |
42 | #include <print.h> |
44 | 43 | ||
45 | /** Returns value stored in fault status register. |
44 | /** Returns value stored in fault status register. |
46 | * |
45 | * |
47 | * @return Value stored in CP15 fault status register (FSR). |
46 | * @return Value stored in CP15 fault status register (FSR). |
48 | */ |
47 | */ |
49 | static inline fault_status_t read_fault_status_register(void) |
48 | static inline fault_status_t read_fault_status_register(void) |
50 | { |
49 | { |
51 | fault_status_union_t fsu; |
50 | fault_status_union_t fsu; |
52 | 51 | ||
53 | /* fault status is stored in CP15 register 5 */ |
52 | /* fault status is stored in CP15 register 5 */ |
54 | asm volatile ( |
53 | asm volatile ( |
55 | "mrc p15, 0, %[dummy], c5, c0, 0" |
54 | "mrc p15, 0, %[dummy], c5, c0, 0" |
56 | : [dummy] "=r" (fsu.dummy) |
55 | : [dummy] "=r" (fsu.dummy) |
57 | ); |
56 | ); |
58 | 57 | ||
59 | return fsu.fs; |
58 | return fsu.fs; |
60 | } |
59 | } |
61 | 60 | ||
62 | /** Returns FAR (fault address register) content. |
61 | /** Returns FAR (fault address register) content. |
63 | * |
62 | * |
64 | * @return FAR (fault address register) content (address that caused a page |
63 | * @return FAR (fault address register) content (address that caused a page |
65 | * fault) |
64 | * fault) |
66 | */ |
65 | */ |
67 | static inline uintptr_t read_fault_address_register(void) |
66 | static inline uintptr_t read_fault_address_register(void) |
68 | { |
67 | { |
69 | uintptr_t ret; |
68 | uintptr_t ret; |
70 | 69 | ||
71 | /* fault adress is stored in CP15 register 6 */ |
70 | /* fault adress is stored in CP15 register 6 */ |
72 | asm volatile ( |
71 | asm volatile ( |
73 | "mrc p15, 0, %[ret], c6, c0, 0" |
72 | "mrc p15, 0, %[ret], c6, c0, 0" |
74 | : [ret] "=r" (ret) |
73 | : [ret] "=r" (ret) |
75 | ); |
74 | ); |
76 | 75 | ||
77 | return ret; |
76 | return ret; |
78 | } |
77 | } |
79 | 78 | ||
80 | /** Decides whether the instruction is load/store or not. |
79 | /** Decides whether the instruction is load/store or not. |
81 | * |
80 | * |
82 | * @param instr Instruction |
81 | * @param instr Instruction |
83 | * |
82 | * |
84 | * @return true when instruction is load/store, false otherwise |
83 | * @return true when instruction is load/store, false otherwise |
85 | * |
84 | * |
86 | */ |
85 | */ |
87 | static inline bool is_load_store_instruction(instruction_t instr) |
86 | static inline bool is_load_store_instruction(instruction_t instr) |
88 | { |
87 | { |
89 | /* load store immediate offset */ |
88 | /* load store immediate offset */ |
90 | if (instr.type == 0x2) |
89 | if (instr.type == 0x2) |
91 | return true; |
90 | return true; |
92 | 91 | ||
93 | /* load store register offset */ |
92 | /* load store register offset */ |
94 | if ((instr.type == 0x3) && (instr.bit4 == 0)) |
93 | if ((instr.type == 0x3) && (instr.bit4 == 0)) |
95 | return true; |
94 | return true; |
96 | 95 | ||
97 | /* load store multiple */ |
96 | /* load store multiple */ |
98 | if (instr.type == 0x4) |
97 | if (instr.type == 0x4) |
99 | return true; |
98 | return true; |
100 | 99 | ||
101 | /* oprocessor load/store */ |
100 | /* oprocessor load/store */ |
102 | if (instr.type == 0x6) |
101 | if (instr.type == 0x6) |
103 | return true; |
102 | return true; |
104 | 103 | ||
105 | return false; |
104 | return false; |
106 | } |
105 | } |
107 | 106 | ||
108 | /** Decides whether the instruction is swap or not. |
107 | /** Decides whether the instruction is swap or not. |
109 | * |
108 | * |
110 | * @param instr Instruction |
109 | * @param instr Instruction |
111 | * |
110 | * |
112 | * @return true when instruction is swap, false otherwise |
111 | * @return true when instruction is swap, false otherwise |
113 | */ |
112 | */ |
114 | static inline bool is_swap_instruction(instruction_t instr) |
113 | static inline bool is_swap_instruction(instruction_t instr) |
115 | { |
114 | { |
116 | /* swap, swapb instruction */ |
115 | /* swap, swapb instruction */ |
117 | if ((instr.type == 0x0) && |
116 | if ((instr.type == 0x0) && |
118 | ((instr.opcode == 0x8) || (instr.opcode == 0xa)) && |
117 | ((instr.opcode == 0x8) || (instr.opcode == 0xa)) && |
119 | (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1)) |
118 | (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1)) |
120 | return true; |
119 | return true; |
121 | 120 | ||
122 | return false; |
121 | return false; |
123 | } |
122 | } |
124 | 123 | ||
125 | /** Decides whether read or write into memory is requested. |
124 | /** Decides whether read or write into memory is requested. |
126 | * |
125 | * |
127 | * @param instr_addr Address of instruction which tries to access memory. |
126 | * @param instr_addr Address of instruction which tries to access memory. |
128 | * @param badvaddr Virtual address the instruction tries to access. |
127 | * @param badvaddr Virtual address the instruction tries to access. |
129 | * |
128 | * |
130 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
129 | * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is |
131 | * requested. |
130 | * requested. |
132 | */ |
131 | */ |
133 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
132 | static pf_access_t get_memory_access_type(uint32_t instr_addr, |
134 | uintptr_t badvaddr) |
133 | uintptr_t badvaddr) |
135 | { |
134 | { |
136 | instruction_union_t instr_union; |
135 | instruction_union_t instr_union; |
137 | instr_union.pc = instr_addr; |
136 | instr_union.pc = instr_addr; |
138 | 137 | ||
139 | instruction_t instr = *(instr_union.instr); |
138 | instruction_t instr = *(instr_union.instr); |
140 | 139 | ||
141 | /* undefined instructions */ |
140 | /* undefined instructions */ |
142 | if (instr.condition == 0xf) { |
141 | if (instr.condition == 0xf) { |
143 | panic("page_fault - instruction does not access memory " |
142 | panic("page_fault - instruction does not access memory " |
144 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
143 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
145 | return PF_ACCESS_EXEC; |
144 | return PF_ACCESS_EXEC; |
146 | } |
145 | } |
147 | 146 | ||
148 | /* load store instructions */ |
147 | /* load store instructions */ |
149 | if (is_load_store_instruction(instr)) { |
148 | if (is_load_store_instruction(instr)) { |
150 | if (instr.access == 1) { |
149 | if (instr.access == 1) { |
151 | return PF_ACCESS_READ; |
150 | return PF_ACCESS_READ; |
152 | } else { |
151 | } else { |
153 | return PF_ACCESS_WRITE; |
152 | return PF_ACCESS_WRITE; |
154 | } |
153 | } |
155 | } |
154 | } |
156 | 155 | ||
157 | /* swap, swpb instruction */ |
156 | /* swap, swpb instruction */ |
158 | if (is_swap_instruction(instr)) { |
157 | if (is_swap_instruction(instr)) { |
159 | return PF_ACCESS_WRITE; |
158 | return PF_ACCESS_WRITE; |
160 | } |
159 | } |
161 | 160 | ||
162 | panic("page_fault - instruction doesn't access memory " |
161 | panic("page_fault - instruction doesn't access memory " |
163 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
162 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
164 | 163 | ||
165 | return PF_ACCESS_EXEC; |
164 | return PF_ACCESS_EXEC; |
166 | } |
165 | } |
167 | 166 | ||
168 | /** Handles "data abort" exception (load or store at invalid address). |
167 | /** Handles "data abort" exception (load or store at invalid address). |
169 | * |
168 | * |
170 | * @param exc_no Exception number. |
169 | * @param exc_no Exception number. |
171 | * @param istate CPU state when exception occured. |
170 | * @param istate CPU state when exception occured. |
172 | */ |
171 | */ |
173 | void data_abort(int exc_no, istate_t *istate) |
172 | void data_abort(int exc_no, istate_t *istate) |
174 | { |
173 | { |
175 | fault_status_t fsr __attribute__ ((unused)) = |
174 | fault_status_t fsr __attribute__ ((unused)) = |
176 | read_fault_status_register(); |
175 | read_fault_status_register(); |
177 | uintptr_t badvaddr = read_fault_address_register(); |
176 | uintptr_t badvaddr = read_fault_address_register(); |
178 | 177 | ||
179 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
178 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
180 | 179 | ||
181 | int ret = as_page_fault(badvaddr, access, istate); |
180 | int ret = as_page_fault(badvaddr, access, istate); |
182 | 181 | ||
183 | if (ret == AS_PF_FAULT) { |
182 | if (ret == AS_PF_FAULT) { |
184 | print_istate(istate); |
183 | print_istate(istate); |
185 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
184 | printf("page fault - pc: %x, va: %x, status: %x(%x), " |
186 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
185 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
187 | access); |
186 | access); |
188 | 187 | ||
189 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
188 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
190 | panic("Page fault."); |
189 | panic("Page fault."); |
191 | } |
190 | } |
192 | } |
191 | } |
193 | 192 | ||
194 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
193 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
195 | * |
194 | * |
196 | * @param exc_no Exception number. |
195 | * @param exc_no Exception number. |
197 | * @param istate CPU state when exception occured. |
196 | * @param istate CPU state when exception occured. |
198 | */ |
197 | */ |
199 | void prefetch_abort(int exc_no, istate_t *istate) |
198 | void prefetch_abort(int exc_no, istate_t *istate) |
200 | { |
199 | { |
201 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
200 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
202 | 201 | ||
203 | if (ret == AS_PF_FAULT) { |
202 | if (ret == AS_PF_FAULT) { |
204 | dprintf("prefetch_abort\n"); |
203 | printf("prefetch_abort\n"); |
205 | print_istate(istate); |
204 | print_istate(istate); |
206 | panic("page fault - prefetch_abort at address: %x.", |
205 | panic("page fault - prefetch_abort at address: %x.", |
207 | istate->pc); |
206 | istate->pc); |
208 | } |
207 | } |
209 | } |
208 | } |
210 | 209 | ||
211 | /** @} |
210 | /** @} |
212 | */ |
211 | */ |
213 | 212 |