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Rev 3022 Rev 4055
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#
 1 
#
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# Copyright (c) 2006 Martin Decky
 2 
# Copyright (c) 2006 Martin Decky
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# All rights reserved.
 3 
# All rights reserved.
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#
 4 
#
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# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
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# are met:
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# are met:
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#
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#
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# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
10 
#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
11 
# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
12 
#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
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#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
14 
# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
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#
 16 
#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
 27 
#
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 28 
 
29 
#include "asm.h"
 29 
#include "asm.h"
30 
#include "regname.h"
 30 
#include "regname.h"
- 
 
 31 
 
- 
 
 32 
.macro SMC_COHERENCY addr
- 
 
 33 
	dcbst 0, \addr
- 
 
 34 
	sync
- 
 
 35 
	icbi 0, \addr
- 
 
 36 
	sync
- 
 
 37 
	isync
- 
 
 38 
.endm
- 
 
 39 
 
- 
 
 40 
.macro FLUSH_DCACHE addr
- 
 
 41 
	dcbst 0, \addr
- 
 
 42 
	sync
- 
 
 43 
	isync
- 
 
 44 
.endm
- 
 
 45 
 
- 
 
 46 
.macro TLB_FLUSH reg
31 
#include "debug.inc"
 47 
	tlbie \reg
- 
 
 48 
	addi \reg, \reg, 0x1000
- 
 
 49 
.endm
32 
 
 50 
 
33 
.text
 51 
.text
34 
 
 52 
 
35 
.global halt
 53 
.global halt
36 
.global memcpy
 54 
.global memcpy
37 
.global jump_to_kernel
 55 
.global jump_to_kernel
38 
 
 56 
 
39 
halt:
 57 
halt:
40 
	b halt
 58 
	b halt
41 
 
 59 
 
42 
memcpy:
 60 
memcpy:
43 
	srwi. r7, r5, 3
 61 
	srwi. r7, r5, 3
44 
	addi r6, r3, -4
 62 
	addi r6, r3, -4
45 
	addi r4, r4, -4
 63 
	addi r4, r4, -4
46 
	beq	2f
 64 
	beq	2f
47
65
48 
	andi. r0, r6, 3
 66 
	andi. r0, r6, 3
49 
	mtctr r7
 67 
	mtctr r7
50 
	bne 5f
 68 
	bne 5f
51
69
52 
	1:
 70 
	1:
53
71
54 
	lwz r7, 4(r4)
 72 
	lwz r7, 4(r4)
55 
	lwzu r8, 8(r4)
 73 
	lwzu r8, 8(r4)
56 
	stw r7, 4(r6)
 74 
	stw r7, 4(r6)
57 
	stwu r8, 8(r6)
 75 
	stwu r8, 8(r6)
58 
	bdnz 1b
 76 
	bdnz 1b
59
77
60 
	andi. r5, r5, 7
 78 
	andi. r5, r5, 7
61
79
62 
	2:
 80 
	2:
63
81
64 
	cmplwi 0, r5, 4
 82 
	cmplwi 0, r5, 4
65 
	blt 3f
 83 
	blt 3f
66
84
67 
	lwzu r0, 4(r4)
 85 
	lwzu r0, 4(r4)
68 
	addi r5, r5, -4
 86 
	addi r5, r5, -4
69 
	stwu r0, 4(r6)
 87 
	stwu r0, 4(r6)
70
88
71 
	3:
 89 
	3:
72
90
73 
	cmpwi 0, r5, 0
 91 
	cmpwi 0, r5, 0
74 
	beqlr
 92 
	beqlr
75 
	mtctr r5
 93 
	mtctr r5
76 
	addi r4, r4, 3
 94 
	addi r4, r4, 3
77 
	addi r6, r6, 3
 95 
	addi r6, r6, 3
78
96
79 
	4:
 97 
	4:
80
98
81 
	lbzu r0, 1(r4)
 99 
	lbzu r0, 1(r4)
82 
	stbu r0, 1(r6)
 100 
	stbu r0, 1(r6)
83 
	bdnz 4b
 101 
	bdnz 4b
84 
	blr
 102 
	blr
85
103
86 
	5:
 104 
	5:
87
105
88 
	subfic r0, r0, 4
 106 
	subfic r0, r0, 4
89 
	mtctr r0
 107 
	mtctr r0
90
108
91 
	6:
 109 
	6:
92
110
93 
	lbz r7, 4(r4)
 111 
	lbz r7, 4(r4)
94 
	addi r4, r4, 1
 112 
	addi r4, r4, 1
95 
	stb r7, 4(r6)
 113 
	stb r7, 4(r6)
96 
	addi r6, r6, 1
 114 
	addi r6, r6, 1
97 
	bdnz 6b
 115 
	bdnz 6b
98 
	subf r5, r0, r5
 116 
	subf r5, r0, r5
99 
	rlwinm. r7, r5, 32-3, 3, 31
 117 
	rlwinm. r7, r5, 32-3, 3, 31
100 
	beq 2b
 118 
	beq 2b
101 
	mtctr r7
 119 
	mtctr r7
102 
	b 1b
 120 
	b 1b
103 
 
 121 
 
104 
 
 122 
 
105 
jump_to_kernel:
 123 
jump_to_kernel:
106
124
107 
	# r3 = bootinfo (pa)
 125 
	# r3 = bootinfo (pa)
108 
	# r4 = bootinfo_size
 126 
	# r4 = bootinfo_size
109 
	# r5 = trans (pa)
 127 
	# r5 = trans (pa)
110 
	# r6 = bytes to copy
 128 
	# r6 = bytes to copy
111 
	# r7 = real_mode (pa)
 129 
	# r7 = real_mode (pa)
112 
	# r8 = framebuffer (pa)
 130 
	# r8 = framebuffer (pa)
113 
	# r9 = scanline
 131 
	# r9 = scanline
114
132
115 
	# disable interrupts
 133 
	# disable interrupts
116
134
117 
	mfmsr r31
 135 
	mfmsr r31
118 
	rlwinm r31, r31, 0, 17, 15
 136 
	rlwinm r31, r31, 0, 17, 15
119 
	mtmsr r31
 137 
	mtmsr r31
120
138
121 
	# set real_mode meeting point address
 139 
	# set real_mode meeting point address
122
140
123 
	mtspr srr0, r7
 141 
	mtspr srr0, r7
124
142
125 
	# jumps to real_mode
 143 
	# jumps to real_mode
126
144
127 
	mfmsr r31
 145 
	mfmsr r31
128 
	lis r30, ~0@h
 146 
	lis r30, ~0@h
129 
	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
 147 
	ori r30, r30, ~(msr_ir | msr_dr | msr_ee)@l
130 
	and r31, r31, r30
 148 
	and r31, r31, r30
131 
	mtspr srr1, r31
 149 
	mtspr srr1, r31
132
150
133 
	sync
 151 
	sync
134 
	isync
 152 
	isync
135 
	rfi
 153 
	rfi
136 
 
 154 
 
137 
.section REALMODE, "ax"
 155 
.section REALMODE, "ax"
138 
.align PAGE_WIDTH
 156 
.align PAGE_WIDTH
139 
.global real_mode
 157 
.global real_mode
140 
 
 158 
 
141 
real_mode:
 159 
real_mode:
142
160
143 
	DEBUG_INIT
 - 
 
144 
	DEBUG_real_mode
 - 
 
145
- 
 
146 
	# copy kernel to proper location
 161 
	# copy kernel to proper location
147 
	#
 162 
	#
148 
	# r5 = trans (pa)
 163 
	# r5 = trans (pa)
149 
	# r6 = bytes to copy
 164 
	# r6 = bytes to copy
150 
	# r8 = framebuffer (pa)
 165 
	# r8 = framebuffer (pa)
151 
	# r9 = scanline
 166 
	# r9 = scanline
152
167
153 
	li r31, PAGE_SIZE >> 2
 168 
	li r31, PAGE_SIZE >> 2
154 
	li r30, 0
 169 
	li r30, 0
155
170
156 
	page_copy:
 171 
	page_copy:
157
172
158 
		cmpwi r6, 0
 173 
		cmpwi r6, 0
159 
		beq copy_end
 174 
		beq copy_end
160
175
161 
		# copy page
 176 
		# copy page
162
177
163 
		mtctr r31
 178 
		mtctr r31
164 
		lwz r29, 0(r5)
 179 
		lwz r29, 0(r5)
165
180
166 
		DEBUG_INIT
 - 
 
167 
		DEBUG_copy_loop
 - 
 
168
- 
 
169 
		copy_loop:
 181 
		copy_loop:
170
182
171 
			lwz r28, 0(r29)
 183 
			lwz r28, 0(r29)
172 
			stw r28, 0(r30)
 184 
			stw r28, 0(r30)
173
185
- 
 
 186 
			SMC_COHERENCY r30
- 
 
 187
174 
			addi r29, r29, 4
 188 
			addi r29, r29, 4
175 
			addi r30, r30, 4
 189 
			addi r30, r30, 4
176 
			subi r6, r6, 4
 190 
			subi r6, r6, 4
177
191
178 
			cmpwi r6, 0
 192 
			cmpwi r6, 0
179 
			beq copy_end
 193 
			beq copy_end
180
194
181 
			bdnz copy_loop
 195 
			bdnz copy_loop
182
196
183 
			DEBUG_end_copy_loop
 - 
 
184
- 
 
185 
		addi r5, r5, 4
 197 
		addi r5, r5, 4
186 
		b page_copy
 198 
		b page_copy
187
199
188 
	copy_end:
 200 
	copy_end:
189
201
190 
	DEBUG_segments
 - 
 
191
- 
 
192 
	# initially fill segment registers
 202 
	# initially fill segment registers
193
203
194 
	li r31, 0
 204 
	li r31, 0
195
205
196 
	li r29, 8
 206 
	li r29, 8
197 
	mtctr r29
 207 
	mtctr r29
198 
	li r30, 0                     # ASID 0 (VSIDs 0 .. 7)
 208 
	li r30, 0                     # ASID 0 (VSIDs 0 .. 7)
199 
 
 209
200 
	seg_fill_uspace:
 210 
	seg_fill_uspace:
201
211
202 
		mtsrin r30, r31
 212 
		mtsrin r30, r31
203 
		addi r30, r30, 1
 213 
		addi r30, r30, 1
204 
		addis r31, r31, 0x1000    # move to next SR
 214 
		addis r31, r31, 0x1000    # move to next SR
205
215
206 
		bdnz seg_fill_uspace
 216 
		bdnz seg_fill_uspace
207
217
208 
	li r29, 8
 218 
	li r29, 8
209 
	mtctr r29
 219 
	mtctr r29
210 
	lis r30, 0x4000               # priviledged access only
 220 
	lis r30, 0x4000               # priviledged access only
211 
	ori r30, r30, 8               # ASID 0 (VSIDs 8 .. 15)
 221 
	ori r30, r30, 8               # ASID 0 (VSIDs 8 .. 15)
212
222
213 
	seg_fill_kernel:
 223 
	seg_fill_kernel:
214
224
215 
		mtsrin r30, r31
 225 
		mtsrin r30, r31
216 
		addi r30, r30, 1
 226 
		addi r30, r30, 1
217 
		addis r31, r31, 0x1000    # move to next SR
 227 
		addis r31, r31, 0x1000    # move to next SR
218
228
219 
		bdnz seg_fill_kernel
 229 
		bdnz seg_fill_kernel
220
230
221 
	# invalidate block address translation registers
 231 
	# invalidate block address translation registers
222
232
223 
	DEBUG_bat
 - 
 
224
- 
 
225 
	li r30, 0
 233 
	li r30, 0
226
234
227 
	mtspr ibat0u, r30
 235 
	mtspr ibat0u, r30
228 
	mtspr ibat0l, r30
 236 
	mtspr ibat0l, r30
229
237
230 
	mtspr ibat1u, r30
 238 
	mtspr ibat1u, r30
231 
	mtspr ibat1l, r30
 239 
	mtspr ibat1l, r30
232
240
233 
	mtspr ibat2u, r30
 241 
	mtspr ibat2u, r30
234 
	mtspr ibat2l, r30
 242 
	mtspr ibat2l, r30
235
243
236 
	mtspr ibat3u, r30
 244 
	mtspr ibat3u, r30
237 
	mtspr ibat3l, r30
 245 
	mtspr ibat3l, r30
238
246
239 
	mtspr dbat0u, r30
 247 
	mtspr dbat0u, r30
240 
	mtspr dbat0l, r30
 248 
	mtspr dbat0l, r30
241
249
242 
	mtspr dbat1u, r30
 250 
	mtspr dbat1u, r30
243 
	mtspr dbat1l, r30
 251 
	mtspr dbat1l, r30
244
252
245 
	mtspr dbat2u, r30
 253 
	mtspr dbat2u, r30
246 
	mtspr dbat2l, r30
 254 
	mtspr dbat2l, r30
247
255
248 
	mtspr dbat3u, r30
 256 
	mtspr dbat3u, r30
249 
	mtspr dbat3l, r30
 257 
	mtspr dbat3l, r30
250
258
251 
	# create empty Page Hash Table
 259 
	# create empty Page Hash Table
252 
	# on top of memory, size 64 KB
 260 
	# on top of memory, size 64 KB
253
261
254 
	DEBUG_pht
 - 
 
255
- 
 
256 
	lwz r31, 0(r3)                # r31 = memory size
 262 
	lwz r31, 0(r3)                # r31 = memory size
257
263
258 
	lis r30, 65536@h
 264 
	lis r30, 65536@h
259 
	ori r30, r30, 65536@l         # r30 = 65536
 265 
	ori r30, r30, 65536@l         # r30 = 65536
260
266
261 
	subi r29, r30, 1              # r29 = 65535
 267 
	subi r29, r30, 1              # r29 = 65535
262
268
263 
	sub r31, r31, r30
 269 
	sub r31, r31, r30
264 
	andc r31, r31, r29            # pht = ALIGN_DOWN(memory_size - 65536, 65536)
 270 
	andc r31, r31, r29            # pht = ALIGN_DOWN(memory_size - 65536, 65536)
265
271
266 
	mtsdr1 r31
 272 
	mtsdr1 r31
267
273
268 
	li r29, 2
 274 
	li r29, 2
269 
	srw r30, r30, r29             # r30 = 16384
 275 
	srw r30, r30, r29             # r30 = 16384
270 
	li r29, 0
 276 
	li r29, 0
271
277
272 
	pht_clear:
 278 
	pht_clear:
273
279
274 
		# write zeroes
 280 
		# write zeroes
275
281
276 
		stw r29, 0(r31)
 282 
		stw r29, 0(r31)
- 
 
 283 
		FLUSH_DCACHE r31
277
284
278 
		addi r31, r31, 4
 285 
		addi r31, r31, 4
279 
		subi r30, r30, 4
 286 
		subi r30, r30, 4
280
287
281 
		cmpwi r30, 0
 288 
		cmpwi r30, 0
282 
		beq clear_end
 289 
		beq clear_end
283
290
284 
		bdnz pht_clear
 291 
		bdnz pht_clear
285 
 
 - 
 
286 
		DEBUG_end_pht_clear
 - 
 
287
292
288 
	clear_end:
 293 
	clear_end:
289
294
290 
#ifdef CONFIG_BAT
 295 
#ifdef CONFIG_BAT
291
296
292 
	# create BAT identity mapping
 297 
	# create BAT identity mapping
293
298
294 
	DEBUG_mapping
 - 
 
295
- 
 
296 
	lwz r31, 0(r3)                # r31 = memory size
 299 
	lwz r31, 0(r3)                # r31 = memory size
297
300
298 
	lis r29, 0x0002
 301 
	lis r29, 0x0002
299 
	cmpw r31, r29
 302 
	cmpw r31, r29
300 
	blt no_bat                    # less than 128 KB -> no BAT
 303 
	blt no_bat                    # less than 128 KB -> no BAT
301
304
302 
	li r29, 18
 305 
	li r29, 18
303 
	srw r31, r31, r29             # r31 = total >> 18
 306 
	srw r31, r31, r29             # r31 = total >> 18
304
307
305 
	# create Block Length mask by replicating
 308 
	# create Block Length mask by replicating
306 
	# the leading logical one 14 times
 309 
	# the leading logical one 14 times
307
310
308 
	li r29, 14
 311 
	li r29, 14
309 
	mtctr r31
 312 
	mtctr r31
310 
	li r29, 1
 313 
	li r29, 1
311
314
312 
	bat_mask:
 315 
	bat_mask:
313 
		srw r30, r31, r29         # r30 = mask >> 1
 316 
		srw r30, r31, r29         # r30 = mask >> 1
314 
		or r31, r31, r30          # mask = mask | r30
 317 
		or r31, r31, r30          # mask = mask | r30
315
318
316 
		bdnz bat_mask
 319 
		bdnz bat_mask
317
320
318 
	DEBUG_bat_mask
 - 
 
319
- 
 
320 
	andi. r31, r31, 0x07ff        # mask = mask & 0x07ff (BAT can map up to 256 MB)
 321 
	andi. r31, r31, 0x07ff        # mask = mask & 0x07ff (BAT can map up to 256 MB)
321
322
322 
	li r29, 2
 323 
	li r29, 2
323 
	slw r31, r31, r29             # mask = mask << 2
 324 
	slw r31, r31, r29             # mask = mask << 2
324 
	ori r31, r31, 0x0002          # mask = mask | 0x0002 (priviledged access only)
 325 
	ori r31, r31, 0x0002          # mask = mask | 0x0002 (priviledged access only)
325
326
326 
	lis r29, 0x8000
 327 
	lis r29, 0x8000
327 
	or r29, r29, r31
 328 
	or r29, r29, r31
328
329
329 
	lis r30, 0x0000
 330 
	lis r30, 0x0000
330 
	ori r30, r30, 0x0002
 331 
	ori r30, r30, 0x0002
331
332
332 
	mtspr ibat0u, r29
 333 
	mtspr ibat0u, r29
333 
	mtspr ibat0l, r30
 334 
	mtspr ibat0l, r30
334
335
335 
	mtspr dbat0u, r29
 336 
	mtspr dbat0u, r29
336 
	mtspr dbat0l, r30
 337 
	mtspr dbat0l, r30
337
338
338 
	no_bat:
 339 
	no_bat:
339 
 
 340
340 
#endif
 341 
#endif
341
342
342 
	DEBUG_tlb
 343 
	# flush TLB
343
344
344 
	tlbia
 345 
	li r31, 0
345 
	tlbsync
 346 
	sync
346
347
- 
 
 348 
	TLB_FLUSH r31
- 
 
 349 
	TLB_FLUSH r31
- 
 
 350 
	TLB_FLUSH r31
- 
 
 351 
	TLB_FLUSH r31
- 
 
 352 
	TLB_FLUSH r31
- 
 
 353 
	TLB_FLUSH r31
- 
 
 354 
	TLB_FLUSH r31
- 
 
 355 
	TLB_FLUSH r31
- 
 
 356
- 
 
 357 
	TLB_FLUSH r31
- 
 
 358 
	TLB_FLUSH r31
- 
 
 359 
	TLB_FLUSH r31
- 
 
 360 
	TLB_FLUSH r31
- 
 
 361 
	TLB_FLUSH r31
- 
 
 362 
	TLB_FLUSH r31
- 
 
 363 
	TLB_FLUSH r31
- 
 
 364 
	TLB_FLUSH r31
- 
 
 365
- 
 
 366 
	TLB_FLUSH r31
- 
 
 367 
	TLB_FLUSH r31
- 
 
 368 
	TLB_FLUSH r31
- 
 
 369 
	TLB_FLUSH r31
- 
 
 370 
	TLB_FLUSH r31
- 
 
 371 
	TLB_FLUSH r31
- 
 
 372 
	TLB_FLUSH r31
- 
 
 373 
	TLB_FLUSH r31
- 
 
 374
- 
 
 375 
	TLB_FLUSH r31
- 
 
 376 
	TLB_FLUSH r31
- 
 
 377 
	TLB_FLUSH r31
- 
 
 378 
	TLB_FLUSH r31
- 
 
 379 
	TLB_FLUSH r31
- 
 
 380 
	TLB_FLUSH r31
- 
 
 381 
	TLB_FLUSH r31
- 
 
 382 
	TLB_FLUSH r31
- 
 
 383
- 
 
 384 
	TLB_FLUSH r31
- 
 
 385 
	TLB_FLUSH r31
- 
 
 386 
	TLB_FLUSH r31
- 
 
 387 
	TLB_FLUSH r31
- 
 
 388 
	TLB_FLUSH r31
- 
 
 389 
	TLB_FLUSH r31
- 
 
 390 
	TLB_FLUSH r31
- 
 
 391 
	TLB_FLUSH r31
- 
 
 392
- 
 
 393 
	TLB_FLUSH r31
- 
 
 394 
	TLB_FLUSH r31
- 
 
 395 
	TLB_FLUSH r31
- 
 
 396 
	TLB_FLUSH r31
- 
 
 397 
	TLB_FLUSH r31
- 
 
 398 
	TLB_FLUSH r31
- 
 
 399 
	TLB_FLUSH r31
- 
 
 400 
	TLB_FLUSH r31
- 
 
 401
- 
 
 402 
	TLB_FLUSH r31
- 
 
 403 
	TLB_FLUSH r31
- 
 
 404 
	TLB_FLUSH r31
- 
 
 405 
	TLB_FLUSH r31
- 
 
 406 
	TLB_FLUSH r31
- 
 
 407 
	TLB_FLUSH r31
- 
 
 408 
	TLB_FLUSH r31
- 
 
 409 
	TLB_FLUSH r31
- 
 
 410
- 
 
 411 
	TLB_FLUSH r31
- 
 
 412 
	TLB_FLUSH r31
- 
 
 413 
	TLB_FLUSH r31
- 
 
 414 
	TLB_FLUSH r31
- 
 
 415 
	TLB_FLUSH r31
- 
 
 416 
	TLB_FLUSH r31
- 
 
 417 
	TLB_FLUSH r31
347 
	DEBUG_prepare
 418 
	TLB_FLUSH r31
- 
 
 419
- 
 
 420 
	eieio
- 
 
 421 
	tlbsync
- 
 
 422 
	sync
348
423
349 
	# start the kernel
 424 
	# start the kernel
350 
	#
 425 
	#
351 
	# pc = KERNEL_START_ADDR
 426 
	# pc = KERNEL_START_ADDR
352 
	# r3 = bootinfo (pa)
 427 
	# r3 = bootinfo (pa)
353 
	# sprg0 = KA2PA(KERNEL_START_ADDR)
 428 
	# sprg0 = KA2PA(KERNEL_START_ADDR)
354 
	# sprg3 = physical memory size
 429 
	# sprg3 = physical memory size
355 
	# sp = 0 (pa)
 430 
	# sp = 0 (pa)
356
431
357 
	lis r31, KERNEL_START_ADDR@ha
 432 
	lis r31, KERNEL_START_ADDR@ha
358 
	addi r31, r31, KERNEL_START_ADDR@l
 433 
	addi r31, r31, KERNEL_START_ADDR@l
359
434
360 
	mtspr srr0, r31
 435 
	mtspr srr0, r31
361
436
362 
	subis r31, r31, 0x8000
 437 
	subis r31, r31, 0x8000
363 
	mtsprg0 r31
 438 
	mtsprg0 r31
364
439
365 
	lwz r31, 0(r3)
 440 
	lwz r31, 0(r3)
366 
	mtsprg3 r31
 441 
	mtsprg3 r31
367
442
368 
	li sp, 0
 443 
	li sp, 0
369
444
370 
	mfmsr r31
 445 
	mfmsr r31
371 
	ori r31, r31, (msr_ir | msr_dr)@l
 446 
	ori r31, r31, (msr_ir | msr_dr)@l
372 
	mtspr srr1, r31
 447 
	mtspr srr1, r31
373
448
374 
	sync
 449 
	sync
375 
	isync
 450 
	isync
376
- 
 
377 
	DEBUG_rfi
 - 
 
378 
	rfi
 451 
	rfi
379 
 
 452 
 
380 
.align PAGE_WIDTH
 453 
.align PAGE_WIDTH
381 
.global trans
 454 
.global trans
382 
trans:
 455 
trans:
383 
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
 456 
	.space (TRANS_SIZE * TRANS_ITEM_SIZE)
384 
 
 457