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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | #include <panic.h> |
34 | #include <panic.h> |
35 | #include <arch/exception.h> |
35 | #include <arch/exception.h> |
36 | #include <arch/debug/print.h> |
36 | #include <arch/debug/print.h> |
37 | #include <arch/mm/page_fault.h> |
37 | #include <arch/mm/page_fault.h> |
38 | #include <mm/as.h> |
38 | #include <mm/as.h> |
39 | #include <genarch/mm/page_pt.h> |
39 | #include <genarch/mm/page_pt.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | 42 | ||
43 | 43 | ||
44 | /** Returns value stored in fault status register. |
44 | /** Returns value stored in fault status register. |
- | 45 | * FSR contain reason of page fault |
|
45 | * |
46 | * |
46 | * \return Value stored in CP15 fault status register (FSR). |
47 | * \return Value stored in CP15 fault status register (FSR). |
47 | */ |
48 | */ |
48 | static inline fault_status_t read_fault_status_register(void) |
49 | static inline fault_status_t read_fault_status_register(void) |
49 | { |
50 | { |
50 | fault_status_union_t fsu; |
51 | fault_status_union_t fsu; |
51 | 52 | ||
52 | // fault adress is stored in CP15 register 5 |
53 | // fault adress is stored in CP15 register 5 |
53 | asm volatile ( |
54 | asm volatile ( |
54 | "mrc p15, 0, %0, c5, c0, 0" |
55 | "mrc p15, 0, %0, c5, c0, 0" |
55 | : "=r"(fsu.dummy) |
56 | : "=r"(fsu.dummy) |
56 | ); |
57 | ); |
57 | return fsu.fs; |
58 | return fsu.fs; |
58 | } |
59 | } |
59 | 60 | ||
60 | 61 | ||
61 | /** Returns FAR (fault address register) content. |
62 | /** Returns FAR (fault address register) content. |
62 | * |
63 | * |
63 | * \return FAR (fault address register) content (address that caused a page fault) |
64 | * \return FAR (fault address register) content (address that caused a page fault) |
64 | */ |
65 | */ |
65 | static inline uintptr_t read_fault_address_register(void) |
66 | static inline uintptr_t read_fault_address_register(void) |
66 | { |
67 | { |
67 | uintptr_t ret; |
68 | uintptr_t ret; |
68 | 69 | ||
69 | // fault adress is stored in CP15 register 6 |
70 | // fault adress is stored in CP15 register 6 |
70 | asm volatile ( |
71 | asm volatile ( |
71 | "mrc p15, 0, %0, c6, c0, 0" |
72 | "mrc p15, 0, %0, c6, c0, 0" |
72 | : "=r"(ret) |
73 | : "=r"(ret) |
73 | ); |
74 | ); |
74 | return ret; |
75 | return ret; |
75 | } |
76 | } |
76 | 77 | ||
77 | 78 | ||
78 | /** Decides whether the instructions is load/store or not. |
79 | /** Decides whether the instructions is load/store or not. |
79 | * |
80 | * |
80 | * \param instr Instruction |
81 | * \param instr Instruction |
81 | * |
82 | * |
82 | * \return true when instruction is load/store, false otherwise |
83 | * \return true when instruction is load/store, false otherwise |
83 | */ |
84 | */ |
84 | static inline bool is_load_store_instruction(instruction_t instr) |
85 | static inline bool is_load_store_instruction(instruction_t instr) |
85 | { |
86 | { |
86 | // load store immediate offset |
87 | // load store immediate offset |
87 | if (instr.type == 0x2) { |
88 | if (instr.type == 0x2) { |
88 | return true; |
89 | return true; |
89 | } |
90 | } |
90 | 91 | ||
91 | // load store register offset |
92 | // load store register offset |
92 | if (instr.type == 0x3 && instr.bit4 == 0) { |
93 | if (instr.type == 0x3 && instr.bit4 == 0) { |
93 | return true; |
94 | return true; |
94 | } |
95 | } |
95 | 96 | ||
96 | // load store multiple |
97 | // load store multiple |
97 | if (instr.type == 0x4) { |
98 | if (instr.type == 0x4) { |
98 | return true; |
99 | return true; |
99 | } |
100 | } |
100 | 101 | ||
101 | // coprocessor load/store |
102 | // coprocessor load/store |
102 | if (instr.type == 0x6) { |
103 | if (instr.type == 0x6) { |
103 | return true; |
104 | return true; |
104 | } |
105 | } |
105 | 106 | ||
106 | return false; |
107 | return false; |
107 | } |
108 | } |
108 | 109 | ||
109 | 110 | ||
110 | /** Decides whether the instructions is swap or not. |
111 | /** Decides whether the instructions is swap or not. |
111 | * |
112 | * |
112 | * \param instr Instruction |
113 | * \param instr Instruction |
113 | * |
114 | * |
114 | * \return true when instruction is swap, false otherwise |
115 | * \return true when instruction is swap, false otherwise |
115 | */ |
116 | */ |
116 | static inline bool is_swap_instruction(instruction_t instr) |
117 | static inline bool is_swap_instruction(instruction_t instr) |
117 | { |
118 | { |
118 | // swap, swapb instruction |
119 | // swap, swapb instruction |
119 | if (instr.type == 0x0 && |
120 | if (instr.type == 0x0 && |
120 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
121 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
121 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
122 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
122 | return true; |
123 | return true; |
123 | } |
124 | } |
124 | 125 | ||
125 | return false; |
126 | return false; |
126 | } |
127 | } |
127 | 128 | ||
128 | 129 | ||
129 | /** Decides whether read or write into memory is requested. |
130 | /** Decides whether read or write into memory is requested. |
130 | * |
131 | * |
131 | * \param instr_addr Address of instruction which tries to access memory |
132 | * \param instr_addr Address of instruction which tries to access memory |
132 | * \param badvaddr Virtual address the instruction tries to access |
133 | * \param badvaddr Virtual address the instruction tries to access |
133 | * |
134 | * |
134 | * \return Type of access into memmory |
135 | * \return Type of access into memmory |
135 | * \note Returns #PF_ACCESS_EXEC if no memory access is requested |
136 | * \note Returns #PF_ACCESS_EXEC if no memory access is requested |
136 | */ |
137 | */ |
137 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
138 | static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr) |
138 | { |
139 | { |
139 | instruction_union_t instr_union; |
140 | instruction_union_t instr_union; |
140 | instr_union.pc = instr_addr; |
141 | instr_union.pc = instr_addr; |
141 | 142 | ||
142 | instruction_t instr = *(instr_union.instr); |
143 | instruction_t instr = *(instr_union.instr); |
143 | 144 | ||
144 | // undefined instructions |
145 | // undefined instructions |
145 | if (instr.condition == 0xf) { |
146 | if (instr.condition == 0xf) { |
146 | panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)", |
147 | panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)", |
147 | instr, badvaddr); |
148 | instr, badvaddr); |
148 | return PF_ACCESS_EXEC; |
149 | return PF_ACCESS_EXEC; |
149 | } |
150 | } |
150 | 151 | ||
151 | // load store instructions |
152 | // load store instructions |
152 | if (is_load_store_instruction(instr)) { |
153 | if (is_load_store_instruction(instr)) { |
153 | if (instr.access == 1) { |
154 | if (instr.access == 1) { |
154 | return PF_ACCESS_READ; |
155 | return PF_ACCESS_READ; |
155 | } else { |
156 | } else { |
156 | return PF_ACCESS_WRITE; |
157 | return PF_ACCESS_WRITE; |
157 | } |
158 | } |
158 | } |
159 | } |
159 | 160 | ||
160 | // swap, swpb instruction |
161 | // swap, swpb instruction |
161 | if (is_swap_instruction(instr)) { |
162 | if (is_swap_instruction(instr)) { |
162 | /* Swap instructions make read and write in one step. |
163 | /* Swap instructions make read and write in one step. |
163 | * Type of access that caused exception have to page tables |
164 | * Type of access that caused exception have to page tables |
164 | * and access rights. |
165 | * and access rights. |
165 | */ |
166 | */ |
166 | 167 | ||
167 | pte_level1_t* pte = (pte_level1_t*) |
168 | pte_level1_t* pte = (pte_level1_t*) |
168 | pt_mapping_operations.mapping_find(AS, badvaddr); |
169 | pt_mapping_operations.mapping_find(AS, badvaddr); |
169 | 170 | ||
170 | if ( pte == NULL ) { |
171 | if ( pte == NULL ) { |
171 | return PF_ACCESS_READ; |
172 | return PF_ACCESS_READ; |
172 | } |
173 | } |
173 | 174 | ||
174 | /* check if read possible |
175 | /* check if read possible |
175 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
176 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
176 | if ( !PTE_PRESENT(pte) ) { |
177 | if ( !PTE_PRESENT(pte) ) { |
177 | return PF_ACCESS_READ; |
178 | return PF_ACCESS_READ; |
178 | } |
179 | } |
179 | 180 | ||
180 | if ( !PTE_WRITABLE(pte) ) { |
181 | if ( !PTE_WRITABLE(pte) ) { |
181 | return PF_ACCESS_WRITE; |
182 | return PF_ACCESS_WRITE; |
182 | } else { |
183 | } else { |
183 | // badvaddr is present readable and writeable but error occured ... why? |
184 | // badvaddr is present readable and writeable but error occured ... why? |
184 | panic("page_fault - swap instruction, but address readable and writeable" |
185 | panic("page_fault - swap instruction, but address readable and writeable" |
185 | "(instr_code:%X, badvaddr:%X)", instr, badvaddr); |
186 | "(instr_code:%X, badvaddr:%X)", instr, badvaddr); |
186 | } |
187 | } |
187 | } |
188 | } |
188 | 189 | ||
189 | panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)", |
190 | panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)", |
190 | instr, badvaddr); |
191 | instr, badvaddr); |
191 | 192 | ||
192 | return PF_ACCESS_EXEC; |
193 | return PF_ACCESS_EXEC; |
193 | } |
194 | } |
194 | 195 | ||
195 | /** Handles "data abort" exception (load or store at invalid address). |
196 | /** Handles "data abort" exception (load or store at invalid address). |
196 | * |
197 | * |
197 | * \param exc_no exception number |
198 | * \param exc_no exception number |
198 | * \param istate CPU state when exception occured |
199 | * \param istate CPU state when exception occured |
199 | */ |
200 | */ |
200 | void data_abort(int exc_no, istate_t *istate) |
201 | void data_abort(int exc_no, istate_t *istate) |
201 | { |
202 | { |
202 | fault_status_t fsr = read_fault_status_register(); |
203 | fault_status_t fsr = read_fault_status_register(); |
203 | uintptr_t badvaddr = read_fault_address_register(); |
204 | uintptr_t badvaddr = read_fault_address_register(); |
204 | 205 | ||
205 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
206 | pf_access_t access = get_memory_access_type(istate->pc, badvaddr); |
206 | 207 | ||
207 | int ret = as_page_fault(badvaddr, access, istate); |
208 | int ret = as_page_fault(badvaddr, access, istate); |
208 | 209 | ||
209 | if (ret == AS_PF_FAULT) { |
210 | if (ret == AS_PF_FAULT) { |
210 | print_istate(istate); |
211 | print_istate(istate); |
211 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n", |
212 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n", |
212 | istate->pc, badvaddr, fsr.status, fsr, access); |
213 | istate->pc, badvaddr, fsr.status, fsr, access); |
213 | 214 | ||
214 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
215 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
215 | panic("page fault\n"); |
216 | panic("page fault\n"); |
216 | } |
217 | } |
217 | } |
218 | } |
218 | 219 | ||
219 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
220 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
220 | * |
221 | * |
221 | * \param exc_no exception number |
222 | * \param exc_no exception number |
222 | * \param istate CPU state when exception occured |
223 | * \param istate CPU state when exception occured |
223 | */ |
224 | */ |
224 | void prefetch_abort(int exc_no, istate_t *istate) |
225 | void prefetch_abort(int exc_no, istate_t *istate) |
225 | { |
226 | { |
226 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
227 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
227 | 228 | ||
228 | if (ret == AS_PF_FAULT) { |
229 | if (ret == AS_PF_FAULT) { |
229 | dprintf("prefetch_abort\n"); |
230 | dprintf("prefetch_abort\n"); |
230 | print_istate(istate); |
231 | print_istate(istate); |
231 | panic("page fault - prefetch_abort at address: %x\n", istate->pc); |
232 | panic("page fault - prefetch_abort at address: %x\n", istate->pc); |
232 | } |
233 | } |
233 | } |
234 | } |
234 | 235 | ||
235 | /** @} |
236 | /** @} |
236 | */ |
237 | */ |
237 | 238 | ||
238 | 239 |