WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/mm/page_fault.c


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32mm
 * @{
 */
/** @file
 */
#include <panic.h>
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/mm/page_fault.h>
#include <mm/as.h>
#include <genarch/mm/page_pt.h>
#include <arch.h>
#include <interrupt.h>
 
 
/** Returns value stored in fault status register.
 *      FSR contain reason of page fault
 *
 *  @return Value stored in CP15 fault status register (FSR).
 */
static inline fault_status_t read_fault_status_register(void)
{
    fault_status_union_t fsu;
 
    // fault adress is stored in CP15 register 5
    asm volatile (
        "mrc p15, 0, %0, c5, c0, 0"
        : "=r"(fsu.dummy)
    );
    return fsu.fs;
}
 
 
/** Returns FAR (fault address register) content.
 *
 *  @return FAR (fault address register) content (address that caused a page fault)
 */
static inline uintptr_t read_fault_address_register(void)
{
    uintptr_t ret;
   
    // fault adress is stored in CP15 register 6
    asm volatile (
        "mrc p15, 0, %0, c6, c0, 0"
        : "=r"(ret)
    );
    return ret;
}
 
 
/** Decides whether the instructions is load/store or not.
 *
 * @param instr Instruction
 *
 * @return true when instruction is load/store, false otherwise
 */
static inline bool is_load_store_instruction(instruction_t instr)
{
    // load store immediate offset
    if (instr.type == 0x2) {
        return true;
    }
 
    // load store register offset
    if (instr.type == 0x3 && instr.bit4 == 0) {
        return true;
    }
 
    // load store multiple
    if (instr.type == 0x4) {
        return true;
    }
 
    // coprocessor load/store
    if (instr.type == 0x6) {
        return true;
    }
 
    return false;
}
 
 
/** Decides whether the instructions is swap or not.
 *
 * @param instr Instruction
 *
 * @return true when instruction is swap, false otherwise
 */
static inline bool is_swap_instruction(instruction_t instr)
{
    // swap, swapb instruction
    if (instr.type == 0x0 &&
        (instr.opcode == 0x8 || instr.opcode == 0xa) &&
        instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
        return true;
    }
 
    return false;
}
 
 
/** Decides whether read or write into memory is requested.
 *
 * @param instr_addr   Address of instruction which tries to access memory
 * @param badvaddr     Virtual address the instruction tries to access
 *
 * @return Type of access into memmory
 * Note:   Returns #PF_ACCESS_EXEC if no memory access is requested
 */
static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
{  
    instruction_union_t instr_union;
    instr_union.pc = instr_addr;
 
    instruction_t instr = *(instr_union.instr);
 
    // undefined instructions
    if (instr.condition == 0xf) {
        panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)",
            instr, badvaddr);
        return PF_ACCESS_EXEC;
    }
 
    // load store instructions
    if (is_load_store_instruction(instr)) {
        if (instr.access == 1) {
            return PF_ACCESS_READ;
        } else {
            return PF_ACCESS_WRITE;
        }
    }
 
    // swap, swpb instruction
    if (is_swap_instruction(instr)) {
        /* Swap instructions make read and write in one step.
         * Type of access that caused exception have to page tables
         *  and access rights.
         */
       
        pte_level1_t* pte = (pte_level1_t*)
        pt_mapping_operations.mapping_find(AS, badvaddr);
 
        if ( pte == NULL ) {
            return PF_ACCESS_READ;
        }
 
        /* check if read possible
        * Note: Don't check PTE_READABLE because it returns 1 everytimes */
        if ( !PTE_PRESENT(pte) ) {
            return PF_ACCESS_READ;
        }
 
        if ( !PTE_WRITABLE(pte) ) {
            return PF_ACCESS_WRITE;
        } else {
            // badvaddr is present readable and writeable but error occured ... why?
            panic("page_fault - swap instruction, but address readable and writeable"
                "(instr_code:%X, badvaddr:%X)", instr, badvaddr);
        }
    }
 
    panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)",
        instr, badvaddr);
 
    return PF_ACCESS_EXEC;
}
 
/** Handles "data abort" exception (load or store at invalid address).
 *
 * @param exc_no    exception number
 * @param istate    CPU state when exception occured
 */
void data_abort(int exc_no, istate_t *istate)
{
    fault_status_t fsr = read_fault_status_register();
    uintptr_t badvaddr = read_fault_address_register();
 
    pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
   
    int ret = as_page_fault(badvaddr, access, istate);
 
    if (ret == AS_PF_FAULT) {
        print_istate(istate);
        dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",
            istate->pc, badvaddr, fsr.status, fsr, access);
 
        fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
        panic("page fault\n");
    }
}
 
/** Handles "prefetch abort" exception (instruction couldn't be executed).
 *
 * @param exc_no    exception number
 * @param istate    CPU state when exception occured
 */
void prefetch_abort(int exc_no, istate_t *istate)
{
    int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
 
    if (ret == AS_PF_FAULT) {
        dprintf("prefetch_abort\n");
        print_istate(istate);
        panic("page fault - prefetch_abort at address: %x\n", istate->pc);
    }
}
 
/** @}
 */
 
 

Rev 2361	Rev 2362
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32mm	29	/** @addtogroup arm32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34	#include <panic.h>	34	#include <panic.h>
35	#include <arch/exception.h>	35	#include <arch/exception.h>
36	#include <arch/debug/print.h>	36	#include <arch/debug/print.h>
37	#include <arch/mm/page_fault.h>	37	#include <arch/mm/page_fault.h>
38	#include <mm/as.h>	38	#include <mm/as.h>
39	#include <genarch/mm/page_pt.h>	39	#include <genarch/mm/page_pt.h>
40	#include <arch.h>	40	#include <arch.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42		42
43		43
44	/** Returns value stored in fault status register.	44	/** Returns value stored in fault status register.
45	* FSR contain reason of page fault	45	* FSR contain reason of page fault
46	*	46	*
47	* \return Value stored in CP15 fault status register (FSR).	47	* @return Value stored in CP15 fault status register (FSR).
48	*/	48	*/
49	static inline fault_status_t read_fault_status_register(void)	49	static inline fault_status_t read_fault_status_register(void)
50	{	50	{
51	fault_status_union_t fsu;	51	fault_status_union_t fsu;
52		52
53	// fault adress is stored in CP15 register 5	53	// fault adress is stored in CP15 register 5
54	asm volatile (	54	asm volatile (
55	"mrc p15, 0, %0, c5, c0, 0"	55	"mrc p15, 0, %0, c5, c0, 0"
56	: "=r"(fsu.dummy)	56	: "=r"(fsu.dummy)
57	);	57	);
58	return fsu.fs;	58	return fsu.fs;
59	}	59	}
60		60
61		61
62	/** Returns FAR (fault address register) content.	62	/** Returns FAR (fault address register) content.
63	*	63	*
64	* \return FAR (fault address register) content (address that caused a page fault)	64	* @return FAR (fault address register) content (address that caused a page fault)
65	*/	65	*/
66	static inline uintptr_t read_fault_address_register(void)	66	static inline uintptr_t read_fault_address_register(void)
67	{	67	{
68	uintptr_t ret;	68	uintptr_t ret;
69		69
70	// fault adress is stored in CP15 register 6	70	// fault adress is stored in CP15 register 6
71	asm volatile (	71	asm volatile (
72	"mrc p15, 0, %0, c6, c0, 0"	72	"mrc p15, 0, %0, c6, c0, 0"
73	: "=r"(ret)	73	: "=r"(ret)
74	);	74	);
75	return ret;	75	return ret;
76	}	76	}
77		77
78		78
79	/** Decides whether the instructions is load/store or not.	79	/** Decides whether the instructions is load/store or not.
80	*	80	*
81	* \param instr Instruction	81	* @param instr Instruction
82	*	82	*
83	* \return true when instruction is load/store, false otherwise	83	* @return true when instruction is load/store, false otherwise
84	*/	84	*/
85	static inline bool is_load_store_instruction(instruction_t instr)	85	static inline bool is_load_store_instruction(instruction_t instr)
86	{	86	{
87	// load store immediate offset	87	// load store immediate offset
88	if (instr.type == 0x2) {	88	if (instr.type == 0x2) {
89	return true;	89	return true;
90	}	90	}
91		91
92	// load store register offset	92	// load store register offset
93	if (instr.type == 0x3 && instr.bit4 == 0) {	93	if (instr.type == 0x3 && instr.bit4 == 0) {
94	return true;	94	return true;
95	}	95	}
96		96
97	// load store multiple	97	// load store multiple
98	if (instr.type == 0x4) {	98	if (instr.type == 0x4) {
99	return true;	99	return true;
100	}	100	}
101		101
102	// coprocessor load/store	102	// coprocessor load/store
103	if (instr.type == 0x6) {	103	if (instr.type == 0x6) {
104	return true;	104	return true;
105	}	105	}
106		106
107	return false;	107	return false;
108	}	108	}
109		109
110		110
111	/** Decides whether the instructions is swap or not.	111	/** Decides whether the instructions is swap or not.
112	*	112	*
113	* \param instr Instruction	113	* @param instr Instruction
114	*	114	*
115	* \return true when instruction is swap, false otherwise	115	* @return true when instruction is swap, false otherwise
116	*/	116	*/
117	static inline bool is_swap_instruction(instruction_t instr)	117	static inline bool is_swap_instruction(instruction_t instr)
118	{	118	{
119	// swap, swapb instruction	119	// swap, swapb instruction
120	if (instr.type == 0x0 &&	120	if (instr.type == 0x0 &&
121	(instr.opcode == 0x8 \|\| instr.opcode == 0xa) &&	121	(instr.opcode == 0x8 \|\| instr.opcode == 0xa) &&
122	instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {	122	instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) {
123	return true;	123	return true;
124	}	124	}
125		125
126	return false;	126	return false;
127	}	127	}
128		128
129		129
130	/** Decides whether read or write into memory is requested.	130	/** Decides whether read or write into memory is requested.
131	*	131	*
132	* \param instr_addr Address of instruction which tries to access memory	132	* @param instr_addr Address of instruction which tries to access memory
133	* \param badvaddr Virtual address the instruction tries to access	133	* @param badvaddr Virtual address the instruction tries to access
134	*	134	*
135	* \return Type of access into memmory	135	* @return Type of access into memmory
136	* \note Returns #PF_ACCESS_EXEC if no memory access is requested	136	* Note: Returns #PF_ACCESS_EXEC if no memory access is requested
137	*/	137	*/
138	static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)	138	static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
139	{	139	{
140	instruction_union_t instr_union;	140	instruction_union_t instr_union;
141	instr_union.pc = instr_addr;	141	instr_union.pc = instr_addr;
142		142
143	instruction_t instr = *(instr_union.instr);	143	instruction_t instr = *(instr_union.instr);
144		144
145	// undefined instructions	145	// undefined instructions
146	if (instr.condition == 0xf) {	146	if (instr.condition == 0xf) {
147	panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)",	147	panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)",
148	instr, badvaddr);	148	instr, badvaddr);
149	return PF_ACCESS_EXEC;	149	return PF_ACCESS_EXEC;
150	}	150	}
151		151
152	// load store instructions	152	// load store instructions
153	if (is_load_store_instruction(instr)) {	153	if (is_load_store_instruction(instr)) {
154	if (instr.access == 1) {	154	if (instr.access == 1) {
155	return PF_ACCESS_READ;	155	return PF_ACCESS_READ;
156	} else {	156	} else {
157	return PF_ACCESS_WRITE;	157	return PF_ACCESS_WRITE;
158	}	158	}
159	}	159	}
160		160
161	// swap, swpb instruction	161	// swap, swpb instruction
162	if (is_swap_instruction(instr)) {	162	if (is_swap_instruction(instr)) {
163	/* Swap instructions make read and write in one step.	163	/* Swap instructions make read and write in one step.
164	* Type of access that caused exception have to page tables	164	* Type of access that caused exception have to page tables
165	* and access rights.	165	* and access rights.
166	*/	166	*/
167		167
168	pte_level1_t* pte = (pte_level1_t*)	168	pte_level1_t* pte = (pte_level1_t*)
169	pt_mapping_operations.mapping_find(AS, badvaddr);	169	pt_mapping_operations.mapping_find(AS, badvaddr);
170		170
171	if ( pte == NULL ) {	171	if ( pte == NULL ) {
172	return PF_ACCESS_READ;	172	return PF_ACCESS_READ;
173	}	173	}
174		174
175	/* check if read possible	175	/* check if read possible
176	* Note: Don't check PTE_READABLE because it returns 1 everytimes */	176	* Note: Don't check PTE_READABLE because it returns 1 everytimes */
177	if ( !PTE_PRESENT(pte) ) {	177	if ( !PTE_PRESENT(pte) ) {
178	return PF_ACCESS_READ;	178	return PF_ACCESS_READ;
179	}	179	}
180		180
181	if ( !PTE_WRITABLE(pte) ) {	181	if ( !PTE_WRITABLE(pte) ) {
182	return PF_ACCESS_WRITE;	182	return PF_ACCESS_WRITE;
183	} else {	183	} else {
184	// badvaddr is present readable and writeable but error occured ... why?	184	// badvaddr is present readable and writeable but error occured ... why?
185	panic("page_fault - swap instruction, but address readable and writeable"	185	panic("page_fault - swap instruction, but address readable and writeable"
186	"(instr_code:%X, badvaddr:%X)", instr, badvaddr);	186	"(instr_code:%X, badvaddr:%X)", instr, badvaddr);
187	}	187	}
188	}	188	}
189		189
190	panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)",	190	panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)",
191	instr, badvaddr);	191	instr, badvaddr);
192		192
193	return PF_ACCESS_EXEC;	193	return PF_ACCESS_EXEC;
194	}	194	}
195		195
196	/** Handles "data abort" exception (load or store at invalid address).	196	/** Handles "data abort" exception (load or store at invalid address).
197	*	197	*
198	* \param exc_no exception number	198	* @param exc_no exception number
199	* \param istate CPU state when exception occured	199	* @param istate CPU state when exception occured
200	*/	200	*/
201	void data_abort(int exc_no, istate_t *istate)	201	void data_abort(int exc_no, istate_t *istate)
202	{	202	{
203	fault_status_t fsr = read_fault_status_register();	203	fault_status_t fsr = read_fault_status_register();
204	uintptr_t badvaddr = read_fault_address_register();	204	uintptr_t badvaddr = read_fault_address_register();
205		205
206	pf_access_t access = get_memory_access_type(istate->pc, badvaddr);	206	pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
207		207
208	int ret = as_page_fault(badvaddr, access, istate);	208	int ret = as_page_fault(badvaddr, access, istate);
209		209
210	if (ret == AS_PF_FAULT) {	210	if (ret == AS_PF_FAULT) {
211	print_istate(istate);	211	print_istate(istate);
212	dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",	212	dprintf("page fault - pc: %x, va: %x, status: %x(%x), access:%d\n",
213	istate->pc, badvaddr, fsr.status, fsr, access);	213	istate->pc, badvaddr, fsr.status, fsr, access);
214		214
215	fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);	215	fault_if_from_uspace(istate, "Page fault: %#x", badvaddr);
216	panic("page fault\n");	216	panic("page fault\n");
217	}	217	}
218	}	218	}
219		219
220	/** Handles "prefetch abort" exception (instruction couldn't be executed).	220	/** Handles "prefetch abort" exception (instruction couldn't be executed).
221	*	221	*
222	* \param exc_no exception number	222	* @param exc_no exception number
223	* \param istate CPU state when exception occured	223	* @param istate CPU state when exception occured
224	*/	224	*/
225	void prefetch_abort(int exc_no, istate_t *istate)	225	void prefetch_abort(int exc_no, istate_t *istate)
226	{	226	{
227	int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);	227	int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate);
228		228
229	if (ret == AS_PF_FAULT) {	229	if (ret == AS_PF_FAULT) {
230	dprintf("prefetch_abort\n");	230	dprintf("prefetch_abort\n");
231	print_istate(istate);	231	print_istate(istate);
232	panic("page fault - prefetch_abort at address: %x\n", istate->pc);	232	panic("page fault - prefetch_abort at address: %x\n", istate->pc);
233	}	233	}
234	}	234	}
235		235
236	/** @}	236	/** @}
237	*/	237	*/
238		238
239		239

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(root)/branches/arm/kernel/arch/arm32/src/mm/page_fault.c @ 3842 – Rev 2361 → 2362