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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
2 | * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | #include <panic.h> |
34 | #include <panic.h> |
35 | #include <arch/exception.h> |
35 | #include <arch/exception.h> |
36 | #include <arch/debug_print/print.h> |
36 | #include <arch/debug_print/print.h> |
37 | #include <arch/mm/page_fault.h> |
37 | #include <arch/mm/page_fault.h> |
38 | #include <mm/as.h> |
38 | #include <mm/as.h> |
39 | #include <genarch/mm/page_pt.h> |
39 | #include <genarch/mm/page_pt.h> |
40 | #include <arch.h> |
40 | #include <arch.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | 42 | ||
43 | 43 | ||
44 | //TODO: remove in final version |
44 | //TODO: remove in final version |
45 | static void print_istate(istate_t* istate); |
45 | static void print_istate(istate_t* istate); |
46 | static void print_istate(istate_t* istate) { |
46 | static void print_istate(istate_t* istate) { |
47 | dprintf("\nIstate dump:\n"); |
47 | dprintf("\nIstate dump:\n"); |
48 | dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3); |
48 | dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3); |
49 | dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7); |
49 | dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7); |
50 | dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11); |
50 | dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11); |
51 | dprintf(" r12:%X sp:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr); |
51 | dprintf(" r12:%X sp:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr); |
- | 52 | dprintf(" pc:%X\n", istate->pc); |
|
- | 53 | ||
52 | } |
54 | } |
53 | 55 | ||
54 | /** |
56 | /** |
55 | * \return Value stored in fault status register |
57 | * \return Value stored in fault status register |
56 | */ |
58 | */ |
57 | static inline fault_status_t read_fault_status_register() { |
59 | static inline fault_status_t read_fault_status_register() { |
58 | fault_status_union_t tmp; |
60 | fault_status_union_t tmp; |
59 | asm volatile ( |
61 | asm volatile ( |
60 | "mrc p15, 0, %0, c5, c0, 0" |
62 | "mrc p15, 0, %0, c5, c0, 0" |
61 | : "=r"(tmp.dummy) |
63 | : "=r"(tmp.dummy) |
62 | ); |
64 | ); |
63 | return tmp.fsr; |
65 | return tmp.fsr; |
64 | } |
66 | } |
65 | 67 | ||
66 | /** |
68 | /** |
67 | * \return Virtual adress. Access on this addres caused exception |
69 | * \return Virtual adress. Access on this addres caused exception |
68 | */ |
70 | */ |
69 | static inline uintptr_t read_fault_address_register() { |
71 | static inline uintptr_t read_fault_address_register() { |
70 | uintptr_t tmp; |
72 | uintptr_t tmp; |
71 | // Fault adress is stored in coprocessor15, register 6 |
73 | // Fault adress is stored in coprocessor15, register 6 |
72 | asm volatile ( |
74 | asm volatile ( |
73 | "mrc p15, 0, %0, c6, c0, 0" |
75 | "mrc p15, 0, %0, c6, c0, 0" |
74 | : "=r"(tmp) |
76 | : "=r"(tmp) |
75 | ); |
77 | ); |
76 | return tmp; |
78 | return tmp; |
77 | }; |
79 | }; |
78 | 80 | ||
79 | /** Check type of instruction |
81 | /** Check type of instruction |
80 | * \param i_code Instruction op code |
82 | * \param i_code Instruction op code |
81 | * \return true if instruction is load or store, false otherwise |
83 | * \return true if instruction is load or store, false otherwise |
82 | */ |
84 | */ |
83 | static inline bool load_store_instruction(instruction_t i_code) { |
85 | static inline bool load_store_instruction(instruction_t i_code) { |
84 | 86 | ||
85 | // load store immediate offset |
87 | // load store immediate offset |
86 | if (i_code.instr_type == 0x2) { |
88 | if (i_code.instr_type == 0x2) { |
87 | return true; |
89 | return true; |
88 | }; |
90 | }; |
89 | 91 | ||
90 | // load store register offset |
92 | // load store register offset |
91 | if (i_code.instr_type == 0x3 && i_code.bit4 == 0) { |
93 | if (i_code.instr_type == 0x3 && i_code.bit4 == 0) { |
92 | return true; |
94 | return true; |
93 | }; |
95 | }; |
94 | 96 | ||
95 | // load store multiple |
97 | // load store multiple |
96 | if (i_code.instr_type == 0x4) { |
98 | if (i_code.instr_type == 0x4) { |
97 | return true; |
99 | return true; |
98 | }; |
100 | }; |
99 | 101 | ||
100 | // coprocessor load / strore |
102 | // coprocessor load / strore |
101 | if (i_code.instr_type == 0x6) { |
103 | if (i_code.instr_type == 0x6) { |
102 | return true; |
104 | return true; |
103 | }; |
105 | }; |
104 | 106 | ||
105 | return false; |
107 | return false; |
106 | } |
108 | } |
107 | 109 | ||
108 | /** Check type of instruction |
110 | /** Check type of instruction |
109 | * \param i_code Instruction op code |
111 | * \param i_code Instruction op code |
110 | * \return true if instruction is swap, false otherwise |
112 | * \return true if instruction is swap, false otherwise |
111 | */ |
113 | */ |
112 | static inline bool swap_instruction(instruction_t i_code) { |
114 | static inline bool swap_instruction(instruction_t i_code) { |
113 | 115 | ||
114 | // swap, swapb instruction |
116 | // swap, swapb instruction |
115 | if (i_code.instr_type == 0x0 && |
117 | if (i_code.instr_type == 0x0 && |
116 | (i_code.opcode == 0x8 || i_code.opcode == 0xA) && |
118 | (i_code.opcode == 0x8 || i_code.opcode == 0xA) && |
117 | i_code.access == 0x0 && i_code.bits567 == 0x4 && |
119 | i_code.access == 0x0 && i_code.bits567 == 0x4 && |
118 | i_code.bit4 == 1) { |
120 | i_code.bit4 == 1) { |
119 | return true; |
121 | return true; |
120 | }; |
122 | }; |
121 | 123 | ||
122 | return false; |
124 | return false; |
123 | } |
125 | } |
124 | 126 | ||
125 | 127 | ||
126 | /** |
128 | /** |
127 | * Decode instruction and decide if try to read or write into memmory. |
129 | * Decode instruction and decide if try to read or write into memmory. |
128 | * |
130 | * |
129 | * \param instr_addr address of instruction which attempts access into memmory |
131 | * \param instr_addr address of instruction which attempts access into memmory |
130 | * \param badvaddr Virtual address on which instruction tries to access |
132 | * \param badvaddr Virtual address on which instruction tries to access |
131 | * \return type of access into memmory |
133 | * \return type of access into memmory |
132 | * Note: return PF_ACESS_EXEC if no memmory acess |
134 | * Note: return PF_ACESS_EXEC if no memmory acess |
133 | */ |
135 | */ |
134 | //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC |
136 | //TODO: remove debug print in final version ... instead panic return PF_ACESS_EXEC |
135 | static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) { |
137 | static pf_access_t get_memmory_access_type(uint32_t instr_addr, uintptr_t badvaddr) { |
136 | instruction_union_t tmp; |
138 | instruction_union_t tmp; |
137 | tmp.ip = instr_addr; |
139 | tmp.ip = instr_addr; |
138 | // get instruction op code |
140 | // get instruction op code |
139 | instruction_t i_code = *(tmp.instr); |
141 | instruction_t i_code = *(tmp.instr); |
140 | 142 | ||
141 | // dprintf("get_instruction_memmory_access\n"); |
143 | // dprintf("get_instruction_memmory_access\n"); |
142 | // dprintf(" instr_addr:%X\n",instr_addr); |
144 | // dprintf(" instr_addr:%X\n",instr_addr); |
143 | // dprintf(" i_code:%X\n",i_code); |
145 | // dprintf(" i_code:%X\n",i_code); |
144 | // dprintf(" i_code.condition:%d\n", i_code.condition); |
146 | // dprintf(" i_code.condition:%d\n", i_code.condition); |
145 | // dprintf(" i_code.instr_type:%d\n",i_code.instr_type); |
147 | // dprintf(" i_code.instr_type:%d\n",i_code.instr_type); |
146 | // dprintf(" i_code.opcode:%d\n",i_code.opcode); |
148 | // dprintf(" i_code.opcode:%d\n",i_code.opcode); |
147 | // dprintf(" i_code.acess:%d\n", i_code.access); |
149 | // dprintf(" i_code.acess:%d\n", i_code.access); |
148 | // dprintf(" i_code.dummy:%d\n", i_code.dummy); |
150 | // dprintf(" i_code.dummy:%d\n", i_code.dummy); |
149 | // dprintf(" i_code.bits567%d\n", i_code.bits567); |
151 | // dprintf(" i_code.bits567%d\n", i_code.bits567); |
150 | // dprintf(" i_code.bit4:%d\n", i_code.bit4); |
152 | // dprintf(" i_code.bit4:%d\n", i_code.bit4); |
151 | // dprintf(" i_code.dummy1:%d\n", i_code.dummy1); |
153 | // dprintf(" i_code.dummy1:%d\n", i_code.dummy1); |
152 | 154 | ||
153 | 155 | ||
154 | // undefined instructions ... (or special instructions) |
156 | // undefined instructions ... (or special instructions) |
155 | if (i_code.condition == 0xf) { |
157 | if (i_code.condition == 0xf) { |
156 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
158 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
157 | return PF_ACCESS_EXEC; |
159 | return PF_ACCESS_EXEC; |
158 | }; |
160 | }; |
159 | 161 | ||
160 | // load store instructions |
162 | // load store instructions |
161 | if (load_store_instruction(i_code)) { |
163 | if (load_store_instruction(i_code)) { |
162 | if ( i_code.access == 1) { |
164 | if ( i_code.access == 1) { |
163 | return PF_ACCESS_READ; |
165 | return PF_ACCESS_READ; |
164 | } else { |
166 | } else { |
165 | return PF_ACCESS_WRITE; |
167 | return PF_ACCESS_WRITE; |
166 | } |
168 | } |
167 | }; |
169 | }; |
168 | 170 | ||
169 | // swap, swpb instruction |
171 | // swap, swpb instruction |
170 | if (swap_instruction(i_code)) |
172 | if (swap_instruction(i_code)) |
171 | { |
173 | { |
172 | /* Swap instructions make read and write in one step. |
174 | /* Swap instructions make read and write in one step. |
173 | * Type of access that caused exception have to page tables |
175 | * Type of access that caused exception have to page tables |
174 | * and access rights. |
176 | * and access rights. |
175 | */ |
177 | */ |
176 | //TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread |
178 | //TODO: ALF!!!!! cann't use AS as is define as THE->as and THE structure is sored after stack_base of current thread |
177 | // but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data |
179 | // but now ... in exception we have separate stacks <==> different stack_pointer ... so AS contains nonsence data |
178 | // same case as_page_fault .... it's nessesary to solve "stack" problem |
180 | // same case as_page_fault .... it's nessesary to solve "stack" problem |
179 | pte_level1_t* pte = (pte_level1_t*) |
181 | pte_level1_t* pte = (pte_level1_t*) |
180 | pt_mapping_operations.mapping_find(AS, badvaddr); |
182 | pt_mapping_operations.mapping_find(AS, badvaddr); |
181 | 183 | ||
182 | ASSERT(pte); |
184 | ASSERT(pte); |
183 | 185 | ||
184 | /* check if read possible |
186 | /* check if read possible |
185 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
187 | * Note: Don't check PTE_READABLE because it returns 1 everytimes */ |
186 | if ( !PTE_PRESENT(pte) ) { |
188 | if ( !PTE_PRESENT(pte) ) { |
187 | return PF_ACCESS_READ; |
189 | return PF_ACCESS_READ; |
188 | } |
190 | } |
189 | if ( !PTE_WRITABLE(pte) ) { |
191 | if ( !PTE_WRITABLE(pte) ) { |
190 | return PF_ACCESS_WRITE; |
192 | return PF_ACCESS_WRITE; |
191 | } |
193 | } |
192 | else |
194 | else |
193 | // badvaddr is present readable and writeable but error occured ... why? |
195 | // badvaddr is present readable and writeable but error occured ... why? |
194 | panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
196 | panic("page_fault - swap instruction, but address readable and writeable (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
195 | } |
197 | } |
196 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
198 | panic("page_fault - on instruction not acessing to memmory (instr_code:%X, badvaddr:%X)",i_code, badvaddr); |
197 | return PF_ACCESS_EXEC; |
199 | return PF_ACCESS_EXEC; |
198 | } |
200 | } |
199 | 201 | ||
200 | /** |
202 | /** |
201 | * Routine that solves exception data_abourt |
203 | * Routine that solves exception data_abourt |
202 | * ... you try to load or store value into invalid memmory address |
204 | * ... you try to load or store value into invalid memmory address |
203 | * \param istate State of CPU when data abourt occured |
205 | * \param istate State of CPU when data abourt occured |
204 | * \param n number of exception |
206 | * \param n number of exception |
205 | */ |
207 | */ |
206 | //TODO: remove debug prints in final tested version |
208 | //TODO: remove debug prints in final tested version |
207 | void data_abort(int n, istate_t *istate) { |
209 | void data_abort(int n, istate_t *istate) { |
208 | fault_status_t fsr = read_fault_status_register(); |
210 | fault_status_t fsr = read_fault_status_register(); |
209 | uintptr_t page = read_fault_address_register(); |
211 | uintptr_t page = read_fault_address_register(); |
210 | 212 | ||
211 | pf_access_t access = get_memmory_access_type( istate->lr, page); |
213 | pf_access_t access = get_memmory_access_type( istate->pc, page); |
212 | 214 | ||
213 | // print_istate(istate); |
215 | // print_istate(istate); |
214 | dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->lr, page, fsr.status,fsr, access); |
216 | dprintf(" page fault : ip:%X, va:%X, status:%x(%x), access:%d\n", istate->pc, page, fsr.status,fsr, access); |
215 | 217 | ||
216 | /* Alf: Will be commented until stack problem will be solved ... |
218 | /* Alf: Will be commented until stack problem will be solved ... |
217 | as_page_fault make consequent page faults*/ |
219 | as_page_fault make consequent page faults*/ |
218 | 220 | ||
219 | int ret = as_page_fault(page, access, istate); |
221 | int ret = as_page_fault(page, access, istate); |
220 | dprintf(" as_page_fault ret:%d\n", ret); |
222 | dprintf(" as_page_fault ret:%d\n", ret); |
221 | if (ret == AS_PF_FAULT) { |
223 | if (ret == AS_PF_FAULT) { |
222 | fault_if_from_uspace(istate, "Page fault: %#x", page); |
224 | fault_if_from_uspace(istate, "Page fault: %#x", page); |
223 | - | ||
224 | panic("page fault\n"); |
225 | panic("page fault\n"); |
225 | } |
226 | } |
226 | 227 | ||
227 | // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures |
228 | // TODO: Remove this ... now for testing purposes ... it's bad to test page faults in kernel, where no page faults should occures |
228 | panic("page fault ... solved\n"); |
229 | // panic("page fault ... solved\n"); |
229 | 230 | ||
230 | } |
231 | } |
231 | 232 | ||
232 | /** |
233 | /** |
233 | * Routine that solves exception prefetch_about |
234 | * Routine that solves exception prefetch_about |
234 | * ... you try to execute instruction on invalid address |
235 | * ... you try to execute instruction on invalid address |
235 | * \param istate State of CPU when prefetch abourt occured |
236 | * \param istate State of CPU when prefetch abourt occured |
236 | * \param n number of exception |
237 | * \param n number of exception |
237 | */ |
238 | */ |
238 | void prefetch_abort(int n, istate_t *istate) { |
239 | void prefetch_abort(int n, istate_t *istate) { |
239 | // Prefetch can be made be bkpt instruction |
- | |
240 | print_istate(istate); |
240 | print_istate(istate); |
241 | dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->lr); |
241 | dprintf(" prefetch_abourt ... instruction on adress:%x can't be fetched\n", istate->pc); |
242 | 242 | ||
243 | /* Alf: Will be commented until stack problem will be solved ... |
243 | /* Alf: Will be commented until stack problem will be solved ... |
244 | as_page_fault make consequent page faults*/ |
244 | as_page_fault make consequent page faults*/ |
245 | 245 | ||
246 | int ret = as_page_fault(istate->lr, PF_ACCESS_EXEC, istate); |
246 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
247 | dprintf(" as_page_fault ret:%d\n", ret); |
247 | dprintf(" as_page_fault ret:%d\n", ret); |
248 | if (ret == AS_PF_FAULT) { |
248 | if (ret == AS_PF_FAULT) { |
249 | panic("page fault - instruction fetch at addr:%X\n", istate->lr); |
249 | panic("page fault - instruction fetch at addr:%X\n", istate->pc); |
250 | } |
250 | } |
251 | 251 | ||
252 | 252 | ||
253 | panic("Prefetch abourt ... solved"); |
253 | // panic("Prefetch abourt ... solved"); |
254 | } |
254 | } |
255 | 255 | ||
256 | /** @} |
256 | /** @} |
257 | */ |
257 | */ |
258 | 258 | ||
259 | 259 |