WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/interrupt.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Interrupts controlling routines.
 */
 
#include <arch/asm.h>
#include <arch/regutils.h>
#include <arch/drivers/gxemul.h>
#include <ddi/irq.h>
#include <ddi/device.h>
#include <interrupt.h>
 
/** Initial size of a table holding interrupt handlers. */
#define IRQ_COUNT 8
 
static irq_t gxemul_timer_irq;
 
/** Disable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_disable(void)
{
    ipl_t ipl = current_status_reg_read();
   
    current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl);
   
    return ipl;
}
 
/** Enable interrupts.
 *
 * @return Old interrupt priority level.
 */
ipl_t interrupts_enable(void)
{
    ipl_t ipl = current_status_reg_read();
   
    current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
   
    return ipl;
}
 
/** Restore interrupt priority level.
 *
 * @param ipl Saved interrupt priority level.
 */
void interrupts_restore(ipl_t ipl)
{
    current_status_reg_control_write(
        (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) |
        (ipl & STATUS_REG_IRQ_DISABLED_BIT));
}
 
/** Read interrupt priority level.
 *
 * @return Current interrupt priority level.
 */
ipl_t interrupts_read(void)
{
    return current_status_reg_read();
}
 
/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
 *
 * @param frequency Interrupts frequency (0 disables RTC).
 */
static void gxemul_timer_start(uint32_t frequency)
{
    *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))
        = frequency;
}
 
static irq_ownership_t gxemul_timer_claim(irq_t *irq)
{
    return IRQ_ACCEPT;
}
 
/** Timer interrupt handler.
 *
 * @param irq Interrupt information.
 * @param arg Not used.
 */
static void gxemul_timer_irq_handler(irq_t *irq)
{
    /*
    * We are holding a lock which prevents preemption.
    * Release the lock, call clock() and reacquire the lock again.
    */
    spinlock_unlock(&irq->lock);
    clock();
    spinlock_lock(&irq->lock);
   
    /* acknowledge tick */
    *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))
        = 0;
}
 
/** Initialize basic tables for exception dispatching
 * and starts the timer.
 */
void interrupt_init(void)
{
    irq_init(IRQ_COUNT, IRQ_COUNT);
   
    irq_initialize(&gxemul_timer_irq);
    gxemul_timer_irq.devno = device_assign_devno();
    gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
    gxemul_timer_irq.claim = gxemul_timer_claim;
    gxemul_timer_irq.handler = gxemul_timer_irq_handler;
   
    irq_register(&gxemul_timer_irq);
   
    gxemul_timer_start(GXEMUL_TIMER_FREQ);
}
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/arm/kernel/arch/arm32/src/interrupt.c @ 4745 – Rev 4117 → 4647

Rev 4117		Rev 4647
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Interrupts controlling routines.	33	* @brief Interrupts controlling routines.
34	*/	34	*/
35		35
36	#include <arch/asm.h>	36	#include <arch/asm.h>
37	#include <arch/regutils.h>	37	#include <arch/regutils.h>
38	#include <arch/drivers/gxemul.h>	38	#include <arch/drivers/gxemul.h>
39	#include <ddi/irq.h>	39	#include <ddi/irq.h>
40	#include <ddi/device.h>	40	#include <ddi/device.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42		42
43	/** Initial size of a table holding interrupt handlers. */	43	/** Initial size of a table holding interrupt handlers. */
44	#define IRQ_COUNT 8	44	#define IRQ_COUNT 8
45		45
46	static irq_t gxemul_timer_irq;	46	static irq_t gxemul_timer_irq;
47		47
48	/** Disable interrupts.	48	/** Disable interrupts.
49	*	49	*
50	* @return Old interrupt priority level.	50	* @return Old interrupt priority level.
51	*/	51	*/
52	ipl_t interrupts_disable(void)	52	ipl_t interrupts_disable(void)
53	{	53	{
54	ipl_t ipl = current_status_reg_read();	54	ipl_t ipl = current_status_reg_read();
55		55
56	current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT \| ipl);	56	current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT \| ipl);
57		57
58	return ipl;	58	return ipl;
59	}	59	}
60		60
61	/** Enable interrupts.	61	/** Enable interrupts.
62	*	62	*
63	* @return Old interrupt priority level.	63	* @return Old interrupt priority level.
64	*/	64	*/
65	ipl_t interrupts_enable(void)	65	ipl_t interrupts_enable(void)
66	{	66	{
67	ipl_t ipl = current_status_reg_read();	67	ipl_t ipl = current_status_reg_read();
68		68
69	current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);	69	current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT);
70		70
71	return ipl;	71	return ipl;
72	}	72	}
73		73
74	/** Restore interrupt priority level.	74	/** Restore interrupt priority level.
75	*	75	*
76	* @param ipl Saved interrupt priority level.	76	* @param ipl Saved interrupt priority level.
77	*/	77	*/
78	void interrupts_restore(ipl_t ipl)	78	void interrupts_restore(ipl_t ipl)
79	{	79	{
80	current_status_reg_control_write(	80	current_status_reg_control_write(
81	(current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) \|	81	(current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) \|
82	(ipl & STATUS_REG_IRQ_DISABLED_BIT));	82	(ipl & STATUS_REG_IRQ_DISABLED_BIT));
83	}	83	}
84		84
85	/** Read interrupt priority level.	85	/** Read interrupt priority level.
86	*	86	*
87	* @return Current interrupt priority level.	87	* @return Current interrupt priority level.
88	*/	88	*/
89	ipl_t interrupts_read(void)	89	ipl_t interrupts_read(void)
90	{	90	{
91	return current_status_reg_read();	91	return current_status_reg_read();
92	}	92	}
93		93
94	/** Starts gxemul Real Time Clock device, which asserts regular interrupts.	94	/** Starts gxemul Real Time Clock device, which asserts regular interrupts.
95	*	95	*
96	* @param frequency Interrupts frequency (0 disables RTC).	96	* @param frequency Interrupts frequency (0 disables RTC).
97	*/	97	*/
98	static void gxemul_timer_start(uint32_t frequency)	98	static void gxemul_timer_start(uint32_t frequency)
99	{	99	{
100	((uint32_t ) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))	100	((uint32_t ) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET))
101	= frequency;	101	= frequency;
102	}	102	}
103		103
104	static irq_ownership_t gxemul_timer_claim(irq_t *irq)	104	static irq_ownership_t gxemul_timer_claim(irq_t *irq)
105	{	105	{
106	return IRQ_ACCEPT;	106	return IRQ_ACCEPT;
107	}	107	}
108		108
109	/** Timer interrupt handler.	109	/** Timer interrupt handler.
110	*	110	*
111	* @param irq Interrupt information.	111	* @param irq Interrupt information.
112	* @param arg Not used.	112	* @param arg Not used.
113	*/	113	*/
114	static void gxemul_timer_irq_handler(irq_t *irq)	114	static void gxemul_timer_irq_handler(irq_t *irq)
115	{	115	{
116	/*	116	/*
117	* We are holding a lock which prevents preemption.	117	* We are holding a lock which prevents preemption.
118	* Release the lock, call clock() and reacquire the lock again.	118	* Release the lock, call clock() and reacquire the lock again.
119	*/	119	*/
120	spinlock_unlock(&irq->lock);	120	spinlock_unlock(&irq->lock);
121	clock();	121	clock();
122	spinlock_lock(&irq->lock);	122	spinlock_lock(&irq->lock);
123		123
124	/* acknowledge tick */	124	/* acknowledge tick */
125	((uint32_t ) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))	125	((uint32_t ) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET))
126	= 0;	126	= 0;
127	}	127	}
128		128
129	/** Initialize basic tables for exception dispatching	129	/** Initialize basic tables for exception dispatching
130	* and starts the timer.	130	* and starts the timer.
131	*/	131	*/
132	void interrupt_init(void)	132	void interrupt_init(void)
133	{	133	{
134	irq_init(IRQ_COUNT, IRQ_COUNT);	134	irq_init(IRQ_COUNT, IRQ_COUNT);
135		135
136	irq_initialize(&gxemul_timer_irq);	136	irq_initialize(&gxemul_timer_irq);
137	gxemul_timer_irq.devno = device_assign_devno();	137	gxemul_timer_irq.devno = device_assign_devno();
138	gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;	138	gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ;
139	gxemul_timer_irq.claim = gxemul_timer_claim;	139	gxemul_timer_irq.claim = gxemul_timer_claim;
140	gxemul_timer_irq.handler = gxemul_timer_irq_handler;	140	gxemul_timer_irq.handler = gxemul_timer_irq_handler;
141		141
142	irq_register(&gxemul_timer_irq);	142	irq_register(&gxemul_timer_irq);
143		143
144	gxemul_timer_start(GXEMUL_TIMER_FREQ);	144	gxemul_timer_start(GXEMUL_TIMER_FREQ);
145	}	145	}
146		146
147	/** @}	147	/** @}
148	*/	148	*/
149		149