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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <arch/asm.h> |
35 | #include <arch/asm.h> |
36 | #include <arch/regutils.h> |
36 | #include <arch/regutils.h> |
37 | #include <ddi/irq.h> |
37 | #include <ddi/irq.h> |
38 | #include <arch/drivers/gxemul.h> |
38 | #include <arch/drivers/gxemul.h> |
39 | #include <interrupt.h> |
39 | #include <interrupt.h> |
40 | 40 | ||
41 | #define IRQ_COUNT 8 |
41 | #define IRQ_COUNT 8 |
42 | 42 | ||
43 | 43 | ||
44 | /** Disable interrupts. |
44 | /** Disable interrupts. |
45 | * |
45 | * |
46 | * @return Old interrupt priority level. |
46 | * @return Old interrupt priority level. |
47 | */ |
47 | */ |
48 | ipl_t interrupts_disable(void) |
48 | ipl_t interrupts_disable(void) |
49 | { |
49 | { |
50 | ipl_t ipl = current_status_reg_read(); |
50 | ipl_t ipl = current_status_reg_read(); |
51 | 51 | ||
52 | current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
52 | current_status_reg_control_write(ipl & ~STATUS_REG_IE_ENABLED_BIT); |
53 | 53 | ||
54 | return ipl; |
54 | return ipl; |
55 | } |
55 | } |
56 | 56 | ||
57 | /** Enable interrupts. |
57 | /** Enable interrupts. |
58 | * |
58 | * |
59 | * @return Old interrupt priority level. |
59 | * @return Old interrupt priority level. |
60 | */ |
60 | */ |
61 | ipl_t interrupts_enable(void) |
61 | ipl_t interrupts_enable(void) |
62 | { |
62 | { |
63 | ipl_t ipl = current_status_reg_read(); |
63 | ipl_t ipl = current_status_reg_read(); |
64 | 64 | ||
65 | current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
65 | current_status_reg_control_write(ipl | STATUS_REG_IE_ENABLED_BIT); |
66 | 66 | ||
67 | return ipl; |
67 | return ipl; |
68 | } |
68 | } |
69 | 69 | ||
70 | /** Restore interrupt priority level. |
70 | /** Restore interrupt priority level. |
71 | * |
71 | * |
72 | * @param ipl Saved interrupt priority level. |
72 | * @param ipl Saved interrupt priority level. |
73 | */ |
73 | */ |
74 | void interrupts_restore(ipl_t ipl) |
74 | void interrupts_restore(ipl_t ipl) |
75 | { |
75 | { |
76 | current_status_reg_control_write(current_status_reg_read() | |
76 | current_status_reg_control_write(current_status_reg_read() | |
77 | (ipl & STATUS_REG_IE_ENABLED_BIT)); |
77 | (ipl & STATUS_REG_IE_ENABLED_BIT)); |
78 | } |
78 | } |
79 | 79 | ||
80 | /** Read interrupt priority level. |
80 | /** Read interrupt priority level. |
81 | * |
81 | * |
82 | * @return Current interrupt priority level. |
82 | * @return Current interrupt priority level. |
83 | */ |
83 | */ |
84 | ipl_t interrupts_read(void) |
84 | ipl_t interrupts_read(void) |
85 | { |
85 | { |
86 | return current_status_reg_read(); |
86 | return current_status_reg_read(); |
87 | } |
87 | } |
88 | 88 | ||
89 | /** Initialize basic tables for exception dispatching |
89 | /** Initialize basic tables for exception dispatching |
90 | * and starts the timer. |
90 | * and starts the timer. |
91 | */ |
91 | */ |
92 | void interrupt_init(void) |
92 | void interrupt_init(void) |
93 | { |
93 | { |
94 | irq_init(IRQ_COUNT, IRQ_COUNT); |
94 | irq_init(IRQ_COUNT, IRQ_COUNT); |
95 | 95 | ||
- | 96 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
|
96 | gxemul_timer_irq_init(); |
97 | gxemul_timer_irq_init(); |
97 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
98 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
- | 99 | #endif |
|
98 | } |
100 | } |
99 | 101 | ||
100 | 102 | ||
101 | /** @} |
103 | /** @} |
102 | */ |
104 | */ |
103 | 105 |