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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | @brief Exception handlers and exception initialization routines. |
33 | @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug_print/print.h> |
37 | #include <arch/debug_print/print.h> |
38 | #include <arch/memstr.h> |
38 | #include <arch/memstr.h> |
39 | #include <arch/regutils.h> |
39 | #include <arch/regutils.h> |
40 | #include <interrupt.h> |
40 | #include <interrupt.h> |
41 | #include <arch/drivers/gxemul.h> |
41 | #include <arch/drivers/gxemul.h> |
42 | #include <arch/mm/page.h> |
42 | #include <arch/mm/page_fault.h> |
43 | 43 | ||
44 | #define PREFETCH_OFFSET 0x8 |
44 | #define PREFETCH_OFFSET 0x8 |
45 | #define BRANCH_OPCODE 0xea000000 |
45 | #define BRANCH_OPCODE 0xea000000 |
46 | #define LDR_OPCODE 0xe59ff000 |
46 | #define LDR_OPCODE 0xe59ff000 |
47 | #define VALID_BRANCH_MASK 0xff000000 |
47 | #define VALID_BRANCH_MASK 0xff000000 |
48 | #define EXC_VECTORS_SIZE 0x20 |
48 | #define EXC_VECTORS_SIZE 0x20 |
49 | #define EXC_VECTORS 0x8 |
49 | #define EXC_VECTORS 0x8 |
50 | 50 | ||
51 | 51 | ||
52 | #define SAVE_REGS_TO_STACK \ |
52 | #define SAVE_REGS_TO_STACK \ |
53 | asm("stmfd sp!, {r0-r12, sp, lr}"); \ |
53 | asm("stmfd sp!, {r0-r12, sp, lr}"); \ |
54 | asm("mrs r14, spsr"); \ |
54 | asm("mrs r14, spsr"); \ |
55 | asm("stmfd sp!, {r14}"); |
55 | asm("stmfd sp!, {r14}"); |
56 | 56 | ||
57 | #define CALL_EXC_DISPATCH(exception) \ |
57 | #define CALL_EXC_DISPATCH(exception) \ |
58 | asm("mov r0, %0" : : "i" (exception)); \ |
58 | asm("mov r0, %0" : : "i" (exception)); \ |
59 | asm("mov r1, sp"); \ |
59 | asm("mov r1, sp"); \ |
60 | asm("bl exc_dispatch"); |
60 | asm("bl exc_dispatch"); |
61 | 61 | ||
62 | /**Loads registers from the stack and resets SPSR before exitting exception |
62 | /**Loads registers from the stack and resets SPSR before exitting exception |
63 | * handler. |
63 | * handler. |
64 | */ |
64 | */ |
65 | #define LOAD_REGS_FROM_STACK \ |
65 | #define LOAD_REGS_FROM_STACK \ |
66 | asm("ldmfd sp!, {r14}"); \ |
66 | asm("ldmfd sp!, {r14}"); \ |
67 | asm("msr spsr, r14"); \ |
67 | asm("msr spsr, r14"); \ |
68 | asm("ldmfd sp!, {r0-r12, sp, pc}^"); |
68 | asm("ldmfd sp!, {r0-r12, sp, pc}^"); |
69 | 69 | ||
70 | /** General exception handler. |
70 | /** General exception handler. |
71 | * Stores registers, dispatches the exception, |
71 | * Stores registers, dispatches the exception, |
72 | * and finally restores registers and returns from exception processing. |
72 | * and finally restores registers and returns from exception processing. |
73 | */ |
73 | */ |
74 | #define PROCESS_EXCEPTION(exception) \ |
74 | #define PROCESS_EXCEPTION(exception) \ |
75 | SAVE_REGS_TO_STACK \ |
75 | SAVE_REGS_TO_STACK \ |
76 | CALL_EXC_DISPATCH(exception) \ |
76 | CALL_EXC_DISPATCH(exception) \ |
77 | LOAD_REGS_FROM_STACK |
77 | LOAD_REGS_FROM_STACK |
78 | 78 | ||
79 | /** Updates specified exception vector to jump to given handler. |
79 | /** Updates specified exception vector to jump to given handler. |
80 | * Addresses of handlers are stored in memory following exception vectors. |
80 | * Addresses of handlers are stored in memory following exception vectors. |
81 | */ |
81 | */ |
82 | static void install_handler (unsigned handler_addr, unsigned* vector) |
82 | static void install_handler (unsigned handler_addr, unsigned* vector) |
83 | { |
83 | { |
84 | /* relative address (related to exc. vector) of the word |
84 | /* relative address (related to exc. vector) of the word |
85 | * where handler's address is stored |
85 | * where handler's address is stored |
86 | */ |
86 | */ |
87 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
87 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
88 | 88 | ||
89 | /* make it LDR instruction and store at exception vector */ |
89 | /* make it LDR instruction and store at exception vector */ |
90 | *vector = handler_address_ptr | LDR_OPCODE; |
90 | *vector = handler_address_ptr | LDR_OPCODE; |
91 | 91 | ||
92 | /* store handler's address */ |
92 | /* store handler's address */ |
93 | *(vector + EXC_VECTORS) = handler_addr; |
93 | *(vector + EXC_VECTORS) = handler_addr; |
94 | } |
94 | } |
95 | 95 | ||
96 | static void reset_exception_entry() |
96 | static void reset_exception_entry() |
97 | { |
97 | { |
98 | PROCESS_EXCEPTION(EXC_RESET); |
98 | PROCESS_EXCEPTION(EXC_RESET); |
99 | } |
99 | } |
100 | 100 | ||
101 | /** Low-level Software Interrupt Exception handler */ |
101 | /** Low-level Software Interrupt Exception handler */ |
102 | static void swi_exception_entry() |
102 | static void swi_exception_entry() |
103 | { |
103 | { |
104 | PROCESS_EXCEPTION(EXC_SWI); |
104 | PROCESS_EXCEPTION(EXC_SWI); |
105 | } |
105 | } |
106 | 106 | ||
107 | /** Low-level Undefined Instruction Exception handler */ |
107 | /** Low-level Undefined Instruction Exception handler */ |
108 | static void undef_instr_exception_entry() |
108 | static void undef_instr_exception_entry() |
109 | { |
109 | { |
110 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
110 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
111 | } |
111 | } |
112 | 112 | ||
113 | /** Low-level Fast Interrupt Exception handler */ |
113 | /** Low-level Fast Interrupt Exception handler */ |
114 | static void fiq_exception_entry() |
114 | static void fiq_exception_entry() |
115 | { |
115 | { |
116 | PROCESS_EXCEPTION(EXC_FIQ); |
116 | PROCESS_EXCEPTION(EXC_FIQ); |
117 | } |
117 | } |
118 | 118 | ||
119 | /** Low-level Prefetch Abort Exception handler */ |
119 | /** Low-level Prefetch Abort Exception handler */ |
120 | static void prefetch_abort_exception_entry() |
120 | static void prefetch_abort_exception_entry() |
121 | { |
121 | { |
122 | asm("sub lr, lr, #4"); |
122 | asm("sub lr, lr, #4"); |
123 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
123 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
124 | } |
124 | } |
125 | 125 | ||
126 | /** Low-level Data Abort Exception handler */ |
126 | /** Low-level Data Abort Exception handler */ |
127 | static void data_abort_exception_entry() |
127 | static void data_abort_exception_entry() |
128 | { |
128 | { |
129 | asm("sub lr, lr, #8"); |
129 | asm("sub lr, lr, #8"); |
130 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
130 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
131 | } |
131 | } |
132 | 132 | ||
133 | 133 | ||
134 | /** Low-level Interrupt Exception handler */ |
134 | /** Low-level Interrupt Exception handler */ |
135 | static void irq_exception_entry() |
135 | static void irq_exception_entry() |
136 | { |
136 | { |
137 | asm("sub lr, lr, #4"); |
137 | asm("sub lr, lr, #4"); |
138 | PROCESS_EXCEPTION(EXC_IRQ); |
138 | PROCESS_EXCEPTION(EXC_IRQ); |
139 | } |
139 | } |
140 | 140 | ||
141 | 141 | ||
142 | /** Interrupt Exception handler. |
142 | /** Interrupt Exception handler. |
143 | * Determines the sources of interrupt, and calls their handlers. |
143 | * Determines the sources of interrupt, and calls their handlers. |
144 | */ |
144 | */ |
145 | static void irq_exception(int exc_no, istate_t* istate) |
145 | static void irq_exception(int exc_no, istate_t* istate) |
146 | { |
146 | { |
147 | // TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar |
147 | // TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar |
148 | // name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM |
148 | // name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM |
149 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
149 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
150 | uint32_t sources = gxemul_irqc_get_sources(); |
150 | uint32_t sources = gxemul_irqc_get_sources(); |
151 | int i = 0; |
151 | int i = 0; |
152 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
152 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
153 | if (sources & (1 << i)) { |
153 | if (sources & (1 << i)) { |
154 | irq_t *irq = irq_dispatch_and_lock(i); |
154 | irq_t *irq = irq_dispatch_and_lock(i); |
155 | if (irq) { |
155 | if (irq) { |
156 | /* The IRQ handler was found. */ |
156 | /* The IRQ handler was found. */ |
157 | irq->handler(irq, irq->arg); |
157 | irq->handler(irq, irq->arg); |
158 | spinlock_unlock(&irq->lock); |
158 | spinlock_unlock(&irq->lock); |
159 | } else { |
159 | } else { |
160 | /* Spurious interrupt.*/ |
160 | /* Spurious interrupt.*/ |
161 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
161 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
162 | } |
162 | } |
163 | } |
163 | } |
164 | } |
164 | } |
165 | #endif |
165 | #endif |
166 | /* TODO remove after testing the above code |
166 | /* TODO remove after testing the above code |
167 | noirq = 0; |
167 | noirq = 0; |
168 | if (i == CONSOLE_IRQ) { |
168 | if (i == CONSOLE_IRQ) { |
169 | char readchar = *(char*)0x10000000; |
169 | char readchar = *(char*)0x10000000; |
170 | if (readchar == 0) { |
170 | if (readchar == 0) { |
171 | aux_puts("?"); |
171 | aux_puts("?"); |
172 | } |
172 | } |
173 | else { |
173 | else { |
174 | dprintf("%c", readchar); |
174 | dprintf("%c", readchar); |
175 | } |
175 | } |
176 | |
176 | |
177 | } |
177 | } |
178 | else if (i == TIMER_IRQ) { |
178 | else if (i == TIMER_IRQ) { |
179 | dprintf("\n.\n"); |
179 | dprintf("\n.\n"); |
180 | //acknowledge |
180 | //acknowledge |
181 | *(uint32_t*)0x15000110 = 0; |
181 | *(uint32_t*)0x15000110 = 0; |
182 | } |
182 | } |
183 | } |
183 | } |
184 | } |
184 | } |
185 | 185 | ||
186 | if (noirq) |
186 | if (noirq) |
187 | aux_puts("IRQ exception without source\n");*/ |
187 | aux_puts("IRQ exception without source\n");*/ |
188 | } |
188 | } |
189 | 189 | ||
190 | /** Fills exception vectors with appropriate exception handlers. |
190 | /** Fills exception vectors with appropriate exception handlers. |
191 | */ |
191 | */ |
192 | void install_exception_handlers(void) |
192 | void install_exception_handlers(void) |
193 | { |
193 | { |
194 | install_handler((unsigned)reset_exception_entry, |
194 | install_handler((unsigned)reset_exception_entry, |
195 | (unsigned*)EXC_RESET_VEC); |
195 | (unsigned*)EXC_RESET_VEC); |
196 | 196 | ||
197 | install_handler((unsigned)undef_instr_exception_entry, |
197 | install_handler((unsigned)undef_instr_exception_entry, |
198 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
198 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
199 | 199 | ||
200 | install_handler((unsigned)swi_exception_entry, |
200 | install_handler((unsigned)swi_exception_entry, |
201 | (unsigned*)EXC_SWI_VEC); |
201 | (unsigned*)EXC_SWI_VEC); |
202 | 202 | ||
203 | install_handler((unsigned)prefetch_abort_exception_entry, |
203 | install_handler((unsigned)prefetch_abort_exception_entry, |
204 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
204 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
205 | 205 | ||
206 | install_handler((unsigned)data_abort_exception_entry, |
206 | install_handler((unsigned)data_abort_exception_entry, |
207 | (unsigned*)EXC_DATA_ABORT_VEC); |
207 | (unsigned*)EXC_DATA_ABORT_VEC); |
208 | 208 | ||
209 | install_handler((unsigned)irq_exception_entry, |
209 | install_handler((unsigned)irq_exception_entry, |
210 | (unsigned*)EXC_IRQ_VEC); |
210 | (unsigned*)EXC_IRQ_VEC); |
211 | 211 | ||
212 | install_handler((unsigned)fiq_exception_entry, |
212 | install_handler((unsigned)fiq_exception_entry, |
213 | (unsigned*)EXC_FIQ_VEC); |
213 | (unsigned*)EXC_FIQ_VEC); |
214 | } |
214 | } |
215 | 215 | ||
216 | /** Activates using high exception vectors addresses. */ |
216 | /** Activates using high exception vectors addresses. */ |
217 | static void high_vectors() |
217 | static void high_vectors() |
218 | { |
218 | { |
219 | uint32_t control_reg; |
219 | uint32_t control_reg; |
220 | 220 | ||
221 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
221 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
222 | 222 | ||
223 | //switch on the high vectors bit |
223 | //switch on the high vectors bit |
224 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
224 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
225 | 225 | ||
226 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
226 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
227 | } |
227 | } |
228 | 228 | ||
229 | 229 | ||
230 | /** Initializes exception handling. |
230 | /** Initializes exception handling. |
231 | * |
231 | * |
232 | * Installs low-level exception handlers and then registers |
232 | * Installs low-level exception handlers and then registers |
233 | * exceptions and their handlers to kernel exception dispatcher. |
233 | * exceptions and their handlers to kernel exception dispatcher. |
234 | */ |
234 | */ |
235 | void exception_init(void) |
235 | void exception_init(void) |
236 | { |
236 | { |
237 | #ifdef HIGH_EXCEPTION_VECTORS |
237 | #ifdef HIGH_EXCEPTION_VECTORS |
238 | high_vectors(); |
238 | high_vectors(); |
239 | #endif |
239 | #endif |
240 | 240 | ||
241 | install_exception_handlers(); |
241 | install_exception_handlers(); |
242 | 242 | ||
243 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
243 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
244 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
244 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
245 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
245 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
246 | /* TODO add next */ |
246 | /* TODO add next */ |
247 | } |
247 | } |
248 | 248 | ||
249 | /* TODO change soon, temporary hack. */ |
249 | /* TODO change soon, temporary hack. */ |
250 | void setup_exception_stacks() |
250 | void setup_exception_stacks() |
251 | { |
251 | { |
252 | /* switch to particular mode and set "sp" there */ |
252 | /* switch to particular mode and set "sp" there */ |
253 | 253 | ||
254 | uint32_t cspr = current_status_reg_read(); |
254 | uint32_t cspr = current_status_reg_read(); |
255 | 255 | ||
256 | /* IRQ stack */ |
256 | /* IRQ stack */ |
257 | current_status_reg_control_write( |
257 | current_status_reg_control_write( |
258 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
258 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
259 | ); |
259 | ); |
260 | asm("ldr sp, =irq_stack"); |
260 | asm("ldr sp, =irq_stack"); |
261 | 261 | ||
262 | /* abort stack */ |
262 | /* abort stack */ |
263 | current_status_reg_control_write( |
263 | current_status_reg_control_write( |
264 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
264 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
265 | ); |
265 | ); |
266 | asm("ldr sp, =abort_stack"); |
266 | asm("ldr sp, =abort_stack"); |
267 | 267 | ||
268 | /* TODO if you want to test other exceptions than IRQ, |
268 | /* TODO if you want to test other exceptions than IRQ, |
269 | make stack analogous to irq_stack (in start.S), |
269 | make stack analogous to irq_stack (in start.S), |
270 | and then set stack pointer here */ |
270 | and then set stack pointer here */ |
271 | 271 | ||
272 | current_status_reg_control_write( cspr); |
272 | current_status_reg_control_write( cspr); |
273 | 273 | ||
274 | } |
274 | } |
275 | 275 | ||
276 | /** @} |
276 | /** @} |
277 | */ |
277 | */ |
278 | 278 |