WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Exception handlers and exception initialization routines.
 */
 
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <print.h>
#include <syscall/syscall.h>
 
/** Offset used in calculation of exception handler's relative address.
 *
 * @see install_handler()
 */
#define PREFETCH_OFFSET      0x8
 
/** LDR instruction's code */
#define LDR_OPCODE           0xe59ff000
 
/** Number of exception vectors. */
#define EXC_VECTORS          8
 
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
 
 
/** Switches to kernel stack and saves all registers there.
 *
 * Temporary exception stack is used to save a few registers
 * before stack switch takes place.
 */
inline static void setup_stack_and_save_regs()
{
asm volatile("ldr r13, =exc_stack       \n\
    stmfd r13!, {r0}            \n\
    mrs r0, spsr                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 1f                  \n\
                        \n\
    @prev mode was usermode         \n\
    ldmfd r13!, {r0}            \n\
    ldr r13, =supervisor_sp         \n\
    ldr r13, [r13]              \n\
    stmfd r13!, {lr}            \n\
    stmfd r13!, {r0-r12}            \n\
    stmfd r13!, {r13, lr}^          \n\
    mrs r0, spsr                \n\
    stmfd r13!, {r0}            \n\
    b 2f                    \n\
                        \n\
    @prev mode was not usermode     \n\
1:                      \n\
    stmfd r13!, {r1, r2, r3}        \n\
    mrs r1, cpsr                \n\
    mov r2, lr              \n\
    bic r1, r1, #0x1f           \n\
    orr r1, r1, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r1              \n\
                        \n\
    mov r3, r13             \n\
    stmfd r13!, {r2}            \n\
    mov r2, lr              \n\
    stmfd r13!, {r4-r12}            \n\
    mov r1, r13             \n\
    @following two lines are for debugging  \n\
    mov sp, #0              \n\
    mov lr, #0              \n\
    msr cpsr_c, r0              \n\
                        \n\
    ldmfd r13!, {r4, r5, r6, r7}        \n\
    stmfd r1!, {r4, r5, r6}         \n\
    stmfd r1!, {r7}             \n\
    stmfd r1!, {r2}             \n\
    stmfd r1!, {r3}             \n\
    mrs r0, spsr                \n\
    stmfd r1!, {r0}             \n\
    mov r13, r1             \n\
2:"
);
}
 
 
/** Returns from exception mode.
 *
 * Previously saved state of registers (including control register)
 * is restored from the stack.
 */
inline static void load_regs()
{
asm volatile(   "ldmfd r13!, {r0}       \n\
    msr spsr, r0                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 3f                  \n\
                        \n\
    @return to user mode            \n\
    ldmfd r13!, {r13, lr}^          \n\
    b 4f                    \n\
                        \n\
    @return to non-user mode        \n\
3:                      \n\
    ldmfd r13!, {r1, r2}            \n\
    mrs r3, cpsr                \n\
    bic r3, r3, #0x1f           \n\
    orr r3, r3, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r3              \n\
                        \n\
    mov r13, r1             \n\
    mov lr, r2              \n\
    msr cpsr_c, r0              \n\
                        \n\
    @actual return              \n\
4:  ldmfd r13, {r0-r12, pc}^"
);
}
 
 
/** Switch CPU to mode in which interrupts are serviced (currently it
 * is Undefined mode).
 *
 * The default mode for interrupt servicing (Interrupt Mode)
 * can not be used because of nested interrupts (which can occur
 * because interrupt are enabled in higher levels of interrupt handler).
 */
inline static void switch_to_irq_servicing_mode()
{
    /* switch to Undefined mode */
    asm volatile(
        /* save regs used during switching */
        "stmfd sp!, {r0-r3}     \n"
 
        /* save stack pointer and link register to r1, r2 */
        "mov r1, sp         \n"
        "mov r2, lr         \n"
 
        /* mode switch */
        "mrs r0, cpsr           \n"
        "bic r0, r0, #0x1f      \n"
        "orr r0, r0, #0x1b      \n"
        "msr cpsr_c, r0         \n"
 
        /* restore saved sp and lr */
        "mov sp, r1         \n"
        "mov lr, r2         \n"
 
        /* restore original regs */
        "ldmfd sp!, {r0-r3}     \n"
    );
}
 
 
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
 
/** General exception handler.
 *
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
 
/** Updates specified exception vector to jump to given handler.
 *
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler.
 *
 * CPU is switched to Undefined mode before further interrupt processing
 * because of possible occurence of nested interrupt exception, which
 * would overwrite (and thus spoil) stack pointer.
 */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
   
    switch_to_irq_servicing_mode();
   
    CALL_EXC_DISPATCH(EXC_IRQ)
 
    load_regs();
}
 
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    /*
    dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
        istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
    */
 
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
}
 
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
}
 
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
 
/** @}
 */
 

Rev 2411	Rev 2414
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Exception handlers and exception initialization routines.	33	* @brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36		36
37	#include <arch/exception.h>	37	#include <arch/exception.h>
38	#include <arch/debug/print.h>	38	#include <arch/debug/print.h>
39	#include <arch/memstr.h>	39	#include <arch/memstr.h>
40	#include <arch/regutils.h>	40	#include <arch/regutils.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42	#include <arch/machine.h>	42	#include <arch/machine.h>
43	#include <arch/mm/page_fault.h>	43	#include <arch/mm/page_fault.h>
44	#include <print.h>	44	#include <print.h>
45	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
46		46
47	/** Offset used in calculation of exception handler's relative address.	47	/** Offset used in calculation of exception handler's relative address.
48	*	48	*
49	* @see install_handler()	49	* @see install_handler()
50	*/	50	*/
51	#define PREFETCH_OFFSET 0x8	51	#define PREFETCH_OFFSET 0x8
52		52
53	/** LDR instruction's code */	53	/** LDR instruction's code */
54	#define LDR_OPCODE 0xe59ff000	54	#define LDR_OPCODE 0xe59ff000
55		55
56	/** Number of exception vectors. */	56	/** Number of exception vectors. */
57	#define EXC_VECTORS 8	57	#define EXC_VECTORS 8
58		58
59	/** Size of memory block occupied by exception vectors. */	59	/** Size of memory block occupied by exception vectors. */
60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)	60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
61		61
62		62
63	/** Switches to kernel stack and saves all registers there.	63	/** Switches to kernel stack and saves all registers there.
64	*	64	*
65	* Temporary exception stack is used to save a few registers	65	* Temporary exception stack is used to save a few registers
66	* before stack switch takes place.	66	* before stack switch takes place.
67	*/	67	*/
68	inline static void setup_stack_and_save_regs()	68	inline static void setup_stack_and_save_regs()
69	{	69	{
70	asm volatile("ldr r13, =exc_stack \n\	70	asm volatile("ldr r13, =exc_stack \n\
71	stmfd r13!, {r0} \n\	71	stmfd r13!, {r0} \n\
72	mrs r0, spsr \n\	72	mrs r0, spsr \n\
73	and r0, r0, #0x1f \n\	73	and r0, r0, #0x1f \n\
74	cmp r0, #0x10 \n\	74	cmp r0, #0x10 \n\
75	bne 1f \n\	75	bne 1f \n\
76	\n\	76	\n\
77	@prev mode was usermode \n\	77	@prev mode was usermode \n\
78	ldmfd r13!, {r0} \n\	78	ldmfd r13!, {r0} \n\
79	ldr r13, =supervisor_sp \n\	79	ldr r13, =supervisor_sp \n\
80	ldr r13, [r13] \n\	80	ldr r13, [r13] \n\
81	stmfd r13!, {lr} \n\	81	stmfd r13!, {lr} \n\
82	stmfd r13!, {r0-r12} \n\	82	stmfd r13!, {r0-r12} \n\
83	stmfd r13!, {r13, lr}^ \n\	83	stmfd r13!, {r13, lr}^ \n\
84	mrs r0, spsr \n\	84	mrs r0, spsr \n\
85	stmfd r13!, {r0} \n\	85	stmfd r13!, {r0} \n\
86	b 2f \n\	86	b 2f \n\
87	\n\	87	\n\
88	@prev mode was not usermode \n\	88	@prev mode was not usermode \n\
89	1: \n\	89	1: \n\
90	stmfd r13!, {r1, r2, r3} \n\	90	stmfd r13!, {r1, r2, r3} \n\
91	mrs r1, cpsr \n\	91	mrs r1, cpsr \n\
92	mov r2, lr \n\	92	mov r2, lr \n\
93	bic r1, r1, #0x1f \n\	93	bic r1, r1, #0x1f \n\
94	orr r1, r1, r0 \n\	94	orr r1, r1, r0 \n\
95	mrs r0, cpsr \n\	95	mrs r0, cpsr \n\
96	msr cpsr_c, r1 \n\	96	msr cpsr_c, r1 \n\
97	\n\	97	\n\
98	mov r3, r13 \n\	98	mov r3, r13 \n\
99	stmfd r13!, {r2} \n\	99	stmfd r13!, {r2} \n\
100	mov r2, lr \n\	100	mov r2, lr \n\
101	stmfd r13!, {r4-r12} \n\	101	stmfd r13!, {r4-r12} \n\
102	mov r1, r13 \n\	102	mov r1, r13 \n\
103	@following two lines are for debugging \n\	103	@following two lines are for debugging \n\
104	mov sp, #0 \n\	104	mov sp, #0 \n\
105	mov lr, #0 \n\	105	mov lr, #0 \n\
106	msr cpsr_c, r0 \n\	106	msr cpsr_c, r0 \n\
107	\n\	107	\n\
108	ldmfd r13!, {r4, r5, r6, r7} \n\	108	ldmfd r13!, {r4, r5, r6, r7} \n\
109	stmfd r1!, {r4, r5, r6} \n\	109	stmfd r1!, {r4, r5, r6} \n\
110	stmfd r1!, {r7} \n\	110	stmfd r1!, {r7} \n\
111	stmfd r1!, {r2} \n\	111	stmfd r1!, {r2} \n\
112	stmfd r1!, {r3} \n\	112	stmfd r1!, {r3} \n\
113	mrs r0, spsr \n\	113	mrs r0, spsr \n\
114	stmfd r1!, {r0} \n\	114	stmfd r1!, {r0} \n\
115	mov r13, r1 \n\	115	mov r13, r1 \n\
116	2:"	116	2:"
117	);	117	);
118	}	118	}
119		119
120		120
121	/** Returns from exception mode.	121	/** Returns from exception mode.
122	*	122	*
123	* Previously saved state of registers (including control register)	123	* Previously saved state of registers (including control register)
124	* is restored from the stack.	124	* is restored from the stack.
125	*/	125	*/
126	inline static void load_regs()	126	inline static void load_regs()
127	{	127	{
128	asm volatile( "ldmfd r13!, {r0} \n\	128	asm volatile( "ldmfd r13!, {r0} \n\
129	msr spsr, r0 \n\	129	msr spsr, r0 \n\
130	and r0, r0, #0x1f \n\	130	and r0, r0, #0x1f \n\
131	cmp r0, #0x10 \n\	131	cmp r0, #0x10 \n\
132	bne 3f \n\	132	bne 3f \n\
133	\n\	133	\n\
134	@return to user mode \n\	134	@return to user mode \n\
135	ldmfd r13!, {r13, lr}^ \n\	135	ldmfd r13!, {r13, lr}^ \n\
136	b 4f \n\	136	b 4f \n\
137	\n\	137	\n\
138	@return to non-user mode \n\	138	@return to non-user mode \n\
139	3: \n\	139	3: \n\
140	ldmfd r13!, {r1, r2} \n\	140	ldmfd r13!, {r1, r2} \n\
141	mrs r3, cpsr \n\	141	mrs r3, cpsr \n\
142	bic r3, r3, #0x1f \n\	142	bic r3, r3, #0x1f \n\
143	orr r3, r3, r0 \n\	143	orr r3, r3, r0 \n\
144	mrs r0, cpsr \n\	144	mrs r0, cpsr \n\
145	msr cpsr_c, r3 \n\	145	msr cpsr_c, r3 \n\
146	\n\	146	\n\
147	mov r13, r1 \n\	147	mov r13, r1 \n\
148	mov lr, r2 \n\	148	mov lr, r2 \n\
149	msr cpsr_c, r0 \n\	149	msr cpsr_c, r0 \n\
150	\n\	150	\n\
151	@actual return \n\	151	@actual return \n\
152	4: ldmfd r13, {r0-r12, pc}^"	152	4: ldmfd r13, {r0-r12, pc}^"
153	);	153	);
154	}	154	}
155		155
156		156
157	/** Switch CPU to mode in which interrupts are serviced (currently it	157	/** Switch CPU to mode in which interrupts are serviced (currently it
158	* is Undefined mode).	158	* is Undefined mode).
159	*	159	*
160	* The default mode for interrupt servicing (Interrupt Mode)	160	* The default mode for interrupt servicing (Interrupt Mode)
161	* can not be used because of nested interrupts (which can occur	161	* can not be used because of nested interrupts (which can occur
162	* because interrupt are enabled in higher levels of interrupt handler).	162	* because interrupt are enabled in higher levels of interrupt handler).
163	*/	163	*/
164	inline static void switchToIrqServicingMode()	164	inline static void switch_to_irq_servicing_mode()
165	{	165	{
166	/* switch to Undefined mode */	166	/* switch to Undefined mode */
167	asm volatile(	167	asm volatile(
168	/* save regs used during switching */	168	/* save regs used during switching */
169	"stmfd sp!, {r0-r3} \n"	169	"stmfd sp!, {r0-r3} \n"
170		170
171	/* save stack pointer and link register to r1, r2 */	171	/* save stack pointer and link register to r1, r2 */
172	"mov r1, sp \n"	172	"mov r1, sp \n"
173	"mov r2, lr \n"	173	"mov r2, lr \n"
174		174
175	/* mode switch */	175	/* mode switch */
176	"mrs r0, cpsr \n"	176	"mrs r0, cpsr \n"
177	"bic r0, r0, #0x1f \n"	177	"bic r0, r0, #0x1f \n"
178	"orr r0, r0, #0x1b \n"	178	"orr r0, r0, #0x1b \n"
179	"msr cpsr_c, r0 \n"	179	"msr cpsr_c, r0 \n"
180		180
181	/* restore saved sp and lr */	181	/* restore saved sp and lr */
182	"mov sp, r1 \n"	182	"mov sp, r1 \n"
183	"mov lr, r2 \n"	183	"mov lr, r2 \n"
184		184
185	/* restore original regs */	185	/* restore original regs */
186	"ldmfd sp!, {r0-r3} \n"	186	"ldmfd sp!, {r0-r3} \n"
187	);	187	);
188	}	188	}
189		189
190		190
191	/** Calls exception dispatch routine. */	191	/** Calls exception dispatch routine. */
192	#define CALL_EXC_DISPATCH(exception) \	192	#define CALL_EXC_DISPATCH(exception) \
193	asm("mov r0, %0" : : "i" (exception)); \	193	asm("mov r0, %0" : : "i" (exception)); \
194	asm("mov r1, r13"); \	194	asm("mov r1, r13"); \
195	asm("bl exc_dispatch");	195	asm("bl exc_dispatch");
196		196
197		197
198	/** General exception handler.	198	/** General exception handler.
199	*	199	*
200	* Stores registers, dispatches the exception,	200	* Stores registers, dispatches the exception,
201	* and finally restores registers and returns from exception processing.	201	* and finally restores registers and returns from exception processing.
202	*	202	*
203	* @param exception Exception number.	203	* @param exception Exception number.
204	*/	204	*/
205	#define PROCESS_EXCEPTION(exception) \	205	#define PROCESS_EXCEPTION(exception) \
206	setup_stack_and_save_regs(); \	206	setup_stack_and_save_regs(); \
207	CALL_EXC_DISPATCH(exception) \	207	CALL_EXC_DISPATCH(exception) \
208	load_regs();	208	load_regs();
209		209
210		210
211	/** Updates specified exception vector to jump to given handler.	211	/** Updates specified exception vector to jump to given handler.
212	*	212	*
213	* Addresses of handlers are stored in memory following exception vectors.	213	* Addresses of handlers are stored in memory following exception vectors.
214	*/	214	*/
215	static void install_handler (unsigned handler_addr, unsigned* vector)	215	static void install_handler (unsigned handler_addr, unsigned* vector)
216	{	216	{
217	/* relative address (related to exc. vector) of the word	217	/* relative address (related to exc. vector) of the word
218	* where handler's address is stored	218	* where handler's address is stored
219	*/	219	*/
220	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	220	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
221		221
222	/* make it LDR instruction and store at exception vector */	222	/* make it LDR instruction and store at exception vector */
223	*vector = handler_address_ptr \| LDR_OPCODE;	223	*vector = handler_address_ptr \| LDR_OPCODE;
224		224
225	/* store handler's address */	225	/* store handler's address */
226	*(vector + EXC_VECTORS) = handler_addr;	226	*(vector + EXC_VECTORS) = handler_addr;
227		227
228	}	228	}
229		229
230		230
231	/** Low-level Reset Exception handler. */	231	/** Low-level Reset Exception handler. */
232	static void reset_exception_entry()	232	static void reset_exception_entry()
233	{	233	{
234	PROCESS_EXCEPTION(EXC_RESET);	234	PROCESS_EXCEPTION(EXC_RESET);
235	}	235	}
236		236
237		237
238	/** Low-level Software Interrupt Exception handler. */	238	/** Low-level Software Interrupt Exception handler. */
239	static void swi_exception_entry()	239	static void swi_exception_entry()
240	{	240	{
241	PROCESS_EXCEPTION(EXC_SWI);	241	PROCESS_EXCEPTION(EXC_SWI);
242	}	242	}
243		243
244		244
245	/** Low-level Undefined Instruction Exception handler. */	245	/** Low-level Undefined Instruction Exception handler. */
246	static void undef_instr_exception_entry()	246	static void undef_instr_exception_entry()
247	{	247	{
248	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	248	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
249	}	249	}
250		250
251		251
252	/** Low-level Fast Interrupt Exception handler. */	252	/** Low-level Fast Interrupt Exception handler. */
253	static void fiq_exception_entry()	253	static void fiq_exception_entry()
254	{	254	{
255	PROCESS_EXCEPTION(EXC_FIQ);	255	PROCESS_EXCEPTION(EXC_FIQ);
256	}	256	}
257		257
258		258
259	/** Low-level Prefetch Abort Exception handler. */	259	/** Low-level Prefetch Abort Exception handler. */
260	static void prefetch_abort_exception_entry()	260	static void prefetch_abort_exception_entry()
261	{	261	{
262	asm("sub lr, lr, #4");	262	asm("sub lr, lr, #4");
263	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	263	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
264	}	264	}
265		265
266		266
267	/** Low-level Data Abort Exception handler. */	267	/** Low-level Data Abort Exception handler. */
268	static void data_abort_exception_entry()	268	static void data_abort_exception_entry()
269	{	269	{
270	asm("sub lr, lr, #8");	270	asm("sub lr, lr, #8");
271	PROCESS_EXCEPTION(EXC_DATA_ABORT);	271	PROCESS_EXCEPTION(EXC_DATA_ABORT);
272	}	272	}
273		273
274		274
275	/** Low-level Interrupt Exception handler.	275	/** Low-level Interrupt Exception handler.
276	*	276	*
277	* CPU is switched to Undefined mode before further interrupt processing	277	* CPU is switched to Undefined mode before further interrupt processing
278	* because of possible occurence of nested interrupt exception, which	278	* because of possible occurence of nested interrupt exception, which
279	* would overwrite (and thus spoil) stack pointer.	279	* would overwrite (and thus spoil) stack pointer.
280	*/	280	*/
281	static void irq_exception_entry()	281	static void irq_exception_entry()
282	{	282	{
283	asm("sub lr, lr, #4");	283	asm("sub lr, lr, #4");
284	setup_stack_and_save_regs();	284	setup_stack_and_save_regs();
285		285
286	switchToIrqServicingMode();	286	switch_to_irq_servicing_mode();
287		287
288	CALL_EXC_DISPATCH(EXC_IRQ)	288	CALL_EXC_DISPATCH(EXC_IRQ)
289		289
290	load_regs();	290	load_regs();
291	}	291	}
292		292
293		293
294	/** Software Interrupt handler.	294	/** Software Interrupt handler.
295	*	295	*
296	* Dispatches the syscall.	296	* Dispatches the syscall.
297	*/	297	*/
298	static void swi_exception(int exc_no, istate_t *istate)	298	static void swi_exception(int exc_no, istate_t *istate)
299	{	299	{
300	/*	300	/*
301	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,	301	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
302	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);	302	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
303	*/	303	*/
304		304
305	istate->r0 = syscall_handler(	305	istate->r0 = syscall_handler(
306	istate->r0,	306	istate->r0,
307	istate->r1,	307	istate->r1,
308	istate->r2,	308	istate->r2,
309	istate->r3,	309	istate->r3,
310	istate->r4);	310	istate->r4);
311	}	311	}
312		312
313		313
314	/** Interrupt Exception handler.	314	/** Interrupt Exception handler.
315	*	315	*
316	* Determines the sources of interrupt, and calls their handlers.	316	* Determines the sources of interrupt, and calls their handlers.
317	*/	317	*/
318	static void irq_exception(int exc_no, istate_t *istate)	318	static void irq_exception(int exc_no, istate_t *istate)
319	{	319	{
320	machine_irq_exception(exc_no, istate);	320	machine_irq_exception(exc_no, istate);
321	}	321	}
322		322
323		323
324	/** Fills exception vectors with appropriate exception handlers. */	324	/** Fills exception vectors with appropriate exception handlers. */
325	void install_exception_handlers(void)	325	void install_exception_handlers(void)
326	{	326	{
327	install_handler((unsigned)reset_exception_entry,	327	install_handler((unsigned)reset_exception_entry,
328	(unsigned*)EXC_RESET_VEC);	328	(unsigned*)EXC_RESET_VEC);
329		329
330	install_handler((unsigned)undef_instr_exception_entry,	330	install_handler((unsigned)undef_instr_exception_entry,
331	(unsigned*)EXC_UNDEF_INSTR_VEC);	331	(unsigned*)EXC_UNDEF_INSTR_VEC);
332		332
333	install_handler((unsigned)swi_exception_entry,	333	install_handler((unsigned)swi_exception_entry,
334	(unsigned*)EXC_SWI_VEC);	334	(unsigned*)EXC_SWI_VEC);
335		335
336	install_handler((unsigned)prefetch_abort_exception_entry,	336	install_handler((unsigned)prefetch_abort_exception_entry,
337	(unsigned*)EXC_PREFETCH_ABORT_VEC);	337	(unsigned*)EXC_PREFETCH_ABORT_VEC);
338		338
339	install_handler((unsigned)data_abort_exception_entry,	339	install_handler((unsigned)data_abort_exception_entry,
340	(unsigned*)EXC_DATA_ABORT_VEC);	340	(unsigned*)EXC_DATA_ABORT_VEC);
341		341
342	install_handler((unsigned)irq_exception_entry,	342	install_handler((unsigned)irq_exception_entry,
343	(unsigned*)EXC_IRQ_VEC);	343	(unsigned*)EXC_IRQ_VEC);
344		344
345	install_handler((unsigned)fiq_exception_entry,	345	install_handler((unsigned)fiq_exception_entry,
346	(unsigned*)EXC_FIQ_VEC);	346	(unsigned*)EXC_FIQ_VEC);
347	}	347	}
348		348
349		349
350	#ifdef HIGH_EXCEPTION_VECTORS	350	#ifdef HIGH_EXCEPTION_VECTORS
351	/** Activates use of high exception vectors addresses. */	351	/** Activates use of high exception vectors addresses. */
352	static void high_vectors()	352	static void high_vectors()
353	{	353	{
354	uint32_t control_reg;	354	uint32_t control_reg;
355		355
356	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	356	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
357		357
358	//switch on the high vectors bit	358	//switch on the high vectors bit
359	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	359	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
360		360
361	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	361	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
362	}	362	}
363	#endif	363	#endif
364		364
365		365
366	/** Initializes exception handling.	366	/** Initializes exception handling.
367	*	367	*
368	* Installs low-level exception handlers and then registers	368	* Installs low-level exception handlers and then registers
369	* exceptions and their handlers to kernel exception dispatcher.	369	* exceptions and their handlers to kernel exception dispatcher.
370	*/	370	*/
371	void exception_init(void)	371	void exception_init(void)
372	{	372	{
373	#ifdef HIGH_EXCEPTION_VECTORS	373	#ifdef HIGH_EXCEPTION_VECTORS
374	high_vectors();	374	high_vectors();
375	#endif	375	#endif
376	install_exception_handlers();	376	install_exception_handlers();
377		377
378	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	378	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
379	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);	379	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
380	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	380	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
381	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	381	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
382	}	382	}
383		383
384		384
385	/** Prints #istate_t structure content.	385	/** Prints #istate_t structure content.
386	*	386	*
387	* @param istate Structure to be printed.	387	* @param istate Structure to be printed.
388	*/	388	*/
389	void print_istate(istate_t *istate)	389	void print_istate(istate_t *istate)
390	{	390	{
391	dprintf("istate dump:\n");	391	dprintf("istate dump:\n");
392		392
393	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	393	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
394	istate->r0, istate->r1, istate->r2, istate->r3);	394	istate->r0, istate->r1, istate->r2, istate->r3);
395	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	395	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
396	istate->r4, istate->r5, istate->r6, istate->r7);	396	istate->r4, istate->r5, istate->r6, istate->r7);
397	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	397	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
398	istate->r8, istate->r9, istate->r10, istate->r11);	398	istate->r8, istate->r9, istate->r10, istate->r11);
399	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	399	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
400	istate->r12, istate->sp, istate->lr, istate->spsr);	400	istate->r12, istate->sp, istate->lr, istate->spsr);
401		401
402	dprintf(" pc: %x\n", istate->pc);	402	dprintf(" pc: %x\n", istate->pc);
403	}	403	}
404		404
405		405
406	/** @}	406	/** @}
407	*/	407	*/
408		408

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(root)/branches/arm/kernel/arch/arm32/src/exception.c @ 2464 – Rev 2411 → 2414