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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | @brief Exception handlers and exception initialization routines. |
33 | @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | 36 | ||
37 | #include <arch/exception.h> |
37 | #include <arch/exception.h> |
38 | #include <arch/debug/print.h> |
38 | #include <arch/debug/print.h> |
39 | #include <arch/memstr.h> |
39 | #include <arch/memstr.h> |
40 | #include <arch/regutils.h> |
40 | #include <arch/regutils.h> |
41 | #include <interrupt.h> |
41 | #include <interrupt.h> |
42 | #include <arch/machine.h> |
42 | #include <arch/machine.h> |
43 | #include <arch/mm/page_fault.h> |
43 | #include <arch/mm/page_fault.h> |
44 | #include <print.h> |
44 | #include <print.h> |
45 | #include <syscall/syscall.h> |
45 | #include <syscall/syscall.h> |
46 | 46 | ||
47 | 47 | ||
48 | #define PREFETCH_OFFSET 0x8 |
48 | #define PREFETCH_OFFSET 0x8 |
49 | #define BRANCH_OPCODE 0xea000000 |
49 | #define BRANCH_OPCODE 0xea000000 |
50 | #define LDR_OPCODE 0xe59ff000 |
50 | #define LDR_OPCODE 0xe59ff000 |
51 | #define VALID_BRANCH_MASK 0xff000000 |
51 | #define VALID_BRANCH_MASK 0xff000000 |
52 | #define EXC_VECTORS_SIZE 0x20 |
52 | #define EXC_VECTORS_SIZE 0x20 |
53 | #define EXC_VECTORS 0x8 |
53 | #define EXC_VECTORS 0x8 |
54 | 54 | ||
55 | 55 | ||
56 | extern uintptr_t supervisor_sp; |
56 | extern uintptr_t supervisor_sp; |
57 | extern uintptr_t exc_stack; |
57 | extern uintptr_t exc_stack; |
58 | 58 | ||
- | 59 | /** Switches to kernel stack and saves all registers there. |
|
59 | 60 | * |
|
- | 61 | * Temporary exception stack is used to save a few registers |
|
- | 62 | * before stack switch takes place. |
|
- | 63 | */ |
|
60 | inline static void setup_stack_and_save_regs() |
64 | inline static void setup_stack_and_save_regs() |
61 | { |
65 | { |
62 | /* |
- | |
63 | - | ||
64 | str r0, =exc_stack |
- | |
65 | str r1, =exc_stack + 4 |
- | |
66 | mrs r0, cpsr |
- | |
67 | mrs r1, spsr |
- | |
68 | and r0, r0, #0x1f |
- | |
69 | and r1, r1, #0x1f |
- | |
70 | cmp r0, r1 |
- | |
71 | be 3f |
- | |
72 | @different exception mode => preserve sp |
- | |
73 | ldr r1, [=exc_stack + 4] |
- | |
74 | ldr r0, [=exc_stack] |
- | |
75 | - | ||
76 | 3: |
- | |
77 | mrs r0, spsr |
- | |
78 | stmfd sp!, {r0, sp, lr} |
- | |
79 | */ |
- | |
80 | - | ||
81 | asm volatile("ldr r13, =exc_stack \n\ |
66 | asm volatile("ldr r13, =exc_stack \n\ |
82 | stmfd r13!, {r0} \n\ |
67 | stmfd r13!, {r0} \n\ |
83 | mrs r0, spsr \n\ |
68 | mrs r0, spsr \n\ |
84 | and r0, r0, #0x1f \n\ |
69 | and r0, r0, #0x1f \n\ |
85 | cmp r0, #0x10 \n\ |
70 | cmp r0, #0x10 \n\ |
86 | bne 1f \n\ |
71 | bne 1f \n\ |
87 | \n\ |
72 | \n\ |
88 | @prev mode was usermode \n\ |
73 | @prev mode was usermode \n\ |
89 | ldmfd r13!, {r0} \n\ |
74 | ldmfd r13!, {r0} \n\ |
90 | ldr r13, =supervisor_sp \n\ |
75 | ldr r13, =supervisor_sp \n\ |
91 | ldr r13, [r13] \n\ |
76 | ldr r13, [r13] \n\ |
92 | stmfd r13!, {lr} \n\ |
77 | stmfd r13!, {lr} \n\ |
93 | stmfd r13!, {r0-r12} \n\ |
78 | stmfd r13!, {r0-r12} \n\ |
94 | stmfd r13!, {r13, lr}^ \n\ |
79 | stmfd r13!, {r13, lr}^ \n\ |
95 | mrs r0, spsr \n\ |
80 | mrs r0, spsr \n\ |
96 | stmfd r13!, {r0} \n\ |
81 | stmfd r13!, {r0} \n\ |
97 | b 2f \n\ |
82 | b 2f \n\ |
98 | \n\ |
83 | \n\ |
99 | @prev mode was not usermode \n\ |
84 | @prev mode was not usermode \n\ |
100 | 1: \n\ |
85 | 1: \n\ |
101 | stmfd r13!, {r1, r2, r3} \n\ |
86 | stmfd r13!, {r1, r2, r3} \n\ |
102 | mrs r1, cpsr \n\ |
87 | mrs r1, cpsr \n\ |
103 | mov r2, lr \n\ |
88 | mov r2, lr \n\ |
104 | bic r1, r1, #0x1f \n\ |
89 | bic r1, r1, #0x1f \n\ |
105 | orr r1, r1, r0 \n\ |
90 | orr r1, r1, r0 \n\ |
106 | mrs r0, cpsr \n\ |
91 | mrs r0, cpsr \n\ |
107 | msr cpsr_c, r1 \n\ |
92 | msr cpsr_c, r1 \n\ |
108 | \n\ |
93 | \n\ |
109 | mov r3, r13 \n\ |
94 | mov r3, r13 \n\ |
110 | stmfd r13!, {r2} \n\ |
95 | stmfd r13!, {r2} \n\ |
111 | mov r2, lr \n\ |
96 | mov r2, lr \n\ |
112 | stmfd r13!, {r4-r12} \n\ |
97 | stmfd r13!, {r4-r12} \n\ |
113 | mov r1, r13 \n\ |
98 | mov r1, r13 \n\ |
114 | @following two lines are for debugging \n\ |
99 | @following two lines are for debugging \n\ |
115 | mov sp, #0 \n\ |
100 | mov sp, #0 \n\ |
116 | mov lr, #0 \n\ |
101 | mov lr, #0 \n\ |
117 | msr cpsr_c, r0 \n\ |
102 | msr cpsr_c, r0 \n\ |
118 | \n\ |
103 | \n\ |
119 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
104 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
120 | stmfd r1!, {r4, r5, r6} \n\ |
105 | stmfd r1!, {r4, r5, r6} \n\ |
121 | stmfd r1!, {r7} \n\ |
106 | stmfd r1!, {r7} \n\ |
122 | stmfd r1!, {r2} \n\ |
107 | stmfd r1!, {r2} \n\ |
123 | stmfd r1!, {r3} \n\ |
108 | stmfd r1!, {r3} \n\ |
124 | mrs r0, spsr \n\ |
109 | mrs r0, spsr \n\ |
125 | stmfd r1!, {r0} \n\ |
110 | stmfd r1!, {r0} \n\ |
126 | mov r13, r1 \n\ |
111 | mov r13, r1 \n\ |
127 | 2:" |
112 | 2:" |
128 | ); |
113 | ); |
129 | } |
114 | } |
130 | 115 | ||
- | 116 | /** Returns from exception mode. |
|
- | 117 | * |
|
- | 118 | * Previously saved state of registers (including control register) |
|
- | 119 | * is restored from the stack. |
|
131 | 120 | */ |
|
132 | inline static void load_regs() |
121 | inline static void load_regs() |
133 | { |
122 | { |
134 | asm volatile( "ldmfd r13!, {r0} \n\ |
123 | asm volatile( "ldmfd r13!, {r0} \n\ |
135 | msr spsr, r0 \n\ |
124 | msr spsr, r0 \n\ |
136 | and r0, r0, #0x1f \n\ |
125 | and r0, r0, #0x1f \n\ |
137 | cmp r0, #0x10 \n\ |
126 | cmp r0, #0x10 \n\ |
138 | bne 3f \n\ |
127 | bne 3f \n\ |
139 | \n\ |
128 | \n\ |
140 | @return to user mode \n\ |
129 | @return to user mode \n\ |
141 | ldmfd r13!, {r13, lr}^ \n\ |
130 | ldmfd r13!, {r13, lr}^ \n\ |
142 | b 4f \n\ |
131 | b 4f \n\ |
143 | \n\ |
132 | \n\ |
144 | @return to non-user mode \n\ |
133 | @return to non-user mode \n\ |
145 | 3: \n\ |
134 | 3: \n\ |
146 | ldmfd r13!, {r1, r2} \n\ |
135 | ldmfd r13!, {r1, r2} \n\ |
147 | mrs r3, cpsr \n\ |
136 | mrs r3, cpsr \n\ |
148 | bic r3, r3, #0x1f \n\ |
137 | bic r3, r3, #0x1f \n\ |
149 | orr r3, r3, r0 \n\ |
138 | orr r3, r3, r0 \n\ |
150 | mrs r0, cpsr \n\ |
139 | mrs r0, cpsr \n\ |
151 | msr cpsr_c, r3 \n\ |
140 | msr cpsr_c, r3 \n\ |
152 | \n\ |
141 | \n\ |
153 | mov r13, r1 \n\ |
142 | mov r13, r1 \n\ |
154 | mov lr, r2 \n\ |
143 | mov lr, r2 \n\ |
155 | msr cpsr_c, r0 \n\ |
144 | msr cpsr_c, r0 \n\ |
156 | \n\ |
145 | \n\ |
157 | @actual return \n\ |
146 | @actual return \n\ |
158 | 4: ldmfd r13, {r0-r12, pc}^" |
147 | 4: ldmfd r13, {r0-r12, pc}^" |
159 | ); |
148 | ); |
160 | } |
149 | } |
161 | 150 | ||
162 | - | ||
163 | - | ||
164 | /*#define SAVE_REGS_TO_STACK \ |
- | |
165 | asm("stmfd r13!, {r0-r12, r13, lr}"); \ |
151 | /** Calls exception dispatch routine. */ |
166 | asm("mrs r14, spsr"); \ |
- | |
167 | asm("stmfd r13!, {r14}"); |
- | |
168 | */ |
- | |
169 | - | ||
170 | - | ||
171 | #define CALL_EXC_DISPATCH(exception) \ |
152 | #define CALL_EXC_DISPATCH(exception) \ |
172 | asm("mov r0, %0" : : "i" (exception)); \ |
153 | asm("mov r0, %0" : : "i" (exception)); \ |
173 | asm("mov r1, r13"); \ |
154 | asm("mov r1, r13"); \ |
174 | asm("bl exc_dispatch"); |
155 | asm("bl exc_dispatch"); |
175 | 156 | ||
176 | - | ||
177 | /**Loads registers from the stack and resets SPSR before exitting exception |
- | |
178 | * handler. |
- | |
179 | |
- | |
180 | #define LOAD_REGS_FROM_STACK \ |
- | |
181 | asm("ldmfd r13!, {r14}"); \ |
- | |
182 | asm("msr spsr, r14"); \ |
- | |
183 | asm("ldmfd r13!, {r0-r12, r13, pc}^"); |
- | |
184 | */ |
- | |
185 | - | ||
186 | 157 | ||
187 | /** General exception handler. |
158 | /** General exception handler. |
- | 159 | * |
|
188 | * Stores registers, dispatches the exception, |
160 | * Stores registers, dispatches the exception, |
189 | * and finally restores registers and returns from exception processing. |
161 | * and finally restores registers and returns from exception processing. |
190 | * |
162 | * |
191 | * @param exception Exception number. |
163 | * @param exception Exception number. |
192 | */ |
164 | */ |
193 | #define PROCESS_EXCEPTION(exception) \ |
165 | #define PROCESS_EXCEPTION(exception) \ |
194 | setup_stack_and_save_regs(); \ |
166 | setup_stack_and_save_regs(); \ |
195 | CALL_EXC_DISPATCH(exception) \ |
167 | CALL_EXC_DISPATCH(exception) \ |
196 | load_regs(); |
168 | load_regs(); |
197 | 169 | ||
198 | /* #define PROCESS_EXCEPTION(exception) \ |
- | |
199 | SAVE_REGS_TO_STACK \ |
- | |
200 | CALL_EXC_DISPATCH(exception) \ |
- | |
201 | LOAD_REGS_FROM_STACK*/ |
- | |
202 | - | ||
203 | 170 | ||
204 | /** Updates specified exception vector to jump to given handler. |
171 | /** Updates specified exception vector to jump to given handler. |
- | 172 | * |
|
205 | * Addresses of handlers are stored in memory following exception vectors. |
173 | * Addresses of handlers are stored in memory following exception vectors. |
206 | */ |
174 | */ |
207 | static void install_handler (unsigned handler_addr, unsigned* vector) |
175 | static void install_handler (unsigned handler_addr, unsigned* vector) |
208 | { |
176 | { |
209 | /* relative address (related to exc. vector) of the word |
177 | /* relative address (related to exc. vector) of the word |
210 | * where handler's address is stored |
178 | * where handler's address is stored |
211 | */ |
179 | */ |
212 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
180 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
213 | 181 | ||
214 | /* make it LDR instruction and store at exception vector */ |
182 | /* make it LDR instruction and store at exception vector */ |
215 | *vector = handler_address_ptr | LDR_OPCODE; |
183 | *vector = handler_address_ptr | LDR_OPCODE; |
216 | 184 | ||
217 | /* store handler's address */ |
185 | /* store handler's address */ |
218 | *(vector + EXC_VECTORS) = handler_addr; |
186 | *(vector + EXC_VECTORS) = handler_addr; |
219 | 187 | ||
220 | } |
188 | } |
221 | 189 | ||
222 | 190 | ||
223 | /** Low-level Reset Exception handler. */ |
191 | /** Low-level Reset Exception handler. */ |
224 | static void reset_exception_entry() |
192 | static void reset_exception_entry() |
225 | { |
193 | { |
226 | PROCESS_EXCEPTION(EXC_RESET); |
194 | PROCESS_EXCEPTION(EXC_RESET); |
227 | } |
195 | } |
228 | 196 | ||
229 | 197 | ||
230 | /** Low-level Software Interrupt Exception handler. */ |
198 | /** Low-level Software Interrupt Exception handler. */ |
231 | static void swi_exception_entry() |
199 | static void swi_exception_entry() |
232 | { |
200 | { |
233 | PROCESS_EXCEPTION(EXC_SWI); |
201 | PROCESS_EXCEPTION(EXC_SWI); |
234 | } |
202 | } |
235 | 203 | ||
236 | 204 | ||
237 | /** Low-level Undefined Instruction Exception handler. */ |
205 | /** Low-level Undefined Instruction Exception handler. */ |
238 | static void undef_instr_exception_entry() |
206 | static void undef_instr_exception_entry() |
239 | { |
207 | { |
240 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
208 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
241 | } |
209 | } |
242 | 210 | ||
243 | 211 | ||
244 | /** Low-level Fast Interrupt Exception handler. */ |
212 | /** Low-level Fast Interrupt Exception handler. */ |
245 | static void fiq_exception_entry() |
213 | static void fiq_exception_entry() |
246 | { |
214 | { |
247 | PROCESS_EXCEPTION(EXC_FIQ); |
215 | PROCESS_EXCEPTION(EXC_FIQ); |
248 | } |
216 | } |
249 | 217 | ||
250 | 218 | ||
251 | /** Low-level Prefetch Abort Exception handler. */ |
219 | /** Low-level Prefetch Abort Exception handler. */ |
252 | static void prefetch_abort_exception_entry() |
220 | static void prefetch_abort_exception_entry() |
253 | { |
221 | { |
254 | asm("sub lr, lr, #4"); |
222 | asm("sub lr, lr, #4"); |
255 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
223 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
256 | } |
224 | } |
257 | 225 | ||
258 | 226 | ||
259 | /** Low-level Data Abort Exception handler. */ |
227 | /** Low-level Data Abort Exception handler. */ |
260 | static void data_abort_exception_entry() |
228 | static void data_abort_exception_entry() |
261 | { |
229 | { |
262 | asm("sub lr, lr, #8"); |
230 | asm("sub lr, lr, #8"); |
263 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
231 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
264 | } |
232 | } |
265 | 233 | ||
266 | 234 | ||
267 | /** Low-level Interrupt Exception handler. */ |
235 | /** Low-level Interrupt Exception handler. |
- | 236 | * |
|
- | 237 | * CPU is switched to Undefined mode before further interrupt processing |
|
- | 238 | * because of possible occurence of nested interrupt exception, which |
|
- | 239 | * would overwrite (and thus spoil) stack pointer. |
|
- | 240 | */ |
|
268 | static void irq_exception_entry() |
241 | static void irq_exception_entry() |
269 | { |
242 | { |
270 | asm("sub lr, lr, #4"); |
243 | asm("sub lr, lr, #4"); |
271 | setup_stack_and_save_regs(); |
244 | setup_stack_and_save_regs(); |
272 | 245 | ||
273 | /* switch to Undefined mode */ |
246 | /* switch to Undefined mode */ |
274 | asm("stmfd sp!, {r0-r3}"); |
247 | asm("stmfd sp!, {r0-r3}"); |
275 | asm("mov r1, sp"); |
248 | asm("mov r1, sp"); |
276 | asm("mov r2, lr"); |
249 | asm("mov r2, lr"); |
277 | // asm("mrs r3, spsr"); |
- | |
278 | asm("mrs r0, cpsr"); |
250 | asm("mrs r0, cpsr"); |
279 | asm("bic r0, r0, #0x1f"); |
251 | asm("bic r0, r0, #0x1f"); |
280 | asm("orr r0, r0, #0x1b"); |
252 | asm("orr r0, r0, #0x1b"); |
281 | asm("msr cpsr_c, r0"); |
253 | asm("msr cpsr_c, r0"); |
282 | asm("mov sp, r1"); |
254 | asm("mov sp, r1"); |
283 | asm("mov lr, r2"); |
255 | asm("mov lr, r2"); |
284 | // asm("msr spsr, r3"); |
- | |
285 | asm("ldmfd sp!, {r0-r3}"); |
256 | asm("ldmfd sp!, {r0-r3}"); |
286 | 257 | ||
287 | CALL_EXC_DISPATCH(EXC_IRQ) |
258 | CALL_EXC_DISPATCH(EXC_IRQ) |
288 | 259 | ||
289 | load_regs(); |
260 | load_regs(); |
290 | } |
261 | } |
291 | 262 | ||
292 | 263 | ||
293 | /** Software Interrupt handler. |
264 | /** Software Interrupt handler. |
294 | * |
265 | * |
295 | * Dispatches the syscall. |
266 | * Dispatches the syscall. |
296 | */ |
267 | */ |
297 | static void swi_exception(int exc_no, istate_t *istate) |
268 | static void swi_exception(int exc_no, istate_t *istate) |
298 | { |
269 | { |
299 | /* |
270 | /* |
300 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
271 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
301 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
272 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
302 | */ |
273 | */ |
303 | 274 | ||
304 | istate->r0 = syscall_handler( |
275 | istate->r0 = syscall_handler( |
305 | istate->r0, |
276 | istate->r0, |
306 | istate->r1, |
277 | istate->r1, |
307 | istate->r2, |
278 | istate->r2, |
308 | istate->r3, |
279 | istate->r3, |
309 | istate->r4); |
280 | istate->r4); |
310 | } |
281 | } |
311 | 282 | ||
312 | 283 | ||
313 | /** Interrupt Exception handler. |
284 | /** Interrupt Exception handler. |
314 | * |
285 | * |
315 | * Determines the sources of interrupt, and calls their handlers. |
286 | * Determines the sources of interrupt, and calls their handlers. |
316 | */ |
287 | */ |
317 | static void irq_exception(int exc_no, istate_t *istate) |
288 | static void irq_exception(int exc_no, istate_t *istate) |
318 | { |
289 | { |
319 | machine_irq_exception(exc_no, istate); |
290 | machine_irq_exception(exc_no, istate); |
320 | } |
291 | } |
321 | 292 | ||
322 | 293 | ||
323 | /** Fills exception vectors with appropriate exception handlers. */ |
294 | /** Fills exception vectors with appropriate exception handlers. */ |
324 | void install_exception_handlers(void) |
295 | void install_exception_handlers(void) |
325 | { |
296 | { |
326 | install_handler((unsigned)reset_exception_entry, |
297 | install_handler((unsigned)reset_exception_entry, |
327 | (unsigned*)EXC_RESET_VEC); |
298 | (unsigned*)EXC_RESET_VEC); |
328 | 299 | ||
329 | install_handler((unsigned)undef_instr_exception_entry, |
300 | install_handler((unsigned)undef_instr_exception_entry, |
330 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
301 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
331 | 302 | ||
332 | install_handler((unsigned)swi_exception_entry, |
303 | install_handler((unsigned)swi_exception_entry, |
333 | (unsigned*)EXC_SWI_VEC); |
304 | (unsigned*)EXC_SWI_VEC); |
334 | 305 | ||
335 | install_handler((unsigned)prefetch_abort_exception_entry, |
306 | install_handler((unsigned)prefetch_abort_exception_entry, |
336 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
307 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
337 | 308 | ||
338 | install_handler((unsigned)data_abort_exception_entry, |
309 | install_handler((unsigned)data_abort_exception_entry, |
339 | (unsigned*)EXC_DATA_ABORT_VEC); |
310 | (unsigned*)EXC_DATA_ABORT_VEC); |
340 | 311 | ||
341 | install_handler((unsigned)irq_exception_entry, |
312 | install_handler((unsigned)irq_exception_entry, |
342 | (unsigned*)EXC_IRQ_VEC); |
313 | (unsigned*)EXC_IRQ_VEC); |
343 | 314 | ||
344 | install_handler((unsigned)fiq_exception_entry, |
315 | install_handler((unsigned)fiq_exception_entry, |
345 | (unsigned*)EXC_FIQ_VEC); |
316 | (unsigned*)EXC_FIQ_VEC); |
346 | } |
317 | } |
347 | 318 | ||
348 | 319 | ||
349 | #ifdef HIGH_EXCEPTION_VECTORS |
320 | #ifdef HIGH_EXCEPTION_VECTORS |
350 | /** Activates use of high exception vectors addresses. */ |
321 | /** Activates use of high exception vectors addresses. */ |
351 | static void high_vectors() |
322 | static void high_vectors() |
352 | { |
323 | { |
353 | uint32_t control_reg; |
324 | uint32_t control_reg; |
354 | 325 | ||
355 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
326 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
356 | 327 | ||
357 | //switch on the high vectors bit |
328 | //switch on the high vectors bit |
358 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
329 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
359 | 330 | ||
360 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
331 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
361 | } |
332 | } |
362 | #endif |
333 | #endif |
363 | 334 | ||
364 | 335 | ||
365 | /** Initializes exception handling. |
336 | /** Initializes exception handling. |
366 | * |
337 | * |
367 | * Installs low-level exception handlers and then registers |
338 | * Installs low-level exception handlers and then registers |
368 | * exceptions and their handlers to kernel exception dispatcher. |
339 | * exceptions and their handlers to kernel exception dispatcher. |
369 | */ |
340 | */ |
370 | void exception_init(void) |
341 | void exception_init(void) |
371 | { |
342 | { |
372 | #ifdef HIGH_EXCEPTION_VECTORS |
343 | #ifdef HIGH_EXCEPTION_VECTORS |
373 | high_vectors(); |
344 | high_vectors(); |
374 | #endif |
345 | #endif |
375 | install_exception_handlers(); |
346 | install_exception_handlers(); |
376 | 347 | ||
377 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
348 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
378 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
349 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
379 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
350 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
380 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
351 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
381 | /* TODO add next */ |
- | |
382 | } |
- | |
383 | - | ||
384 | - | ||
385 | /** Sets stack pointers in all supported exception modes. */ |
- | |
386 | void setup_exception_stacks() |
- | |
387 | { |
- | |
388 | /* switch to particular mode and set "r13" there */ |
- | |
389 | - | ||
390 | uint32_t cspr = current_status_reg_read(); |
- | |
391 | - | ||
392 | /* IRQ stack */ |
- | |
393 | current_status_reg_control_write( |
- | |
394 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
- | |
395 | ); |
- | |
396 | asm("ldr r13, =exc_stack"); |
- | |
397 | - | ||
398 | /* abort stack */ |
- | |
399 | current_status_reg_control_write( |
- | |
400 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
- | |
401 | ); |
- | |
402 | asm("ldr r13, =exc_stack"); |
- | |
403 | - | ||
404 | /* TODO if you want to test other exceptions than IRQ, |
- | |
405 | make stack analogous to irq_stack (in start.S), |
- | |
406 | and then set stack pointer here */ |
- | |
407 | - | ||
408 | current_status_reg_control_write(cspr); |
- | |
409 | } |
352 | } |
410 | 353 | ||
411 | 354 | ||
412 | /** Prints #istate_t structure content. |
355 | /** Prints #istate_t structure content. |
413 | * |
356 | * |
414 | * @param istate Structure to be printed. |
357 | * @param istate Structure to be printed. |
415 | */ |
358 | */ |
416 | void print_istate(istate_t *istate) |
359 | void print_istate(istate_t *istate) |
417 | { |
360 | { |
418 | dprintf("istate dump:\n"); |
361 | dprintf("istate dump:\n"); |
419 | 362 | ||
420 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
363 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
421 | istate->r0, istate->r1, istate->r2, istate->r3); |
364 | istate->r0, istate->r1, istate->r2, istate->r3); |
422 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
365 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
423 | istate->r4, istate->r5, istate->r6, istate->r7); |
366 | istate->r4, istate->r5, istate->r6, istate->r7); |
424 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
367 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
425 | istate->r8, istate->r9, istate->r10, istate->r11); |
368 | istate->r8, istate->r9, istate->r10, istate->r11); |
426 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
369 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
427 | istate->r12, istate->sp, istate->lr, istate->spsr); |
370 | istate->r12, istate->sp, istate->lr, istate->spsr); |
428 | 371 | ||
429 | dprintf(" pc: %x\n", istate->pc); |
372 | dprintf(" pc: %x\n", istate->pc); |
430 | } |
373 | } |
431 | 374 | ||
432 | 375 | ||
433 | /** @} |
376 | /** @} |
434 | */ |
377 | */ |
435 | 378 |