WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
    @brief  Exception handlers and exception initialization routines.
 */
 
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <print.h>
#include <syscall/syscall.h>
 
 
#define PREFETCH_OFFSET      0x8
#define BRANCH_OPCODE        0xea000000
#define LDR_OPCODE           0xe59ff000
#define VALID_BRANCH_MASK    0xff000000
#define EXC_VECTORS_SIZE     0x20
#define EXC_VECTORS          0x8
 
 
extern uintptr_t supervisor_sp;
extern uintptr_t exc_stack;
 
 
inline static void setup_stack_and_save_regs()
{
/*
 
str r0, =exc_stack
str r1, =exc_stack + 4
mrs r0, cpsr
mrs r1, spsr
and r0, r0, #0x1f
and r1, r1, #0x1f
cmp r0, r1
be 3f
@different exception mode => preserve sp
ldr r1, [=exc_stack + 4]
ldr r0, [=exc_stack]
 
3:
mrs r0, spsr
stmfd sp!, {r0, sp, lr}
*/
   
asm volatile("ldr r13, =exc_stack       \n\
    stmfd r13!, {r0}            \n\
    mrs r0, spsr                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 1f                  \n\
                        \n\
    @prev mode was usermode         \n\
    ldmfd r13!, {r0}            \n\
    ldr r13, =supervisor_sp         \n\
    ldr r13, [r13]              \n\
    stmfd r13!, {lr}            \n\
    stmfd r13!, {r0-r12}            \n\
    stmfd r13!, {r13, lr}^          \n\
    mrs r0, spsr                \n\
    stmfd r13!, {r0}            \n\
    b 2f                    \n\
                        \n\
    @prev mode was not usermode     \n\
1:                      \n\
    stmfd r13!, {r1, r2, r3}        \n\
    mrs r1, cpsr                \n\
    mov r2, lr              \n\
    bic r1, r1, #0x1f           \n\
    orr r1, r1, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r1              \n\
                        \n\
    mov r3, r13             \n\
    stmfd r13!, {r2}            \n\
    mov r2, lr              \n\
    stmfd r13!, {r4-r12}            \n\
    mov r1, r13             \n\
    @following two lines are for debugging  \n\
    mov sp, #0              \n\
    mov lr, #0              \n\
    msr cpsr_c, r0              \n\
                        \n\
    ldmfd r13!, {r4, r5, r6, r7}        \n\
    stmfd r1!, {r4, r5, r6}         \n\
    stmfd r1!, {r7}             \n\
    stmfd r1!, {r2}             \n\
    stmfd r1!, {r3}             \n\
    mrs r0, spsr                \n\
    stmfd r1!, {r0}             \n\
    mov r13, r1             \n\
2:"
);
}
 
 
inline static void load_regs()
{
asm volatile(   "ldmfd r13!, {r0}       \n\
    msr spsr, r0                \n\
    and r0, r0, #0x1f           \n\
    cmp r0, #0x10               \n\
    bne 3f                  \n\
                        \n\
    @return to user mode            \n\
    ldmfd r13!, {r13, lr}^          \n\
    b 4f                    \n\
                        \n\
    @return to non-user mode        \n\
3:                      \n\
    ldmfd r13!, {r1, r2}            \n\
    mrs r3, cpsr                \n\
    bic r3, r3, #0x1f           \n\
    orr r3, r3, r0              \n\
    mrs r0, cpsr                \n\
    msr cpsr_c, r3              \n\
                        \n\
    mov r13, r1             \n\
    mov lr, r2              \n\
    msr cpsr_c, r0              \n\
                        \n\
    @actual return              \n\
4:  ldmfd r13, {r0-r12, pc}^"
);
}
 
 
 
/*#define SAVE_REGS_TO_STACK            \
    asm("stmfd r13!, {r0-r12, r13, lr}");   \
    asm("mrs r14, spsr");           \
    asm("stmfd r13!, {r14}");
*/
 
 
#define CALL_EXC_DISPATCH(exception)        \
    asm("mov r0, %0" : : "i" (exception));  \
    asm("mov r1, r13");         \
    asm("bl exc_dispatch");     
 
 
/**Loads registers from the stack and resets SPSR before exitting exception
 * handler.
 
#define LOAD_REGS_FROM_STACK            \
    asm("ldmfd r13!, {r14}");       \
    asm("msr spsr, r14");           \
    asm("ldmfd r13!, {r0-r12, r13, pc}^");
 */
 
   
/** General exception handler.
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
#define PROCESS_EXCEPTION(exception)        \
    setup_stack_and_save_regs();        \
    CALL_EXC_DISPATCH(exception)        \
    load_regs();
 
/* #define PROCESS_EXCEPTION(exception)     \
    SAVE_REGS_TO_STACK      \
    CALL_EXC_DISPATCH(exception)        \
    LOAD_REGS_FROM_STACK*/
 
 
/** Updates specified exception vector to jump to given handler.
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler (unsigned handler_addr, unsigned* vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry()
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry()
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry()
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry()
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry()
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry()
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
 
/** Low-level Interrupt Exception handler. */
static void irq_exception_entry()
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
 
    /* switch to Undefined mode */
    asm("stmfd sp!, {r0-r3}");
    asm("mov r1, sp");
    asm("mov r2, lr");
//  asm("mrs r3, spsr");
    asm("mrs r0, cpsr");
    asm("bic r0, r0, #0x1f");
    asm("orr r0, r0, #0x1b");
    asm("msr cpsr_c, r0");
    asm("mov sp, r1");
    asm("mov lr, r2");
//  asm("msr spsr, r3");
    asm("ldmfd sp!, {r0-r3}");
 
    CALL_EXC_DISPATCH(EXC_IRQ)
 
    load_regs();
}
 
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    /*
    dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
        istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
    */
 
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
}
 
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt, and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned)reset_exception_entry,
             (unsigned*)EXC_RESET_VEC);
   
    install_handler((unsigned)undef_instr_exception_entry,
             (unsigned*)EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned)swi_exception_entry,
             (unsigned*)EXC_SWI_VEC);
   
    install_handler((unsigned)prefetch_abort_exception_entry,
             (unsigned*)EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned)data_abort_exception_entry,
             (unsigned*)EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned)irq_exception_entry,
             (unsigned*)EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
             (unsigned*)EXC_FIQ_VEC);
}
 
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors()
{
    uint32_t control_reg;
   
    asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
   
    //switch on the high vectors bit
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
}
#endif
 
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
    /* TODO add next */
}
 
 
/** Sets stack pointers in all supported exception modes. */
void setup_exception_stacks()
{
        /* switch to particular mode and set "r13" there */
 
        uint32_t cspr = current_status_reg_read();
 
        /* IRQ stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* abort stack */
        current_status_reg_control_write(
                        (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE
        );
        asm("ldr r13, =exc_stack");
 
        /* TODO if you want to test other exceptions than IRQ,
        make stack analogous to irq_stack (in start.S),
        and then set stack pointer here */
 
        current_status_reg_control_write(cspr);
}
 
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
 
/** @}
 */
 

Rev 2341	Rev 2344
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	@brief Exception handlers and exception initialization routines.	33	@brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36		36
37	#include <arch/exception.h>	37	#include <arch/exception.h>
38	#include <arch/debug/print.h>	38	#include <arch/debug/print.h>
39	#include <arch/memstr.h>	39	#include <arch/memstr.h>
40	#include <arch/regutils.h>	40	#include <arch/regutils.h>
41	#include <interrupt.h>	41	#include <interrupt.h>
42	#include <arch/machine.h>	42	#include <arch/machine.h>
43	#include <arch/mm/page_fault.h>	43	#include <arch/mm/page_fault.h>
44	#include <print.h>	44	#include <print.h>
45	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
46		46
47		47
48	#define PREFETCH_OFFSET 0x8	48	#define PREFETCH_OFFSET 0x8
49	#define BRANCH_OPCODE 0xea000000	49	#define BRANCH_OPCODE 0xea000000
50	#define LDR_OPCODE 0xe59ff000	50	#define LDR_OPCODE 0xe59ff000
51	#define VALID_BRANCH_MASK 0xff000000	51	#define VALID_BRANCH_MASK 0xff000000
52	#define EXC_VECTORS_SIZE 0x20	52	#define EXC_VECTORS_SIZE 0x20
53	#define EXC_VECTORS 0x8	53	#define EXC_VECTORS 0x8
54		54
55		55
56	extern uintptr_t supervisor_sp;	56	extern uintptr_t supervisor_sp;
57	extern uintptr_t exc_stack;	57	extern uintptr_t exc_stack;
58		58
59		59
60	inline static void setup_stack_and_save_regs()	60	inline static void setup_stack_and_save_regs()
61	{	61	{
-		62	/*
-		63
-		64	str r0, =exc_stack
-		65	str r1, =exc_stack + 4
-		66	mrs r0, cpsr
-		67	mrs r1, spsr
-		68	and r0, r0, #0x1f
-		69	and r1, r1, #0x1f
-		70	cmp r0, r1
-		71	be 3f
-		72	@different exception mode => preserve sp
-		73	ldr r1, [=exc_stack + 4]
-		74	ldr r0, [=exc_stack]
-		75
-		76	3:
-		77	mrs r0, spsr
-		78	stmfd sp!, {r0, sp, lr}
-		79	*/
-		80
62	asm volatile( "ldr r13, =exc_stack \n\	81	asm volatile("ldr r13, =exc_stack \n\
63	stmfd r13!, {r0} \n\	82	stmfd r13!, {r0} \n\
64	mrs r0, spsr \n\	83	mrs r0, spsr \n\
65	and r0, r0, #0x1f \n\	84	and r0, r0, #0x1f \n\
66	cmp r0, #0x10 \n\	85	cmp r0, #0x10 \n\
67	bne 1f \n\	86	bne 1f \n\
68	\n\	87	\n\
69	@prev mode was usermode \n\	88	@prev mode was usermode \n\
70	ldmfd r13!, {r0} \n\	89	ldmfd r13!, {r0} \n\
71	ldr r13, =supervisor_sp \n\	90	ldr r13, =supervisor_sp \n\
72	ldr r13, [r13] \n\	91	ldr r13, [r13] \n\
73	stmfd r13!, {lr} \n\	92	stmfd r13!, {lr} \n\
74	stmfd r13!, {r0-r12} \n\	93	stmfd r13!, {r0-r12} \n\
75	stmfd r13!, {r13, lr}^ \n\	94	stmfd r13!, {r13, lr}^ \n\
76	mrs r0, spsr \n\	95	mrs r0, spsr \n\
77	stmfd r13!, {r0} \n\	96	stmfd r13!, {r0} \n\
78	b 2f \n\	97	b 2f \n\
79	\n\	98	\n\
80	@prev mode was not usermode \n\	99	@prev mode was not usermode \n\
81	1: \n\	100	1: \n\
82	stmfd r13!, {r1, r2, r3} \n\	101	stmfd r13!, {r1, r2, r3} \n\
83	mrs r1, cpsr \n\	102	mrs r1, cpsr \n\
84	mov r2, lr \n\	103	mov r2, lr \n\
85	bic r1, r1, #0x1f \n\	104	bic r1, r1, #0x1f \n\
86	orr r1, r1, r0 \n\	105	orr r1, r1, r0 \n\
87	mrs r0, cpsr \n\	106	mrs r0, cpsr \n\
88	msr cpsr_c, r1 \n\	107	msr cpsr_c, r1 \n\
89	\n\	108	\n\
90	mov r3, r13 \n\	109	mov r3, r13 \n\
91	stmfd r13!, {r2} \n\	110	stmfd r13!, {r2} \n\
92	mov r2, lr \n\	111	mov r2, lr \n\
93	stmfd r13!, {r4-r12} \n\	112	stmfd r13!, {r4-r12} \n\
94	mov r1, r13 \n\	113	mov r1, r13 \n\
95	@following two lines are for debugging \n\	114	@following two lines are for debugging \n\
96	mov sp, #0 \n\	115	mov sp, #0 \n\
97	mov lr, #0 \n\	116	mov lr, #0 \n\
98	msr cpsr_c, r0 \n\	117	msr cpsr_c, r0 \n\
99	\n\	118	\n\
100	ldmfd r13!, {r4, r5, r6, r7} \n\	119	ldmfd r13!, {r4, r5, r6, r7} \n\
101	stmfd r1!, {r4, r5, r6} \n\	120	stmfd r1!, {r4, r5, r6} \n\
102	stmfd r1!, {r7} \n\	121	stmfd r1!, {r7} \n\
103	stmfd r1!, {r2} \n\	122	stmfd r1!, {r2} \n\
104	stmfd r1!, {r3} \n\	123	stmfd r1!, {r3} \n\
105	mrs r0, spsr \n\	124	mrs r0, spsr \n\
106	stmfd r1!, {r0} \n\	125	stmfd r1!, {r0} \n\
107	mov r13, r1 \n\	126	mov r13, r1 \n\
108	2:"	127	2:"
109	);	128	);
110	}	129	}
111		130
112		131
113	inline static void load_regs()	132	inline static void load_regs()
114	{	133	{
115	asm volatile( "ldmfd r13!, {r0} \n\	134	asm volatile( "ldmfd r13!, {r0} \n\
116	msr spsr, r0 \n\	135	msr spsr, r0 \n\
117	and r0, r0, #0x1f \n\	136	and r0, r0, #0x1f \n\
118	cmp r0, #0x10 \n\	137	cmp r0, #0x10 \n\
119	bne 3f \n\	138	bne 3f \n\
120	\n\	139	\n\
121	@return to user mode \n\	140	@return to user mode \n\
122	ldmfd r13!, {r13, lr}^ \n\	141	ldmfd r13!, {r13, lr}^ \n\
123	b 4f \n\	142	b 4f \n\
124	\n\	143	\n\
125	@return to non-user mode \n\	144	@return to non-user mode \n\
126	3: \n\	145	3: \n\
127	ldmfd r13!, {r1, r2} \n\	146	ldmfd r13!, {r1, r2} \n\
128	mrs r3, cpsr \n\	147	mrs r3, cpsr \n\
129	bic r3, r3, #0x1f \n\	148	bic r3, r3, #0x1f \n\
130	orr r3, r3, r0 \n\	149	orr r3, r3, r0 \n\
131	mrs r0, cpsr \n\	150	mrs r0, cpsr \n\
132	msr cpsr_c, r3 \n\	151	msr cpsr_c, r3 \n\
133	\n\	152	\n\
134	mov r13, r1 \n\	153	mov r13, r1 \n\
135	mov lr, r2 \n\	154	mov lr, r2 \n\
136	msr cpsr_c, r0 \n\	155	msr cpsr_c, r0 \n\
137	\n\	156	\n\
138	@actual return \n\	157	@actual return \n\
139	4: ldmfd r13, {r0-r12, pc}^"	158	4: ldmfd r13, {r0-r12, pc}^"
140	);	159	);
141	}	160	}
142		161
143		162
144		163
145	/*#define SAVE_REGS_TO_STACK \	164	/*#define SAVE_REGS_TO_STACK \
146	asm("stmfd r13!, {r0-r12, r13, lr}"); \	165	asm("stmfd r13!, {r0-r12, r13, lr}"); \
147	asm("mrs r14, spsr"); \	166	asm("mrs r14, spsr"); \
148	asm("stmfd r13!, {r14}");	167	asm("stmfd r13!, {r14}");
149	*/	168	*/
150		169
151		170
152	#define CALL_EXC_DISPATCH(exception) \	171	#define CALL_EXC_DISPATCH(exception) \
153	asm("mov r0, %0" : : "i" (exception)); \	172	asm("mov r0, %0" : : "i" (exception)); \
154	asm("mov r1, r13"); \	173	asm("mov r1, r13"); \
155	asm("bl exc_dispatch");	174	asm("bl exc_dispatch");
156		175
157		176
158	/**Loads registers from the stack and resets SPSR before exitting exception	177	/**Loads registers from the stack and resets SPSR before exitting exception
159	* handler.	178	* handler.
160		179
161	#define LOAD_REGS_FROM_STACK \	180	#define LOAD_REGS_FROM_STACK \
162	asm("ldmfd r13!, {r14}"); \	181	asm("ldmfd r13!, {r14}"); \
163	asm("msr spsr, r14"); \	182	asm("msr spsr, r14"); \
164	asm("ldmfd r13!, {r0-r12, r13, pc}^");	183	asm("ldmfd r13!, {r0-r12, r13, pc}^");
165	*/	184	*/
166		185
167		186
168	/** General exception handler.	187	/** General exception handler.
169	* Stores registers, dispatches the exception,	188	* Stores registers, dispatches the exception,
170	* and finally restores registers and returns from exception processing.	189	* and finally restores registers and returns from exception processing.
171	*	190	*
172	* @param exception Exception number.	191	* @param exception Exception number.
173	*/	192	*/
174	#define PROCESS_EXCEPTION(exception) \	193	#define PROCESS_EXCEPTION(exception) \
175	setup_stack_and_save_regs(); \	194	setup_stack_and_save_regs(); \
176	CALL_EXC_DISPATCH(exception) \	195	CALL_EXC_DISPATCH(exception) \
177	load_regs();	196	load_regs();
178		197
179	/* #define PROCESS_EXCEPTION(exception) \	198	/* #define PROCESS_EXCEPTION(exception) \
180	SAVE_REGS_TO_STACK \	199	SAVE_REGS_TO_STACK \
181	CALL_EXC_DISPATCH(exception) \	200	CALL_EXC_DISPATCH(exception) \
182	LOAD_REGS_FROM_STACK*/	201	LOAD_REGS_FROM_STACK*/
183		202
184		203
185	/** Updates specified exception vector to jump to given handler.	204	/** Updates specified exception vector to jump to given handler.
186	* Addresses of handlers are stored in memory following exception vectors.	205	* Addresses of handlers are stored in memory following exception vectors.
187	*/	206	*/
188	static void install_handler (unsigned handler_addr, unsigned* vector)	207	static void install_handler (unsigned handler_addr, unsigned* vector)
189	{	208	{
190	/* relative address (related to exc. vector) of the word	209	/* relative address (related to exc. vector) of the word
191	* where handler's address is stored	210	* where handler's address is stored
192	*/	211	*/
193	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;	212	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
194		213
195	/* make it LDR instruction and store at exception vector */	214	/* make it LDR instruction and store at exception vector */
196	*vector = handler_address_ptr \| LDR_OPCODE;	215	*vector = handler_address_ptr \| LDR_OPCODE;
197		216
198	/* store handler's address */	217	/* store handler's address */
199	*(vector + EXC_VECTORS) = handler_addr;	218	*(vector + EXC_VECTORS) = handler_addr;
200		219
201	}	220	}
202		221
203		222
204	/** Low-level Reset Exception handler. */	223	/** Low-level Reset Exception handler. */
205	static void reset_exception_entry()	224	static void reset_exception_entry()
206	{	225	{
207	PROCESS_EXCEPTION(EXC_RESET);	226	PROCESS_EXCEPTION(EXC_RESET);
208	}	227	}
209		228
210		229
211	/** Low-level Software Interrupt Exception handler. */	230	/** Low-level Software Interrupt Exception handler. */
212	static void swi_exception_entry()	231	static void swi_exception_entry()
213	{	232	{
214	PROCESS_EXCEPTION(EXC_SWI);	233	PROCESS_EXCEPTION(EXC_SWI);
215	}	234	}
216		235
217		236
218	/** Low-level Undefined Instruction Exception handler. */	237	/** Low-level Undefined Instruction Exception handler. */
219	static void undef_instr_exception_entry()	238	static void undef_instr_exception_entry()
220	{	239	{
221	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	240	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
222	}	241	}
223		242
224		243
225	/** Low-level Fast Interrupt Exception handler. */	244	/** Low-level Fast Interrupt Exception handler. */
226	static void fiq_exception_entry()	245	static void fiq_exception_entry()
227	{	246	{
228	PROCESS_EXCEPTION(EXC_FIQ);	247	PROCESS_EXCEPTION(EXC_FIQ);
229	}	248	}
230		249
231		250
232	/** Low-level Prefetch Abort Exception handler. */	251	/** Low-level Prefetch Abort Exception handler. */
233	static void prefetch_abort_exception_entry()	252	static void prefetch_abort_exception_entry()
234	{	253	{
235	asm("sub lr, lr, #4");	254	asm("sub lr, lr, #4");
236	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	255	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
237	}	256	}
238		257
239		258
240	/** Low-level Data Abort Exception handler. */	259	/** Low-level Data Abort Exception handler. */
241	static void data_abort_exception_entry()	260	static void data_abort_exception_entry()
242	{	261	{
243	asm("sub lr, lr, #8");	262	asm("sub lr, lr, #8");
244	PROCESS_EXCEPTION(EXC_DATA_ABORT);	263	PROCESS_EXCEPTION(EXC_DATA_ABORT);
245	}	264	}
246		265
247		266
248	/** Low-level Interrupt Exception handler. */	267	/** Low-level Interrupt Exception handler. */
249	static void irq_exception_entry()	268	static void irq_exception_entry()
250	{	269	{
251	asm("sub lr, lr, #4");	270	asm("sub lr, lr, #4");
-		271	setup_stack_and_save_regs();
-		272
-		273	/* switch to Undefined mode */
-		274	asm("stmfd sp!, {r0-r3}");
-		275	asm("mov r1, sp");
-		276	asm("mov r2, lr");
-		277	// asm("mrs r3, spsr");
-		278	asm("mrs r0, cpsr");
-		279	asm("bic r0, r0, #0x1f");
-		280	asm("orr r0, r0, #0x1b");
-		281	asm("msr cpsr_c, r0");
-		282	asm("mov sp, r1");
-		283	asm("mov lr, r2");
-		284	// asm("msr spsr, r3");
-		285	asm("ldmfd sp!, {r0-r3}");
-		286
252	PROCESS_EXCEPTION(EXC_IRQ);	287	CALL_EXC_DISPATCH(EXC_IRQ)
-		288
-		289	load_regs();
253	}	290	}
254		291
255		292
256	/** Software Interrupt handler.	293	/** Software Interrupt handler.
257	*	294	*
258	* Dispatches the syscall.	295	* Dispatches the syscall.
259	*/	296	*/
260	static void swi_exception(int exc_no, istate_t *istate)	297	static void swi_exception(int exc_no, istate_t *istate)
261	{	298	{
262	/*	299	/*
263	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,	300	dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0,
264	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);	301	istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
265	*/	302	*/
266		303
267	istate->r0 = syscall_handler(	304	istate->r0 = syscall_handler(
268	istate->r0,	305	istate->r0,
269	istate->r1,	306	istate->r1,
270	istate->r2,	307	istate->r2,
271	istate->r3,	308	istate->r3,
272	istate->r4);	309	istate->r4);
273	}	310	}
274		311
275		312
276	/** Interrupt Exception handler.	313	/** Interrupt Exception handler.
277	*	314	*
278	* Determines the sources of interrupt, and calls their handlers.	315	* Determines the sources of interrupt, and calls their handlers.
279	*/	316	*/
280	static void irq_exception(int exc_no, istate_t *istate)	317	static void irq_exception(int exc_no, istate_t *istate)
281	{	318	{
282	machine_irq_exception(exc_no, istate);	319	machine_irq_exception(exc_no, istate);
283	}	320	}
284		321
285		322
286	/** Fills exception vectors with appropriate exception handlers. */	323	/** Fills exception vectors with appropriate exception handlers. */
287	void install_exception_handlers(void)	324	void install_exception_handlers(void)
288	{	325	{
289	install_handler((unsigned)reset_exception_entry,	326	install_handler((unsigned)reset_exception_entry,
290	(unsigned*)EXC_RESET_VEC);	327	(unsigned*)EXC_RESET_VEC);
291		328
292	install_handler((unsigned)undef_instr_exception_entry,	329	install_handler((unsigned)undef_instr_exception_entry,
293	(unsigned*)EXC_UNDEF_INSTR_VEC);	330	(unsigned*)EXC_UNDEF_INSTR_VEC);
294		331
295	install_handler((unsigned)swi_exception_entry,	332	install_handler((unsigned)swi_exception_entry,
296	(unsigned*)EXC_SWI_VEC);	333	(unsigned*)EXC_SWI_VEC);
297		334
298	install_handler((unsigned)prefetch_abort_exception_entry,	335	install_handler((unsigned)prefetch_abort_exception_entry,
299	(unsigned*)EXC_PREFETCH_ABORT_VEC);	336	(unsigned*)EXC_PREFETCH_ABORT_VEC);
300		337
301	install_handler((unsigned)data_abort_exception_entry,	338	install_handler((unsigned)data_abort_exception_entry,
302	(unsigned*)EXC_DATA_ABORT_VEC);	339	(unsigned*)EXC_DATA_ABORT_VEC);
303		340
304	install_handler((unsigned)irq_exception_entry,	341	install_handler((unsigned)irq_exception_entry,
305	(unsigned*)EXC_IRQ_VEC);	342	(unsigned*)EXC_IRQ_VEC);
306		343
307	install_handler((unsigned)fiq_exception_entry,	344	install_handler((unsigned)fiq_exception_entry,
308	(unsigned*)EXC_FIQ_VEC);	345	(unsigned*)EXC_FIQ_VEC);
309	}	346	}
310		347
311		348
312	#ifdef HIGH_EXCEPTION_VECTORS	349	#ifdef HIGH_EXCEPTION_VECTORS
313	/** Activates use of high exception vectors addresses. */	350	/** Activates use of high exception vectors addresses. */
314	static void high_vectors()	351	static void high_vectors()
315	{	352	{
316	uint32_t control_reg;	353	uint32_t control_reg;
317		354
318	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));	355	asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg));
319		356
320	//switch on the high vectors bit	357	//switch on the high vectors bit
321	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	358	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
322		359
323	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	360	asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg));
324	}	361	}
325	#endif	362	#endif
326		363
327		364
328	/** Initializes exception handling.	365	/** Initializes exception handling.
329	*	366	*
330	* Installs low-level exception handlers and then registers	367	* Installs low-level exception handlers and then registers
331	* exceptions and their handlers to kernel exception dispatcher.	368	* exceptions and their handlers to kernel exception dispatcher.
332	*/	369	*/
333	void exception_init(void)	370	void exception_init(void)
334	{	371	{
335	#ifdef HIGH_EXCEPTION_VECTORS	372	#ifdef HIGH_EXCEPTION_VECTORS
336	high_vectors();	373	high_vectors();
337	#endif	374	#endif
338	install_exception_handlers();	375	install_exception_handlers();
339		376
340	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	377	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
341	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);	378	exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort);
342	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	379	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
343	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	380	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
344	/* TODO add next */	381	/* TODO add next */
345	}	382	}
346		383
347		384
348	/** Sets stack pointers in all supported exception modes. */	385	/** Sets stack pointers in all supported exception modes. */
349	void setup_exception_stacks()	386	void setup_exception_stacks()
350	{	387	{
351	/* switch to particular mode and set "r13" there */	388	/* switch to particular mode and set "r13" there */
352		389
353	uint32_t cspr = current_status_reg_read();	390	uint32_t cspr = current_status_reg_read();
354		391
355	/* IRQ stack */	392	/* IRQ stack */
356	current_status_reg_control_write(	393	current_status_reg_control_write(
357	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE	394	(cspr & ~STATUS_REG_MODE_MASK) \| IRQ_MODE
358	);	395	);
359	asm("ldr r13, =exc_stack");	396	asm("ldr r13, =exc_stack");
360		397
361	/* abort stack */	398	/* abort stack */
362	current_status_reg_control_write(	399	current_status_reg_control_write(
363	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE	400	(cspr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE
364	);	401	);
365	asm("ldr r13, =exc_stack");	402	asm("ldr r13, =exc_stack");
366		403
367	/* TODO if you want to test other exceptions than IRQ,	404	/* TODO if you want to test other exceptions than IRQ,
368	make stack analogous to irq_stack (in start.S),	405	make stack analogous to irq_stack (in start.S),
369	and then set stack pointer here */	406	and then set stack pointer here */
370		407
371	current_status_reg_control_write(cspr);	408	current_status_reg_control_write(cspr);
372	}	409	}
373		410
374		411
375	/** Prints #istate_t structure content.	412	/** Prints #istate_t structure content.
376	*	413	*
377	* @param istate Structure to be printed.	414	* @param istate Structure to be printed.
378	*/	415	*/
379	void print_istate(istate_t *istate)	416	void print_istate(istate_t *istate)
380	{	417	{
381	dprintf("istate dump:\n");	418	dprintf("istate dump:\n");
382		419
383	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	420	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
384	istate->r0, istate->r1, istate->r2, istate->r3);	421	istate->r0, istate->r1, istate->r2, istate->r3);
385	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	422	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
386	istate->r4, istate->r5, istate->r6, istate->r7);	423	istate->r4, istate->r5, istate->r6, istate->r7);
387	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	424	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
388	istate->r8, istate->r9, istate->r10, istate->r11);	425	istate->r8, istate->r9, istate->r10, istate->r11);
389	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	426	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
390	istate->r12, istate->sp, istate->lr, istate->spsr);	427	istate->r12, istate->sp, istate->lr, istate->spsr);
391		428
392	dprintf(" pc: %x\n", istate->pc);	429	dprintf(" pc: %x\n", istate->pc);
393	}	430	}
394		431
395		432
396	/** @}	433	/** @}
397	*/	434	*/
398		435

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(root)/branches/arm/kernel/arch/arm32/src/exception.c – Rev 2341 → 2344