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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | @brief Exception handlers and exception initialization routines. |
33 | @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include <arch/debug_print/print.h> |
37 | #include <arch/debug_print/print.h> |
38 | #include <arch/memstr.h> |
38 | #include <arch/memstr.h> |
39 | #include <arch/regutils.h> |
39 | #include <arch/regutils.h> |
40 | #include <interrupt.h> |
40 | #include <interrupt.h> |
41 | #include <arch/drivers/gxemul.h> |
41 | #include <arch/drivers/gxemul.h> |
42 | #include <arch/mm/page_fault.h> |
42 | #include <arch/mm/page_fault.h> |
43 | #include <print.h> |
43 | #include <print.h> |
44 | #include <syscall/syscall.h> |
44 | #include <syscall/syscall.h> |
45 | 45 | ||
46 | #define PREFETCH_OFFSET 0x8 |
46 | #define PREFETCH_OFFSET 0x8 |
47 | #define BRANCH_OPCODE 0xea000000 |
47 | #define BRANCH_OPCODE 0xea000000 |
48 | #define LDR_OPCODE 0xe59ff000 |
48 | #define LDR_OPCODE 0xe59ff000 |
49 | #define VALID_BRANCH_MASK 0xff000000 |
49 | #define VALID_BRANCH_MASK 0xff000000 |
50 | #define EXC_VECTORS_SIZE 0x20 |
50 | #define EXC_VECTORS_SIZE 0x20 |
51 | #define EXC_VECTORS 0x8 |
51 | #define EXC_VECTORS 0x8 |
52 | 52 | ||
53 | extern uintptr_t supervisor_sp; |
53 | extern uintptr_t supervisor_sp; |
54 | extern uintptr_t exc_stack; |
54 | extern uintptr_t exc_stack; |
55 | 55 | ||
56 | inline static void setup_stack_and_save_regs() |
56 | inline static void setup_stack_and_save_regs() |
57 | { |
57 | { |
58 | asm volatile( "ldr r13, =exc_stack \n\ |
58 | asm volatile( "ldr r13, =exc_stack \n\ |
59 | stmfd r13!, {r0} \n\ |
59 | stmfd r13!, {r0} \n\ |
60 | mrs r0, spsr \n\ |
60 | mrs r0, spsr \n\ |
61 | and r0, r0, #0x1f \n\ |
61 | and r0, r0, #0x1f \n\ |
62 | cmp r0, #0x10 \n\ |
62 | cmp r0, #0x10 \n\ |
63 | bne 1f \n\ |
63 | bne 1f \n\ |
64 | \n\ |
64 | \n\ |
65 | @prev mode was usermode \n\ |
65 | @prev mode was usermode \n\ |
66 | ldmfd r13!, {r0} \n\ |
66 | ldmfd r13!, {r0} \n\ |
67 | ldr r13, =supervisor_sp \n\ |
67 | ldr r13, =supervisor_sp \n\ |
68 | ldr r13, [r13] \n\ |
68 | ldr r13, [r13] \n\ |
69 | stmfd r13!, {lr} \n\ |
69 | stmfd r13!, {lr} \n\ |
70 | stmfd r13!, {r0-r12} \n\ |
70 | stmfd r13!, {r0-r12} \n\ |
71 | stmfd r13!, {r13, lr}^ \n\ |
71 | stmfd r13!, {r13, lr}^ \n\ |
72 | mrs r0, spsr \n\ |
72 | mrs r0, spsr \n\ |
73 | stmfd r13!, {r0} \n\ |
73 | stmfd r13!, {r0} \n\ |
74 | b 2f \n\ |
74 | b 2f \n\ |
75 | \n\ |
75 | \n\ |
76 | @prev mode was not usermode \n\ |
76 | @prev mode was not usermode \n\ |
77 | 1: \n\ |
77 | 1: \n\ |
78 | stmfd r13!, {r1, r2, r3} \n\ |
78 | stmfd r13!, {r1, r2, r3} \n\ |
79 | mrs r1, cpsr \n\ |
79 | mrs r1, cpsr \n\ |
80 | mov r2, lr \n\ |
80 | mov r2, lr \n\ |
81 | bic r1, r1, #0x1f \n\ |
81 | bic r1, r1, #0x1f \n\ |
82 | orr r1, r1, r0 \n\ |
82 | orr r1, r1, r0 \n\ |
83 | mrs r0, cpsr \n\ |
83 | mrs r0, cpsr \n\ |
84 | msr cpsr_c, r1 \n\ |
84 | msr cpsr_c, r1 \n\ |
85 | \n\ |
85 | \n\ |
86 | mov r3, r13 \n\ |
86 | mov r3, r13 \n\ |
87 | stmfd r13!, {r2} \n\ |
87 | stmfd r13!, {r2} \n\ |
88 | mov r2, lr \n\ |
88 | mov r2, lr \n\ |
89 | stmfd r13!, {r4-r12} \n\ |
89 | stmfd r13!, {r4-r12} \n\ |
90 | mov r1, r13 \n\ |
90 | mov r1, r13 \n\ |
91 | @following two lines are for debugging \n\ |
91 | @following two lines are for debugging \n\ |
92 | mov sp, #0 \n\ |
92 | mov sp, #0 \n\ |
93 | mov lr, #0 \n\ |
93 | mov lr, #0 \n\ |
94 | msr cpsr_c, r0 \n\ |
94 | msr cpsr_c, r0 \n\ |
95 | \n\ |
95 | \n\ |
96 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
96 | ldmfd r13!, {r4, r5, r6, r7} \n\ |
97 | stmfd r1!, {r4, r5, r6} \n\ |
97 | stmfd r1!, {r4, r5, r6} \n\ |
98 | stmfd r1!, {r7} \n\ |
98 | stmfd r1!, {r7} \n\ |
99 | stmfd r1!, {r2} \n\ |
99 | stmfd r1!, {r2} \n\ |
100 | stmfd r1!, {r3} \n\ |
100 | stmfd r1!, {r3} \n\ |
101 | mrs r0, spsr \n\ |
101 | mrs r0, spsr \n\ |
102 | stmfd r1!, {r0} \n\ |
102 | stmfd r1!, {r0} \n\ |
103 | mov r13, r1 \n\ |
103 | mov r13, r1 \n\ |
104 | 2:" |
104 | 2:" |
105 | ); |
105 | ); |
106 | } |
106 | } |
107 | 107 | ||
108 | 108 | ||
109 | inline static void load_regs() |
109 | inline static void load_regs() |
110 | { |
110 | { |
111 | asm volatile( "ldmfd r13!, {r0} \n\ |
111 | asm volatile( "ldmfd r13!, {r0} \n\ |
112 | msr spsr, r0 \n\ |
112 | msr spsr, r0 \n\ |
113 | and r0, r0, #0x1f \n\ |
113 | and r0, r0, #0x1f \n\ |
114 | cmp r0, #0x10 \n\ |
114 | cmp r0, #0x10 \n\ |
115 | bne 3f \n\ |
115 | bne 3f \n\ |
116 | \n\ |
116 | \n\ |
117 | @return to user mode \n\ |
117 | @return to user mode \n\ |
118 | ldmfd r13!, {r13, lr}^ \n\ |
118 | ldmfd r13!, {r13, lr}^ \n\ |
119 | b 4f \n\ |
119 | b 4f \n\ |
120 | \n\ |
120 | \n\ |
121 | @return to non-user mode \n\ |
121 | @return to non-user mode \n\ |
122 | 3: \n\ |
122 | 3: \n\ |
123 | ldmfd r13!, {r1, r2} \n\ |
123 | ldmfd r13!, {r1, r2} \n\ |
124 | mrs r3, cpsr \n\ |
124 | mrs r3, cpsr \n\ |
125 | bic r3, r3, #0x1f \n\ |
125 | bic r3, r3, #0x1f \n\ |
126 | orr r3, r3, r0 \n\ |
126 | orr r3, r3, r0 \n\ |
127 | mrs r0, cpsr \n\ |
127 | mrs r0, cpsr \n\ |
128 | msr cpsr_c, r3 \n\ |
128 | msr cpsr_c, r3 \n\ |
129 | \n\ |
129 | \n\ |
130 | mov r13, r1 \n\ |
130 | mov r13, r1 \n\ |
131 | mov lr, r2 \n\ |
131 | mov lr, r2 \n\ |
132 | msr cpsr_c, r0 \n\ |
132 | msr cpsr_c, r0 \n\ |
133 | \n\ |
133 | \n\ |
134 | @actual return \n\ |
134 | @actual return \n\ |
135 | 4: ldmfd r13, {r0-r12, pc}^" |
135 | 4: ldmfd r13, {r0-r12, pc}^" |
136 | ); |
136 | ); |
137 | } |
137 | } |
138 | 138 | ||
139 | 139 | ||
140 | 140 | ||
141 | /*#define SAVE_REGS_TO_STACK \ |
141 | /*#define SAVE_REGS_TO_STACK \ |
142 | asm("stmfd r13!, {r0-r12, r13, lr}"); \ |
142 | asm("stmfd r13!, {r0-r12, r13, lr}"); \ |
143 | asm("mrs r14, spsr"); \ |
143 | asm("mrs r14, spsr"); \ |
144 | asm("stmfd r13!, {r14}"); |
144 | asm("stmfd r13!, {r14}"); |
145 | */ |
145 | */ |
146 | 146 | ||
147 | 147 | ||
148 | #define CALL_EXC_DISPATCH(exception) \ |
148 | #define CALL_EXC_DISPATCH(exception) \ |
149 | asm("mov r0, %0" : : "i" (exception)); \ |
149 | asm("mov r0, %0" : : "i" (exception)); \ |
150 | asm("mov r1, r13"); \ |
150 | asm("mov r1, r13"); \ |
151 | asm("bl exc_dispatch"); |
151 | asm("bl exc_dispatch"); |
152 | 152 | ||
153 | 153 | ||
154 | /**Loads registers from the stack and resets SPSR before exitting exception |
154 | /**Loads registers from the stack and resets SPSR before exitting exception |
155 | * handler. |
155 | * handler. |
156 | |
156 | |
157 | #define LOAD_REGS_FROM_STACK \ |
157 | #define LOAD_REGS_FROM_STACK \ |
158 | asm("ldmfd r13!, {r14}"); \ |
158 | asm("ldmfd r13!, {r14}"); \ |
159 | asm("msr spsr, r14"); \ |
159 | asm("msr spsr, r14"); \ |
160 | asm("ldmfd r13!, {r0-r12, r13, pc}^"); |
160 | asm("ldmfd r13!, {r0-r12, r13, pc}^"); |
161 | */ |
161 | */ |
162 | 162 | ||
163 | 163 | ||
164 | /** General exception handler. |
164 | /** General exception handler. |
165 | * Stores registers, dispatches the exception, |
165 | * Stores registers, dispatches the exception, |
166 | * and finally restores registers and returns from exception processing. |
166 | * and finally restores registers and returns from exception processing. |
167 | */ |
167 | */ |
168 | 168 | ||
169 | #define PROCESS_EXCEPTION(exception) \ |
169 | #define PROCESS_EXCEPTION(exception) \ |
170 | setup_stack_and_save_regs(); \ |
170 | setup_stack_and_save_regs(); \ |
171 | CALL_EXC_DISPATCH(exception) \ |
171 | CALL_EXC_DISPATCH(exception) \ |
172 | load_regs(); |
172 | load_regs(); |
173 | 173 | ||
174 | /* #define PROCESS_EXCEPTION(exception) \ |
174 | /* #define PROCESS_EXCEPTION(exception) \ |
175 | SAVE_REGS_TO_STACK \ |
175 | SAVE_REGS_TO_STACK \ |
176 | CALL_EXC_DISPATCH(exception) \ |
176 | CALL_EXC_DISPATCH(exception) \ |
177 | LOAD_REGS_FROM_STACK*/ |
177 | LOAD_REGS_FROM_STACK*/ |
178 | 178 | ||
179 | /** Updates specified exception vector to jump to given handler. |
179 | /** Updates specified exception vector to jump to given handler. |
180 | * Addresses of handlers are stored in memory following exception vectors. |
180 | * Addresses of handlers are stored in memory following exception vectors. |
181 | */ |
181 | */ |
182 | static void install_handler (unsigned handler_addr, unsigned* vector) |
182 | static void install_handler (unsigned handler_addr, unsigned* vector) |
183 | { |
183 | { |
184 | /* relative address (related to exc. vector) of the word |
184 | /* relative address (related to exc. vector) of the word |
185 | * where handler's address is stored |
185 | * where handler's address is stored |
186 | */ |
186 | */ |
187 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
187 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
188 | 188 | ||
189 | /* make it LDR instruction and store at exception vector */ |
189 | /* make it LDR instruction and store at exception vector */ |
190 | *vector = handler_address_ptr | LDR_OPCODE; |
190 | *vector = handler_address_ptr | LDR_OPCODE; |
191 | 191 | ||
192 | /* store handler's address */ |
192 | /* store handler's address */ |
193 | *(vector + EXC_VECTORS) = handler_addr; |
193 | *(vector + EXC_VECTORS) = handler_addr; |
194 | 194 | ||
195 | } |
195 | } |
196 | 196 | ||
197 | 197 | ||
198 | static void reset_exception_entry() |
198 | static void reset_exception_entry() |
199 | { |
199 | { |
200 | PROCESS_EXCEPTION(EXC_RESET); |
200 | PROCESS_EXCEPTION(EXC_RESET); |
201 | } |
201 | } |
202 | 202 | ||
203 | /** Low-level Software Interrupt Exception handler */ |
203 | /** Low-level Software Interrupt Exception handler */ |
204 | static void swi_exception_entry() |
204 | static void swi_exception_entry() |
205 | { |
205 | { |
206 | PROCESS_EXCEPTION(EXC_SWI); |
206 | PROCESS_EXCEPTION(EXC_SWI); |
207 | } |
207 | } |
208 | 208 | ||
209 | /** Low-level Undefined Instruction Exception handler */ |
209 | /** Low-level Undefined Instruction Exception handler */ |
210 | static void undef_instr_exception_entry() |
210 | static void undef_instr_exception_entry() |
211 | { |
211 | { |
212 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
212 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
213 | } |
213 | } |
214 | 214 | ||
215 | /** Low-level Fast Interrupt Exception handler */ |
215 | /** Low-level Fast Interrupt Exception handler */ |
216 | static void fiq_exception_entry() |
216 | static void fiq_exception_entry() |
217 | { |
217 | { |
218 | PROCESS_EXCEPTION(EXC_FIQ); |
218 | PROCESS_EXCEPTION(EXC_FIQ); |
219 | } |
219 | } |
220 | 220 | ||
221 | /** Low-level Prefetch Abort Exception handler */ |
221 | /** Low-level Prefetch Abort Exception handler */ |
222 | static void prefetch_abort_exception_entry() |
222 | static void prefetch_abort_exception_entry() |
223 | { |
223 | { |
224 | asm("sub lr, lr, #4"); |
224 | asm("sub lr, lr, #4"); |
225 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
225 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
226 | } |
226 | } |
227 | 227 | ||
228 | /** Low-level Data Abort Exception handler */ |
228 | /** Low-level Data Abort Exception handler */ |
229 | static void data_abort_exception_entry() |
229 | static void data_abort_exception_entry() |
230 | { |
230 | { |
231 | asm("sub lr, lr, #8"); |
231 | asm("sub lr, lr, #8"); |
232 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
232 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
233 | } |
233 | } |
234 | 234 | ||
235 | 235 | ||
236 | /** Low-level Interrupt Exception handler */ |
236 | /** Low-level Interrupt Exception handler */ |
237 | static void irq_exception_entry() |
237 | static void irq_exception_entry() |
238 | { |
238 | { |
239 | asm("sub lr, lr, #4"); |
239 | asm("sub lr, lr, #4"); |
240 | PROCESS_EXCEPTION(EXC_IRQ); |
240 | PROCESS_EXCEPTION(EXC_IRQ); |
241 | } |
241 | } |
242 | 242 | ||
243 | /** Software Interrupt handler. |
243 | /** Software Interrupt handler. |
244 | * |
244 | * |
245 | * Dispatches the syscall. |
245 | * Dispatches the syscall. |
246 | */ |
246 | */ |
247 | static void swi_exception(int exc_no, istate_t* istate) |
247 | static void swi_exception(int exc_no, istate_t *istate) |
248 | { |
248 | { |
249 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x", istate->r0, |
249 | dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, |
250 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
250 | istate->r1, istate->r2, istate->r3, istate->r4, istate->pc); |
251 | 251 | ||
252 | istate->r0 = syscall_handler( |
252 | istate->r0 = syscall_handler( |
253 | istate->r0, |
253 | istate->r0, |
254 | istate->r1, |
254 | istate->r1, |
255 | istate->r2, |
255 | istate->r2, |
256 | istate->r3, |
256 | istate->r3, |
257 | istate->r4); |
257 | istate->r4); |
258 | } |
258 | } |
259 | 259 | ||
260 | /** Interrupt Exception handler. |
260 | /** Interrupt Exception handler. |
261 | * |
261 | * |
262 | * Determines the sources of interrupt, and calls their handlers. |
262 | * Determines the sources of interrupt, and calls their handlers. |
263 | */ |
263 | */ |
264 | static void irq_exception(int exc_no, istate_t* istate) |
264 | static void irq_exception(int exc_no, istate_t *istate) |
265 | { |
265 | { |
266 | // TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar |
266 | // TODO: move somewhere to gxemul.c and use machine_irq_exception (or some similar |
267 | // name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM |
267 | // name) to avoid using MACHINE == MACHINE_GXEMUL_TESTARM |
268 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
268 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
269 | uint32_t sources = gxemul_irqc_get_sources(); |
269 | uint32_t sources = gxemul_irqc_get_sources(); |
270 | int i = 0; |
270 | int i = 0; |
271 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
271 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
272 | if (sources & (1 << i)) { |
272 | if (sources & (1 << i)) { |
273 | irq_t *irq = irq_dispatch_and_lock(i); |
273 | irq_t *irq = irq_dispatch_and_lock(i); |
274 | if (irq) { |
274 | if (irq) { |
275 | /* The IRQ handler was found. */ |
275 | /* The IRQ handler was found. */ |
276 | irq->handler(irq, irq->arg); |
276 | irq->handler(irq, irq->arg); |
277 | spinlock_unlock(&irq->lock); |
277 | spinlock_unlock(&irq->lock); |
278 | } else { |
278 | } else { |
279 | /* Spurious interrupt.*/ |
279 | /* Spurious interrupt.*/ |
280 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
280 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
281 | } |
281 | } |
282 | } |
282 | } |
283 | } |
283 | } |
284 | #endif |
284 | #endif |
285 | /* TODO remove after testing the above code |
285 | /* TODO remove after testing the above code |
286 | noirq = 0; |
286 | noirq = 0; |
287 | if (i == CONSOLE_IRQ) { |
287 | if (i == CONSOLE_IRQ) { |
288 | char readchar = *(char*)0x10000000; |
288 | char readchar = *(char*)0x10000000; |
289 | if (readchar == 0) { |
289 | if (readchar == 0) { |
290 | aux_puts("?"); |
290 | aux_puts("?"); |
291 | } |
291 | } |
292 | else { |
292 | else { |
293 | dprintf("%c", readchar); |
293 | dprintf("%c", readchar); |
294 | } |
294 | } |
295 | |
295 | |
296 | } |
296 | } |
297 | else if (i == TIMER_IRQ) { |
297 | else if (i == TIMER_IRQ) { |
298 | dprintf("\n.\n"); |
298 | dprintf("\n.\n"); |
299 | //acknowledge |
299 | //acknowledge |
300 | *(uint32_t*)0x15000110 = 0; |
300 | *(uint32_t*)0x15000110 = 0; |
301 | } |
301 | } |
302 | } |
302 | } |
303 | } |
303 | } |
304 | 304 | ||
305 | if (noirq) |
305 | if (noirq) |
306 | aux_puts("IRQ exception without source\n");*/ |
306 | aux_puts("IRQ exception without source\n");*/ |
307 | } |
307 | } |
308 | 308 | ||
309 | /** Fills exception vectors with appropriate exception handlers. |
309 | /** Fills exception vectors with appropriate exception handlers. |
310 | */ |
310 | */ |
311 | void install_exception_handlers(void) |
311 | void install_exception_handlers(void) |
312 | { |
312 | { |
313 | install_handler((unsigned)reset_exception_entry, |
313 | install_handler((unsigned)reset_exception_entry, |
314 | (unsigned*)EXC_RESET_VEC); |
314 | (unsigned*)EXC_RESET_VEC); |
315 | 315 | ||
316 | install_handler((unsigned)undef_instr_exception_entry, |
316 | install_handler((unsigned)undef_instr_exception_entry, |
317 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
317 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
318 | 318 | ||
319 | install_handler((unsigned)swi_exception_entry, |
319 | install_handler((unsigned)swi_exception_entry, |
320 | (unsigned*)EXC_SWI_VEC); |
320 | (unsigned*)EXC_SWI_VEC); |
321 | 321 | ||
322 | install_handler((unsigned)prefetch_abort_exception_entry, |
322 | install_handler((unsigned)prefetch_abort_exception_entry, |
323 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
323 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
324 | 324 | ||
325 | install_handler((unsigned)data_abort_exception_entry, |
325 | install_handler((unsigned)data_abort_exception_entry, |
326 | (unsigned*)EXC_DATA_ABORT_VEC); |
326 | (unsigned*)EXC_DATA_ABORT_VEC); |
327 | 327 | ||
328 | install_handler((unsigned)irq_exception_entry, |
328 | install_handler((unsigned)irq_exception_entry, |
329 | (unsigned*)EXC_IRQ_VEC); |
329 | (unsigned*)EXC_IRQ_VEC); |
330 | 330 | ||
331 | install_handler((unsigned)fiq_exception_entry, |
331 | install_handler((unsigned)fiq_exception_entry, |
332 | (unsigned*)EXC_FIQ_VEC); |
332 | (unsigned*)EXC_FIQ_VEC); |
333 | } |
333 | } |
334 | 334 | ||
335 | #ifdef HIGH_EXCEPTION_VECTORS |
335 | #ifdef HIGH_EXCEPTION_VECTORS |
336 | /** Activates using high exception vectors addresses. */ |
336 | /** Activates using high exception vectors addresses. */ |
337 | static void high_vectors() |
337 | static void high_vectors() |
338 | { |
338 | { |
339 | uint32_t control_reg; |
339 | uint32_t control_reg; |
340 | 340 | ||
341 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
341 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
342 | 342 | ||
343 | //switch on the high vectors bit |
343 | //switch on the high vectors bit |
344 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
344 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
345 | 345 | ||
346 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
346 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
347 | } |
347 | } |
348 | #endif |
348 | #endif |
349 | 349 | ||
350 | /** Initializes exception handling. |
350 | /** Initializes exception handling. |
351 | * |
351 | * |
352 | * Installs low-level exception handlers and then registers |
352 | * Installs low-level exception handlers and then registers |
353 | * exceptions and their handlers to kernel exception dispatcher. |
353 | * exceptions and their handlers to kernel exception dispatcher. |
354 | */ |
354 | */ |
355 | void exception_init(void) |
355 | void exception_init(void) |
356 | { |
356 | { |
357 | #ifdef HIGH_EXCEPTION_VECTORS |
357 | #ifdef HIGH_EXCEPTION_VECTORS |
358 | high_vectors(); |
358 | high_vectors(); |
359 | #endif |
359 | #endif |
360 | install_exception_handlers(); |
360 | install_exception_handlers(); |
361 | 361 | ||
362 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
362 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
363 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
363 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort); |
364 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
364 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort); |
365 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
365 | exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception); |
366 | /* TODO add next */ |
366 | /* TODO add next */ |
367 | } |
367 | } |
368 | 368 | ||
369 | /** Sets stack pointers in all supported exception modes. |
369 | /** Sets stack pointers in all supported exception modes. |
370 | * |
370 | * |
371 | * @param stack_ptr stack pointer |
371 | * @param stack_ptr stack pointer |
372 | */ |
372 | */ |
373 | void setup_exception_stacks() |
373 | void setup_exception_stacks() |
374 | { |
374 | { |
375 | /* switch to particular mode and set "r13" there */ |
375 | /* switch to particular mode and set "r13" there */ |
376 | 376 | ||
377 | uint32_t cspr = current_status_reg_read(); |
377 | uint32_t cspr = current_status_reg_read(); |
378 | 378 | ||
379 | /* IRQ stack */ |
379 | /* IRQ stack */ |
380 | current_status_reg_control_write( |
380 | current_status_reg_control_write( |
381 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
381 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
382 | ); |
382 | ); |
383 | asm("ldr r13, =exc_stack"); |
383 | asm("ldr r13, =exc_stack"); |
384 | 384 | ||
385 | /* abort stack */ |
385 | /* abort stack */ |
386 | current_status_reg_control_write( |
386 | current_status_reg_control_write( |
387 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
387 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
388 | ); |
388 | ); |
389 | asm("ldr r13, =exc_stack"); |
389 | asm("ldr r13, =exc_stack"); |
390 | 390 | ||
391 | /* TODO if you want to test other exceptions than IRQ, |
391 | /* TODO if you want to test other exceptions than IRQ, |
392 | make stack analogous to irq_stack (in start.S), |
392 | make stack analogous to irq_stack (in start.S), |
393 | and then set stack pointer here */ |
393 | and then set stack pointer here */ |
394 | 394 | ||
395 | current_status_reg_control_write(cspr); |
395 | current_status_reg_control_write(cspr); |
396 | 396 | ||
397 | } |
397 | } |
398 | 398 | ||
- | 399 | ||
- | 400 | void print_istate(istate_t *istate) |
|
- | 401 | { |
|
- | 402 | dprintf("istate dump:\n"); |
|
- | 403 | ||
- | 404 | dprintf(" r0: %x r1: %x r2: %x r3: %x\n", |
|
- | 405 | istate->r0, istate->r1, istate->r2, istate->r3); |
|
- | 406 | dprintf(" r4: %x r5: %x r6: %x r7: %x\n", |
|
- | 407 | istate->r4, istate->r5, istate->r6, istate->r7); |
|
- | 408 | dprintf(" r8: %x r8: %x r10: %x r11: %x\n", |
|
- | 409 | istate->r8, istate->r9, istate->r10, istate->r11); |
|
- | 410 | dprintf(" r12: %x sp: %x lr: %x spsr: %x\n", |
|
- | 411 | istate->r12, istate->sp, istate->lr, istate->spsr); |
|
- | 412 | ||
- | 413 | dprintf(" pc: %x\n", istate->pc); |
|
- | 414 | } |
|
- | 415 | ||
- | 416 | ||
399 | /** @} |
417 | /** @} |
400 | */ |
418 | */ |
401 | 419 |