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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | @brief Exception handlers and exception initialization routines. |
33 | @brief Exception handlers and exception initialization routines. |
34 | */ |
34 | */ |
35 | 35 | ||
36 | #include <arch/exception.h> |
36 | #include <arch/exception.h> |
37 | #include "aux_print/printf.h" |
37 | #include <arch/debug_print/print.h> |
38 | #include <arch/memstr.h> |
38 | #include <arch/memstr.h> |
39 | #include <arch/regutils.h> |
39 | #include <arch/regutils.h> |
40 | #include <interrupt.h> |
40 | #include <interrupt.h> |
41 | #include <arch/drivers/gxemul.h> |
41 | #include <arch/drivers/gxemul.h> |
42 | 42 | ||
43 | #define PREFETCH_OFFSET 0x8 |
43 | #define PREFETCH_OFFSET 0x8 |
44 | #define BRANCH_OPCODE 0xea000000 |
44 | #define BRANCH_OPCODE 0xea000000 |
45 | #define LDR_OPCODE 0xe59ff000 |
45 | #define LDR_OPCODE 0xe59ff000 |
46 | #define VALID_BRANCH_MASK 0xff000000 |
46 | #define VALID_BRANCH_MASK 0xff000000 |
47 | #define EXC_VECTORS_SIZE 0x20 |
47 | #define EXC_VECTORS_SIZE 0x20 |
48 | #define EXC_VECTORS 0x8 |
48 | #define EXC_VECTORS 0x8 |
49 | 49 | ||
50 | 50 | ||
51 | #define SAVE_REGS_TO_STACK \ |
51 | #define SAVE_REGS_TO_STACK \ |
52 | asm("stmfd sp!, {r0-r12, sp, lr}"); \ |
52 | asm("stmfd sp!, {r0-r12, sp, lr}"); \ |
53 | asm("mrs r14, spsr"); \ |
53 | asm("mrs r14, spsr"); \ |
54 | asm("stmfd sp!, {r14}"); |
54 | asm("stmfd sp!, {r14}"); |
55 | 55 | ||
56 | #define CALL_EXC_DISPATCH(exception) \ |
56 | #define CALL_EXC_DISPATCH(exception) \ |
57 | asm("mov r0, %0" : : "i" (exception)); \ |
57 | asm("mov r0, %0" : : "i" (exception)); \ |
58 | asm("mov r1, sp"); \ |
58 | asm("mov r1, sp"); \ |
59 | asm("bl exc_dispatch"); |
59 | asm("bl exc_dispatch"); |
60 | 60 | ||
61 | /**Loads registers from the stack and resets SPSR before exitting exception |
61 | /**Loads registers from the stack and resets SPSR before exitting exception |
62 | * handler. |
62 | * handler. |
63 | */ |
63 | */ |
64 | #define LOAD_REGS_FROM_STACK \ |
64 | #define LOAD_REGS_FROM_STACK \ |
65 | asm("ldmfd sp!, {r14}"); \ |
65 | asm("ldmfd sp!, {r14}"); \ |
66 | asm("msr spsr, r14"); \ |
66 | asm("msr spsr, r14"); \ |
67 | asm("ldmfd sp!, {r0-r12, sp, pc}^"); |
67 | asm("ldmfd sp!, {r0-r12, sp, pc}^"); |
68 | 68 | ||
69 | /** General exception handler. |
69 | /** General exception handler. |
70 | * Stores registers, dispatches the exception, |
70 | * Stores registers, dispatches the exception, |
71 | * and finally restores registers and returns from exception processing. |
71 | * and finally restores registers and returns from exception processing. |
72 | */ |
72 | */ |
73 | #define PROCESS_EXCEPTION(exception) \ |
73 | #define PROCESS_EXCEPTION(exception) \ |
74 | SAVE_REGS_TO_STACK \ |
74 | SAVE_REGS_TO_STACK \ |
75 | CALL_EXC_DISPATCH(exception) \ |
75 | CALL_EXC_DISPATCH(exception) \ |
76 | LOAD_REGS_FROM_STACK |
76 | LOAD_REGS_FROM_STACK |
77 | 77 | ||
78 | /** Updates specified exception vector to jump to given handler. |
78 | /** Updates specified exception vector to jump to given handler. |
79 | * Addresses of handlers are stored in memory following exception vectors. |
79 | * Addresses of handlers are stored in memory following exception vectors. |
80 | */ |
80 | */ |
81 | static void install_handler (unsigned handler_addr, unsigned* vector) |
81 | static void install_handler (unsigned handler_addr, unsigned* vector) |
82 | { |
82 | { |
83 | /* relative address (related to exc. vector) of the word |
83 | /* relative address (related to exc. vector) of the word |
84 | * where handler's address is stored |
84 | * where handler's address is stored |
85 | */ |
85 | */ |
86 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
86 | volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET; |
87 | 87 | ||
88 | /* make it LDR instruction and store at exception vector */ |
88 | /* make it LDR instruction and store at exception vector */ |
89 | *vector = handler_address_ptr | LDR_OPCODE; |
89 | *vector = handler_address_ptr | LDR_OPCODE; |
90 | 90 | ||
91 | /* store handler's address */ |
91 | /* store handler's address */ |
92 | *(vector + EXC_VECTORS) = handler_addr; |
92 | *(vector + EXC_VECTORS) = handler_addr; |
93 | } |
93 | } |
94 | 94 | ||
95 | static void reset_exception_entry() |
95 | static void reset_exception_entry() |
96 | { |
96 | { |
97 | PROCESS_EXCEPTION(EXC_RESET); |
97 | PROCESS_EXCEPTION(EXC_RESET); |
98 | } |
98 | } |
99 | 99 | ||
100 | /** Low-level Software Interrupt Exception handler */ |
100 | /** Low-level Software Interrupt Exception handler */ |
101 | static void swi_exception_entry() |
101 | static void swi_exception_entry() |
102 | { |
102 | { |
103 | PROCESS_EXCEPTION(EXC_SWI); |
103 | PROCESS_EXCEPTION(EXC_SWI); |
104 | } |
104 | } |
105 | 105 | ||
106 | /** Low-level Undefined Instruction Exception handler */ |
106 | /** Low-level Undefined Instruction Exception handler */ |
107 | static void undef_instr_exception_entry() |
107 | static void undef_instr_exception_entry() |
108 | { |
108 | { |
109 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
109 | PROCESS_EXCEPTION(EXC_UNDEF_INSTR); |
110 | } |
110 | } |
111 | 111 | ||
112 | /** Low-level Fast Interrupt Exception handler */ |
112 | /** Low-level Fast Interrupt Exception handler */ |
113 | static void fiq_exception_entry() |
113 | static void fiq_exception_entry() |
114 | { |
114 | { |
115 | PROCESS_EXCEPTION(EXC_FIQ); |
115 | PROCESS_EXCEPTION(EXC_FIQ); |
116 | } |
116 | } |
117 | 117 | ||
118 | /** Low-level Prefetch Abort Exception handler */ |
118 | /** Low-level Prefetch Abort Exception handler */ |
119 | static void prefetch_abort_exception_entry() |
119 | static void prefetch_abort_exception_entry() |
120 | { |
120 | { |
121 | asm("sub lr, lr, #4"); |
121 | asm("sub lr, lr, #4"); |
122 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
122 | PROCESS_EXCEPTION(EXC_PREFETCH_ABORT); |
123 | } |
123 | } |
124 | 124 | ||
125 | /** Low-level Data Abort Exception handler */ |
125 | /** Low-level Data Abort Exception handler */ |
126 | static void data_abort_exception_entry() |
126 | static void data_abort_exception_entry() |
127 | { |
127 | { |
128 | asm("sub lr, lr, #8"); |
128 | asm("sub lr, lr, #8"); |
129 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
129 | PROCESS_EXCEPTION(EXC_DATA_ABORT); |
130 | } |
130 | } |
131 | 131 | ||
132 | 132 | ||
133 | /** Low-level Interrupt Exception handler */ |
133 | /** Low-level Interrupt Exception handler */ |
134 | static void irq_exception_entry() |
134 | static void irq_exception_entry() |
135 | { |
135 | { |
136 | asm("sub lr, lr, #4"); |
136 | asm("sub lr, lr, #4"); |
137 | PROCESS_EXCEPTION(EXC_IRQ); |
137 | PROCESS_EXCEPTION(EXC_IRQ); |
138 | } |
138 | } |
139 | 139 | ||
140 | static void prefetch_abort_exception(int exc_no, istate_t* istate) |
140 | static void prefetch_abort_exception(int exc_no, istate_t* istate) |
141 | { |
141 | { |
142 | //aux_puts("(PREFETCH|DATA) ABORT exception caught, not processed.\n"); |
142 | //aux_puts("(PREFETCH|DATA) ABORT exception caught, not processed.\n"); |
143 | } |
143 | } |
144 | 144 | ||
145 | 145 | ||
146 | /** Interrupt Exception handler. |
146 | /** Interrupt Exception handler. |
147 | * Determines the sources of interrupt, and calls their handlers. |
147 | * Determines the sources of interrupt, and calls their handlers. |
148 | */ |
148 | */ |
149 | static void irq_exception(int exc_no, istate_t* istate) |
149 | static void irq_exception(int exc_no, istate_t* istate) |
150 | { |
150 | { |
151 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
151 | #if MACHINE == MACHINE_GXEMUL_TESTARM |
152 | uint32_t sources = gxemul_irqc_get_sources(); |
152 | uint32_t sources = gxemul_irqc_get_sources(); |
153 | int i = 0; |
153 | int i = 0; |
154 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
154 | for (; i < GXEMUL_IRQC_MAX_IRQ; i++) { |
155 | if (sources & (1 << i)) { |
155 | if (sources & (1 << i)) { |
156 | irq_t *irq = irq_dispatch_and_lock(i); |
156 | irq_t *irq = irq_dispatch_and_lock(i); |
157 | if (irq) { |
157 | if (irq) { |
158 | /* The IRQ handler was found. */ |
158 | /* The IRQ handler was found. */ |
159 | irq->handler(irq, irq->arg); |
159 | irq->handler(irq, irq->arg); |
160 | spinlock_unlock(&irq->lock); |
160 | spinlock_unlock(&irq->lock); |
161 | } else { |
161 | } else { |
162 | /* Spurious interrupt.*/ |
162 | /* Spurious interrupt.*/ |
163 | aux_printf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
163 | dprintf("cpu%d: spurious interrupt (inum=%d)\n", CPU->id, i); |
164 | } |
164 | } |
165 | } |
165 | } |
166 | } |
166 | } |
167 | #endif |
167 | #endif |
168 | /* TODO remove after testing the above code |
168 | /* TODO remove after testing the above code |
169 | noirq = 0; |
169 | noirq = 0; |
170 | if (i == CONSOLE_IRQ) { |
170 | if (i == CONSOLE_IRQ) { |
171 | char readchar = *(char*)0x10000000; |
171 | char readchar = *(char*)0x10000000; |
172 | if (readchar == 0) { |
172 | if (readchar == 0) { |
173 | aux_puts("?"); |
173 | aux_puts("?"); |
174 | } |
174 | } |
175 | else { |
175 | else { |
176 | aux_printf("%c", readchar); |
176 | dprintf("%c", readchar); |
177 | } |
177 | } |
178 | |
178 | |
179 | } |
179 | } |
180 | else if (i == TIMER_IRQ) { |
180 | else if (i == TIMER_IRQ) { |
181 | aux_printf("\n.\n"); |
181 | dprintf("\n.\n"); |
182 | //acknowledge |
182 | //acknowledge |
183 | *(uint32_t*)0x15000110 = 0; |
183 | *(uint32_t*)0x15000110 = 0; |
184 | } |
184 | } |
185 | } |
185 | } |
186 | } |
186 | } |
187 | 187 | ||
188 | if (noirq) |
188 | if (noirq) |
189 | aux_puts("IRQ exception without source\n");*/ |
189 | aux_puts("IRQ exception without source\n");*/ |
190 | } |
190 | } |
191 | 191 | ||
192 | /** Fills exception vectors with appropriate exception handlers. |
192 | /** Fills exception vectors with appropriate exception handlers. |
193 | */ |
193 | */ |
194 | void install_exception_handlers(void) |
194 | void install_exception_handlers(void) |
195 | { |
195 | { |
196 | install_handler((unsigned)reset_exception_entry, |
196 | install_handler((unsigned)reset_exception_entry, |
197 | (unsigned*)EXC_RESET_VEC); |
197 | (unsigned*)EXC_RESET_VEC); |
198 | 198 | ||
199 | install_handler((unsigned)undef_instr_exception_entry, |
199 | install_handler((unsigned)undef_instr_exception_entry, |
200 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
200 | (unsigned*)EXC_UNDEF_INSTR_VEC); |
201 | 201 | ||
202 | install_handler((unsigned)swi_exception_entry, |
202 | install_handler((unsigned)swi_exception_entry, |
203 | (unsigned*)EXC_SWI_VEC); |
203 | (unsigned*)EXC_SWI_VEC); |
204 | 204 | ||
205 | install_handler((unsigned)prefetch_abort_exception_entry, |
205 | install_handler((unsigned)prefetch_abort_exception_entry, |
206 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
206 | (unsigned*)EXC_PREFETCH_ABORT_VEC); |
207 | 207 | ||
208 | install_handler((unsigned)data_abort_exception_entry, |
208 | install_handler((unsigned)data_abort_exception_entry, |
209 | (unsigned*)EXC_DATA_ABORT_VEC); |
209 | (unsigned*)EXC_DATA_ABORT_VEC); |
210 | 210 | ||
211 | install_handler((unsigned)irq_exception_entry, |
211 | install_handler((unsigned)irq_exception_entry, |
212 | (unsigned*)EXC_IRQ_VEC); |
212 | (unsigned*)EXC_IRQ_VEC); |
213 | 213 | ||
214 | install_handler((unsigned)fiq_exception_entry, |
214 | install_handler((unsigned)fiq_exception_entry, |
215 | (unsigned*)EXC_FIQ_VEC); |
215 | (unsigned*)EXC_FIQ_VEC); |
216 | } |
216 | } |
217 | 217 | ||
218 | /** Activates using high exception vectors addresses. */ |
218 | /** Activates using high exception vectors addresses. */ |
219 | static void high_vectors() |
219 | static void high_vectors() |
220 | { |
220 | { |
221 | uint32_t control_reg; |
221 | uint32_t control_reg; |
222 | 222 | ||
223 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
223 | asm volatile( "mrc p15, 0, %0, c1, c1": "=r" (control_reg)); |
224 | 224 | ||
225 | //switch on the high vectors bit |
225 | //switch on the high vectors bit |
226 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
226 | control_reg |= CP15_R1_HIGH_VECTORS_BIT; |
227 | 227 | ||
228 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
228 | asm volatile( "mcr p15, 0, %0, c1, c1" : : "r" (control_reg)); |
229 | } |
229 | } |
230 | 230 | ||
231 | 231 | ||
232 | /** Initializes exception handling. |
232 | /** Initializes exception handling. |
233 | * |
233 | * |
234 | * Installs low-level exception handlers and then registers |
234 | * Installs low-level exception handlers and then registers |
235 | * exceptions and their handlers to kernel exception dispatcher. |
235 | * exceptions and their handlers to kernel exception dispatcher. |
236 | */ |
236 | */ |
237 | void exception_init(void) |
237 | void exception_init(void) |
238 | { |
238 | { |
239 | #ifdef HIGH_EXCEPTION_VECTORS |
239 | #ifdef HIGH_EXCEPTION_VECTORS |
240 | high_vectors(); |
240 | high_vectors(); |
241 | #endif |
241 | #endif |
242 | 242 | ||
243 | install_exception_handlers(); |
243 | install_exception_handlers(); |
244 | 244 | ||
245 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
245 | exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception); |
246 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort_exception); |
246 | exc_register(EXC_PREFETCH_ABORT, "prefetch abort", (iroutine) prefetch_abort_exception); |
247 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) prefetch_abort_exception); |
247 | exc_register(EXC_DATA_ABORT, "data abort", (iroutine) prefetch_abort_exception); |
248 | /* TODO add next */ |
248 | /* TODO add next */ |
249 | } |
249 | } |
250 | 250 | ||
251 | /* TODO change soon, temporary hack. */ |
251 | /* TODO change soon, temporary hack. */ |
252 | void setup_exception_stacks() |
252 | void setup_exception_stacks() |
253 | { |
253 | { |
254 | /* switch to particular mode and set "sp" there */ |
254 | /* switch to particular mode and set "sp" there */ |
255 | 255 | ||
256 | uint32_t cspr = current_status_reg_read(); |
256 | uint32_t cspr = current_status_reg_read(); |
257 | 257 | ||
258 | /* IRQ stack */ |
258 | /* IRQ stack */ |
259 | current_status_reg_control_write( |
259 | current_status_reg_control_write( |
260 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
260 | (cspr & ~STATUS_REG_MODE_MASK) | IRQ_MODE |
261 | ); |
261 | ); |
262 | asm("ldr sp, =irq_stack"); |
262 | asm("ldr sp, =irq_stack"); |
263 | 263 | ||
264 | /* abort stack */ |
264 | /* abort stack */ |
265 | current_status_reg_control_write( |
265 | current_status_reg_control_write( |
266 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
266 | (cspr & ~STATUS_REG_MODE_MASK) | ABORT_MODE |
267 | ); |
267 | ); |
268 | asm("ldr sp, =abort_stack"); |
268 | asm("ldr sp, =abort_stack"); |
269 | 269 | ||
270 | /* TODO if you want to test other exceptions than IRQ, |
270 | /* TODO if you want to test other exceptions than IRQ, |
271 | make stack analogous to irq_stack (in start.S), |
271 | make stack analogous to irq_stack (in start.S), |
272 | and then set stack pointer here */ |
272 | and then set stack pointer here */ |
273 | 273 | ||
274 | current_status_reg_control_write( cspr); |
274 | current_status_reg_control_write( cspr); |
275 | 275 | ||
276 | } |
276 | } |
277 | 277 | ||
278 | /** @} |
278 | /** @} |
279 | */ |
279 | */ |
280 | 280 |