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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
2 | * Copyright (c) 2007 Michal Kebrt, Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #include <interrupt.h> |
35 | #include <interrupt.h> |
36 | #include <ipc/irq.h> |
36 | #include <ipc/irq.h> |
37 | #include <console/chardev.h> |
37 | #include <console/chardev.h> |
38 | #include <arch/drivers/gxemul.h> |
38 | #include <arch/drivers/gxemul.h> |
39 | #include <console/console.h> |
39 | #include <console/console.h> |
40 | #include <sysinfo/sysinfo.h> |
40 | #include <sysinfo/sysinfo.h> |
41 | #include <print.h> |
41 | #include <print.h> |
42 | #include <ddi/device.h> |
42 | #include <ddi/device.h> |
43 | #include <mm/page.h> |
43 | #include <mm/page.h> |
44 | #include <arch/machine.h> |
44 | #include <arch/machine.h> |
45 | 45 | ||
46 | /** Address of devices. */ |
46 | /** Address of devices. */ |
47 | #define GXEMUL_VIDEORAM 0x10000000 |
47 | #define GXEMUL_VIDEORAM 0x10000000 |
48 | #define GXEMUL_KBD 0x10000000 |
48 | #define GXEMUL_KBD 0x10000000 |
- | 49 | #define GXEMUL_HALT_OFFSET 0x10 |
|
49 | #define GXEMUL_RTC 0x15000000 |
50 | #define GXEMUL_RTC 0x15000000 |
50 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
51 | #define GXEMUL_RTC_FREQ_OFFSET 0x100 |
51 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
52 | #define GXEMUL_RTC_ACK_OFFSET 0x110 |
52 | #define GXEMUL_IRQC 0x16000000 |
53 | #define GXEMUL_IRQC 0x16000000 |
53 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
54 | #define GXEMUL_IRQC_MASK_OFFSET 0x4 |
54 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
55 | #define GXEMUL_IRQC_UNMASK_OFFSET 0x8 |
55 | #define GXEMUL_MP 0x11000000 |
56 | #define GXEMUL_MP 0x11000000 |
56 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
57 | #define GXEMUL_MP_MEMSIZE_OFFSET 0x0090 |
57 | 58 | ||
58 | 59 | ||
59 | /** IRQs */ |
60 | /** IRQs */ |
60 | #define GXEMUL_KBD_IRQ 2 |
61 | #define GXEMUL_KBD_IRQ 2 |
61 | #define GXEMUL_TIMER_IRQ 4 |
62 | #define GXEMUL_TIMER_IRQ 4 |
62 | 63 | ||
63 | static gxemul_hw_map_t gxemul_hw_map; |
64 | static gxemul_hw_map_t gxemul_hw_map; |
64 | static chardev_t console; |
65 | static chardev_t console; |
65 | static irq_t gxemul_irq; |
66 | static irq_t gxemul_irq; |
66 | static irq_t gxemul_timer_irq; |
67 | static irq_t gxemul_timer_irq; |
67 | 68 | ||
68 | static bool hw_map_init_called = false; |
69 | static bool hw_map_init_called = false; |
69 | 70 | ||
70 | static void gxemul_write(chardev_t *dev, const char ch); |
71 | static void gxemul_write(chardev_t *dev, const char ch); |
71 | static void gxemul_enable(chardev_t *dev); |
72 | static void gxemul_enable(chardev_t *dev); |
72 | static void gxemul_disable(chardev_t *dev); |
73 | static void gxemul_disable(chardev_t *dev); |
73 | static char gxemul_do_read(chardev_t *dev); |
74 | static char gxemul_do_read(chardev_t *dev); |
74 | 75 | ||
75 | static chardev_operations_t gxemul_ops = { |
76 | static chardev_operations_t gxemul_ops = { |
76 | .resume = gxemul_enable, |
77 | .resume = gxemul_enable, |
77 | .suspend = gxemul_disable, |
78 | .suspend = gxemul_disable, |
78 | .write = gxemul_write, |
79 | .write = gxemul_write, |
79 | .read = gxemul_do_read, |
80 | .read = gxemul_do_read, |
80 | }; |
81 | }; |
81 | 82 | ||
82 | 83 | ||
83 | /** Initializes #gxemul_hw_map. */ |
84 | /** Initializes #gxemul_hw_map. */ |
84 | void machine_hw_map_init(void) |
85 | void machine_hw_map_init(void) |
85 | { |
86 | { |
86 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
87 | gxemul_hw_map.videoram = hw_map(GXEMUL_VIDEORAM, PAGE_SIZE); |
87 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
88 | gxemul_hw_map.kbd = hw_map(GXEMUL_KBD, PAGE_SIZE); |
88 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
89 | gxemul_hw_map.rtc = hw_map(GXEMUL_RTC, PAGE_SIZE); |
89 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
90 | gxemul_hw_map.irqc = hw_map(GXEMUL_IRQC, PAGE_SIZE); |
90 | 91 | ||
91 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
92 | gxemul_hw_map.rtc_freq = gxemul_hw_map.rtc + GXEMUL_RTC_FREQ_OFFSET; |
92 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
93 | gxemul_hw_map.rtc_ack = gxemul_hw_map.rtc + GXEMUL_RTC_ACK_OFFSET; |
93 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
94 | gxemul_hw_map.irqc_mask = gxemul_hw_map.irqc + GXEMUL_IRQC_MASK_OFFSET; |
94 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
95 | gxemul_hw_map.irqc_unmask = gxemul_hw_map.irqc + GXEMUL_IRQC_UNMASK_OFFSET; |
95 | 96 | ||
96 | hw_map_init_called = true; |
97 | hw_map_init_called = true; |
97 | } |
98 | } |
98 | 99 | ||
99 | /** Putchar that works with gxemul */ |
100 | /** Putchar that works with gxemul */ |
100 | void gxemul_write(chardev_t *dev, const char ch) |
101 | void gxemul_write(chardev_t *dev, const char ch) |
101 | { |
102 | { |
102 | *((char *) gxemul_hw_map.videoram) = ch; |
103 | *((char *) gxemul_hw_map.videoram) = ch; |
103 | } |
104 | } |
104 | 105 | ||
105 | /* Called from getc(). */ |
106 | /* Called from getc(). */ |
106 | void gxemul_enable(chardev_t *dev) |
107 | void gxemul_enable(chardev_t *dev) |
107 | { |
108 | { |
108 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
109 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
109 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
110 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
110 | } |
111 | } |
111 | 112 | ||
112 | /* Called from getc(). */ |
113 | /* Called from getc(). */ |
113 | void gxemul_disable(chardev_t *dev) |
114 | void gxemul_disable(chardev_t *dev) |
114 | { |
115 | { |
115 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
116 | // cp0_mask_int(GXEMUL_KBD_IRQ); |
116 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
117 | gxemul_irqc_mask(GXEMUL_KBD_IRQ); |
117 | } |
118 | } |
118 | 119 | ||
119 | /** Read character using polling, assume interrupts disabled */ |
120 | /** Read character using polling, assume interrupts disabled */ |
120 | static char gxemul_do_read(chardev_t *dev) |
121 | static char gxemul_do_read(chardev_t *dev) |
121 | { |
122 | { |
122 | char ch; |
123 | char ch; |
123 | 124 | ||
124 | while (1) { |
125 | while (1) { |
125 | ch = *((volatile char *) gxemul_hw_map.kbd); |
126 | ch = *((volatile char *) gxemul_hw_map.kbd); |
126 | if (ch) { |
127 | if (ch) { |
127 | if (ch == '\r') |
128 | if (ch == '\r') |
128 | return '\n'; |
129 | return '\n'; |
129 | if (ch == 0x7f) |
130 | if (ch == 0x7f) |
130 | return '\b'; |
131 | return '\b'; |
131 | return ch; |
132 | return ch; |
132 | } |
133 | } |
133 | } |
134 | } |
134 | } |
135 | } |
135 | 136 | ||
136 | /** Process keyboard interrupt. */ |
137 | /** Process keyboard interrupt. */ |
137 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
138 | static void gxemul_irq_handler(irq_t *irq, void *arg, ...) |
138 | { |
139 | { |
139 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
140 | if ((irq->notif_cfg.notify) && (irq->notif_cfg.answerbox)) |
140 | ipc_irq_send_notif(irq); |
141 | ipc_irq_send_notif(irq); |
141 | else { |
142 | else { |
142 | char ch = 0; |
143 | char ch = 0; |
143 | 144 | ||
144 | ch = *((char *) gxemul_hw_map.kbd); |
145 | ch = *((char *) gxemul_hw_map.kbd); |
145 | if (ch =='\r') |
146 | if (ch =='\r') |
146 | ch = '\n'; |
147 | ch = '\n'; |
147 | if (ch == 0x7f) |
148 | if (ch == 0x7f) |
148 | ch = '\b'; |
149 | ch = '\b'; |
149 | chardev_push_character(&console, ch); |
150 | chardev_push_character(&console, ch); |
150 | } |
151 | } |
151 | } |
152 | } |
152 | 153 | ||
153 | static irq_ownership_t gxemul_claim(void) |
154 | static irq_ownership_t gxemul_claim(void) |
154 | { |
155 | { |
155 | return IRQ_ACCEPT; |
156 | return IRQ_ACCEPT; |
156 | } |
157 | } |
157 | 158 | ||
158 | void machine_grab_console(void) |
159 | void machine_grab_console(void) |
159 | { |
160 | { |
160 | ipl_t ipl = interrupts_disable(); |
161 | ipl_t ipl = interrupts_disable(); |
161 | spinlock_lock(&gxemul_irq.lock); |
162 | spinlock_lock(&gxemul_irq.lock); |
162 | gxemul_irq.notif_cfg.notify = false; |
163 | gxemul_irq.notif_cfg.notify = false; |
163 | spinlock_unlock(&gxemul_irq.lock); |
164 | spinlock_unlock(&gxemul_irq.lock); |
164 | interrupts_restore(ipl); |
165 | interrupts_restore(ipl); |
165 | } |
166 | } |
166 | 167 | ||
167 | void machine_release_console(void) |
168 | void machine_release_console(void) |
168 | { |
169 | { |
169 | ipl_t ipl = interrupts_disable(); |
170 | ipl_t ipl = interrupts_disable(); |
170 | spinlock_lock(&gxemul_irq.lock); |
171 | spinlock_lock(&gxemul_irq.lock); |
171 | if (gxemul_irq.notif_cfg.answerbox) |
172 | if (gxemul_irq.notif_cfg.answerbox) |
172 | gxemul_irq.notif_cfg.notify = true; |
173 | gxemul_irq.notif_cfg.notify = true; |
173 | spinlock_unlock(&gxemul_irq.lock); |
174 | spinlock_unlock(&gxemul_irq.lock); |
174 | interrupts_restore(ipl); |
175 | interrupts_restore(ipl); |
175 | } |
176 | } |
176 | 177 | ||
177 | 178 | ||
178 | /** Return console object representing gxemul console */ |
179 | /** Return console object representing gxemul console */ |
179 | void machine_console_init(devno_t devno) |
180 | void machine_console_init(devno_t devno) |
180 | { |
181 | { |
181 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
182 | chardev_initialize("gxemul_console", &console, &gxemul_ops); |
182 | stdin = &console; |
183 | stdin = &console; |
183 | stdout = &console; |
184 | stdout = &console; |
184 | 185 | ||
185 | irq_initialize(&gxemul_irq); |
186 | irq_initialize(&gxemul_irq); |
186 | gxemul_irq.devno = devno; |
187 | gxemul_irq.devno = devno; |
187 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
188 | gxemul_irq.inr = GXEMUL_KBD_IRQ; |
188 | gxemul_irq.claim = gxemul_claim; |
189 | gxemul_irq.claim = gxemul_claim; |
189 | gxemul_irq.handler = gxemul_irq_handler; |
190 | gxemul_irq.handler = gxemul_irq_handler; |
190 | irq_register(&gxemul_irq); |
191 | irq_register(&gxemul_irq); |
191 | 192 | ||
192 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
193 | // cp0_unmask_int(GXEMUL_KBD_IRQ); |
193 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
194 | gxemul_irqc_unmask(GXEMUL_KBD_IRQ); |
194 | 195 | ||
195 | sysinfo_set_item_val("kbd", NULL, true); |
196 | sysinfo_set_item_val("kbd", NULL, true); |
196 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
197 | sysinfo_set_item_val("kbd.devno", NULL, devno); |
197 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
198 | sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ); |
198 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
199 | sysinfo_set_item_val("kbd.address.virtual", NULL, gxemul_hw_map.kbd); |
199 | } |
200 | } |
200 | 201 | ||
201 | /** Return the mask of active interrupts. */ |
202 | /** Return the mask of active interrupts. */ |
202 | inline uint32_t gxemul_irqc_get_sources(void) |
203 | inline uint32_t gxemul_irqc_get_sources(void) |
203 | { |
204 | { |
204 | return *(uint32_t*) gxemul_hw_map.irqc; |
205 | return *(uint32_t*) gxemul_hw_map.irqc; |
205 | } |
206 | } |
206 | 207 | ||
207 | /** Masks interrupt. |
208 | /** Masks interrupt. |
208 | * |
209 | * |
209 | * @param irq interrupt number |
210 | * @param irq interrupt number |
210 | */ |
211 | */ |
211 | inline void gxemul_irqc_mask(uint32_t irq) |
212 | inline void gxemul_irqc_mask(uint32_t irq) |
212 | { |
213 | { |
213 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
214 | *(uint32_t*) gxemul_hw_map.irqc_mask = irq; |
214 | } |
215 | } |
215 | 216 | ||
216 | /** Unmasks interrupt. |
217 | /** Unmasks interrupt. |
217 | * |
218 | * |
218 | * @param irq interrupt number |
219 | * @param irq interrupt number |
219 | */ |
220 | */ |
220 | inline void gxemul_irqc_unmask(uint32_t irq) |
221 | inline void gxemul_irqc_unmask(uint32_t irq) |
221 | { |
222 | { |
222 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
223 | *(uint32_t*) gxemul_hw_map.irqc_unmask = irq; |
223 | } |
224 | } |
224 | 225 | ||
225 | 226 | ||
226 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
227 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
227 | * |
228 | * |
228 | * @param frequency interrupts frequency (0 disables RTC) |
229 | * @param frequency interrupts frequency (0 disables RTC) |
229 | */ |
230 | */ |
230 | void gxemul_timer_start(uint32_t frequency) |
231 | void gxemul_timer_start(uint32_t frequency) |
231 | { |
232 | { |
232 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
233 | *(uint32_t*) gxemul_hw_map.rtc_freq = frequency; |
233 | } |
234 | } |
234 | 235 | ||
235 | static irq_ownership_t gxemul_timer_claim(void) |
236 | static irq_ownership_t gxemul_timer_claim(void) |
236 | { |
237 | { |
237 | return IRQ_ACCEPT; |
238 | return IRQ_ACCEPT; |
238 | } |
239 | } |
239 | 240 | ||
240 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
241 | static void gxemul_timer_irq_handler(irq_t *irq, void *arg, ...) |
241 | { |
242 | { |
242 | /* TODO time drifts ?? |
243 | /* TODO time drifts ?? |
243 | unsigned long drift; |
244 | unsigned long drift; |
244 | 245 | ||
245 | drift = cp0_count_read() - nextcount; |
246 | drift = cp0_count_read() - nextcount; |
246 | while (drift > cp0_compare_value) { |
247 | while (drift > cp0_compare_value) { |
247 | drift -= cp0_compare_value; |
248 | drift -= cp0_compare_value; |
248 | CPU->missed_clock_ticks++; |
249 | CPU->missed_clock_ticks++; |
249 | } |
250 | } |
250 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
251 | nextcount = cp0_count_read() + cp0_compare_value - drift; |
251 | cp0_compare_write(nextcount); |
252 | cp0_compare_write(nextcount); |
252 | */ |
253 | */ |
253 | 254 | ||
254 | /* |
255 | /* |
255 | * We are holding a lock which prevents preemption. |
256 | * We are holding a lock which prevents preemption. |
256 | * Release the lock, call clock() and reacquire the lock again. |
257 | * Release the lock, call clock() and reacquire the lock again. |
257 | */ |
258 | */ |
258 | spinlock_unlock(&irq->lock); |
259 | spinlock_unlock(&irq->lock); |
259 | clock(); |
260 | clock(); |
260 | spinlock_lock(&irq->lock); |
261 | spinlock_lock(&irq->lock); |
261 | 262 | ||
262 | /* acknowledge tick */ |
263 | /* acknowledge tick */ |
263 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
264 | *(uint32_t*) gxemul_hw_map.rtc_ack = 0; |
264 | 265 | ||
265 | /* TODO what's that? * |
266 | /* TODO what's that? * |
266 | if (virtual_timer_fnc != NULL) |
267 | if (virtual_timer_fnc != NULL) |
267 | virtual_timer_fnc(); |
268 | virtual_timer_fnc(); |
268 | */ |
269 | */ |
269 | } |
270 | } |
270 | 271 | ||
271 | /** |
272 | /** |
272 | * Initializes and registers timer interrupt handler. |
273 | * Initializes and registers timer interrupt handler. |
273 | */ |
274 | */ |
274 | void gxemul_timer_irq_init() |
275 | void gxemul_timer_irq_init() |
275 | { |
276 | { |
276 | irq_initialize(&gxemul_timer_irq); |
277 | irq_initialize(&gxemul_timer_irq); |
277 | gxemul_timer_irq.devno = device_assign_devno(); |
278 | gxemul_timer_irq.devno = device_assign_devno(); |
278 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
279 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
279 | gxemul_timer_irq.claim = gxemul_timer_claim; |
280 | gxemul_timer_irq.claim = gxemul_timer_claim; |
280 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
281 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
281 | 282 | ||
282 | irq_register(&gxemul_timer_irq); |
283 | irq_register(&gxemul_timer_irq); |
283 | } |
284 | } |
284 | 285 | ||
285 | void machine_timer_irq_start() |
286 | void machine_timer_irq_start() |
286 | { |
287 | { |
287 | gxemul_timer_irq_init(); |
288 | gxemul_timer_irq_init(); |
288 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
289 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
289 | } |
290 | } |
290 | 291 | ||
291 | size_t machine_get_memory_size(void) |
292 | size_t machine_get_memory_size(void) |
292 | { |
293 | { |
293 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
294 | return *((int*)(GXEMUL_MP + GXEMUL_MP_MEMSIZE_OFFSET)); |
294 | } |
295 | } |
295 | 296 | ||
296 | void machine_debug_putc(char ch) { |
297 | void machine_debug_putc(char ch) |
- | 298 | { |
|
- | 299 | char * addr = 0; |
|
- | 300 | if (!hw_map_init_called) { |
|
- | 301 | addr = (char *) GXEMUL_KBD; |
|
- | 302 | } else { |
|
- | 303 | addr = (char *) gxemul_hw_map.videoram; |
|
- | 304 | } |
|
- | 305 | ||
- | 306 | *(addr) = ch; |
|
- | 307 | } |
|
- | 308 | ||
- | 309 | void machine_cpu_halt(void) |
|
- | 310 | { |
|
- | 311 | char * addr = 0; |
|
297 | if (!hw_map_init_called) { |
312 | if (!hw_map_init_called) { |
298 | *((volatile char *) GXEMUL_KBD) = ch; |
313 | addr = (char *) GXEMUL_KBD; |
299 | } else { |
314 | } else { |
300 | *((char *) gxemul_hw_map.videoram) = ch; |
315 | addr = (char *) gxemul_hw_map.videoram; |
301 | } |
316 | } |
- | 317 | ||
- | 318 | *(addr + GXEMUL_HALT_OFFSET) = '\0'; |
|
302 | } |
319 | } |
303 | 320 | ||
- | 321 | ||
304 | /** @} |
322 | /** @} |
305 | */ |
323 | */ |
306 | 324 |