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/*
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/*
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 * Copyright (c) 2007 Michal Kebrt
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 * Copyright (c) 2007 Michal Kebrt
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup arm32
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/** @addtogroup arm32
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 * @{
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 * @{
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 */
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 */
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/** @file
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/** @file
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 */
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 */
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#include <arch.h>
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#include <arch.h>
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#include <arch/boot.h>
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#include <arch/boot.h>
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#include <config.h>
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#include <config.h>
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#include <arch/console.h>
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#include <arch/console.h>
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#include <ddi/device.h>
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#include <ddi/device.h>
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#include <genarch/fb/fb.h>
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#include <genarch/fb/fb.h>
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#include <genarch/fb/visuals.h>
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#include <genarch/fb/visuals.h>
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#include <ddi/irq.h>
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#include <ddi/irq.h>
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#include <arch/debug/print.h>
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#include <arch/debug/print.h>
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#include <print.h>
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#include <print.h>
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#include <config.h>
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#include <config.h>
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#include <interrupt.h>
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#include <interrupt.h>
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#include <arch/regutils.h>
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#include <arch/regutils.h>
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#include <arch/machine.h>
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#include <arch/machine.h>
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#include <userspace.h>
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#include <userspace.h>
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bootinfo_t bootinfo;
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bootinfo_t bootinfo;
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extern uintptr_t supervisor_sp;
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extern uintptr_t supervisor_sp;
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void arch_pre_main(void)
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void arch_pre_main(void)
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{
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{
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    int i;
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    int i;
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    init.cnt = bootinfo.cnt;
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    init.cnt = bootinfo.cnt;
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    for (i = 0; i < bootinfo.cnt; ++i) {
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    for (i = 0; i < bootinfo.cnt; ++i) {
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        init.tasks[i].addr = bootinfo.tasks[i].addr;
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        init.tasks[i].addr = bootinfo.tasks[i].addr;
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        init.tasks[i].size = bootinfo.tasks[i].size;
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        init.tasks[i].size = bootinfo.tasks[i].size;
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    }
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    }
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}
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}
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void arch_pre_mm_init(void)
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void arch_pre_mm_init(void)
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{
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{
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    /* It is not assumed by default */
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    /* It is not assumed by default */
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    interrupts_disable();
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    interrupts_disable();
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}
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}
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void arch_post_mm_init(void)
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void arch_post_mm_init(void)
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{
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{
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    machine_hw_map_init();
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    machine_hw_map_init();
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    /* Initialize dispatch table */
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    /* Initialize dispatch table */
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    exception_init();
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    exception_init();
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    interrupt_init();
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    interrupt_init();
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    console_init(device_assign_devno());
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    console_init(device_assign_devno());
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#ifdef CONFIG_FB
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#ifdef CONFIG_FB
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    fb_init(machine_get_fb_address(), 640, 480, 1920, VISUAL_RGB_8_8_8);
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    fb_init(machine_get_fb_address(), 640, 480, 1920, VISUAL_RGB_8_8_8);
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#endif
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#endif
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}
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}
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void arch_post_cpu_init(void)
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void arch_post_cpu_init(void)
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{
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{
97
}
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}
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void arch_pre_smp_init(void)
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void arch_pre_smp_init(void)
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{
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{
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    /* TODO */
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    /* TODO */
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}
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}
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void arch_post_smp_init(void)
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void arch_post_smp_init(void)
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{
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{
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    /* TODO */
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    /* TODO */
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}
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}
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/** Perform arm32 specific tasks needed before the new task is run. */
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/** Perform arm32 specific tasks needed before the new task is run. */
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void before_task_runs_arch(void)
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void before_task_runs_arch(void)
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{
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{
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    tlb_invalidate_all();
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    tlb_invalidate_all();
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}
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}
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/** Perform arm32 specific tasks needed before the new thread is scheduled. */
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/** Perform arm32 specific tasks needed before the new thread is scheduled. */
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void before_thread_runs_arch(void)
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void before_thread_runs_arch(void)
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{
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{
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    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
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    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
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}
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}
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void after_thread_ran_arch(void)
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void after_thread_ran_arch(void)
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{
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{
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}
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}
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/** Struct to hold general purpose register values */
-
 
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typedef struct {
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    uint32_t r0;
-
 
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    uint32_t r1;
-
 
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    uint32_t r2;
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    uint32_t r3;
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    uint32_t r4;
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    uint32_t r5;
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    uint32_t r6;
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    uint32_t r7;
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    uint32_t r8;
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    uint32_t r9;
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    uint32_t r10;
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    uint32_t r11;
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    uint32_t r12;
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    uint32_t sp;
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    uint32_t lr;
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    uint32_t pc;
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149
} ustate_t;
-
 
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-
 
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-
 
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/** Changes processor mode and jumps to the address specified in the first parameter.
-
 
153
 *
-
 
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 *  @param kernel_uarg   Userspace settings (entry point, stack, ...).
-
 
155
 */
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void userspace(uspace_arg_t *kernel_uarg)
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157
{
-
 
158
    // dprintf("Userspace:  .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
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159
    //  (unsigned int)(kernel_uarg->uspace_uarg), kernel_uarg->uspace_entry,
-
 
160
    //  kernel_uarg->uspace_stack);
-
 
161
 
-
 
162
    volatile ustate_t ustate;
-
 
163
 
-
 
164
    // set first parameter
-
 
165
    ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
-
 
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-
 
167
    // clear other registers
-
 
168
    ustate.r1 = ustate.r2  = ustate.r3  = ustate.r4  =
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        ustate.r5 = ustate.r6  = ustate.r7  = ustate.r8  =
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        ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
-
 
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-
 
172
    ustate.lr = 3;
-
 
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-
 
174
    //set user stack
-
 
175
    ustate.sp = ((uint32_t)kernel_uarg->uspace_stack) +
-
 
176
            PAGE_SIZE - sizeof(void*);
-
 
177
    //on the bottom of stack there is pointer to TLS
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-
 
179
    //set where uspace execution starts
-
 
180
    ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
-
 
181
 
-
 
182
    //status register in user mode
-
 
183
    ipl_t cpsr = current_status_reg_read();
-
 
184
    cpsr &= ~STATUS_REG_MODE_MASK | USER_MODE;
-
 
185
   
-
 
186
    ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) | SUPERVISOR_MODE;
-
 
187
 
-
 
188
    asm __volatile__ (
-
 
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        // save pointer into ustate struct
-
 
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        "mov r0, %0         \n"
-
 
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        // save cspr
-
 
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        "mov r1, %1         \n"
-
 
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        // change mode into any exception mode
-
 
194
        "msr cpsr_c, %2         \n"
-
 
195
        // set saved cpsr
-
 
196
        "msr spsr_c, r1 \n"
-
 
197
 
-
 
198
        "mov sp, r0 \n"
-
 
199
        // replace almost all registers
-
 
200
        "ldmfd sp!, {r0-r12, sp, lr}^\n"
-
 
201
        //jump to the usermode
-
 
202
        "ldmfd sp!, {pc}^"
-
 
203
    : // no output
-
 
204
    : "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
-
 
205
    : "r0","r1"
-
 
206
    );
-
 
207
 
-
 
208
    while(1) ;
-
 
209
}
-
 
210
 
-
 
211
 
131
 
212
void cpu_halt(void)
132
void cpu_halt(void)
213
{
133
{
214
    machine_cpu_halt();
134
    machine_cpu_halt();
215
}
135
}
216
 
136
 
217
/** @}
137
/** @}
218
 */
138
 */
219
 
139
 
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