WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/arm32.c


/*
 * Copyright (c) 2007 Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 */
 
 
#include <arch.h>
#include <arch/boot.h>
#include <config.h>
#include <arch/console.h>
#include <ddi/device.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <ddi/irq.h>
#include <arch/debug/print.h>
#include <print.h>
#include <config.h>
#include <interrupt.h>
#include <arch/regutils.h>
#include <arch/machine.h>
#include <userspace.h>
 
bootinfo_t bootinfo;
// // uintptr_t supervisor_sp /*__attribute__ ((section (".text")))*/;
extern uintptr_t supervisor_sp;
 
 
void arch_pre_main(void)
{
    int i;
 
    init.cnt = bootinfo.cnt;
 
    for (i = 0; i < bootinfo.cnt; ++i) {
        init.tasks[i].addr = bootinfo.tasks[i].addr;
        init.tasks[i].size = bootinfo.tasks[i].size;
    }
   
}
 
 
void arch_pre_mm_init(void)
{
    /* It is not assumed by default */
    interrupts_disable();
 
    setup_exception_stacks();
}
 
 
void arch_post_mm_init(void)
{
    machine_hw_map_init();
 
    /* Initialize dispatch table */
    exception_init();
 
    interrupt_init();
   
    console_init(device_assign_devno());
 
 
}
 
 
void arch_post_cpu_init(void)
{
}
 
 
void arch_pre_smp_init(void)
{
    /* TODO */
}
 
 
void arch_post_smp_init(void)
{
    /* TODO */
}
 
 
/** Perform arm32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
    tlb_invalidate_all();
}
 
 
/** Perform arm32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
}
 
 
void after_thread_ran_arch(void)
{
}
 
 
/** Struct to hold general purpose register values */
typedef struct {
    uint32_t r0;
    uint32_t r1;
    uint32_t r2;
    uint32_t r3;
    uint32_t r4;
    uint32_t r5;
    uint32_t r6;
    uint32_t r7;
    uint32_t r8;
    uint32_t r9;
    uint32_t r10;
    uint32_t r11;
    uint32_t r12;
    uint32_t sp;
    uint32_t lr;
    uint32_t pc;
} ustate_t;
 
 
/** Changes processor mode and jumps to the address specified in the first parameter.
 *
 *  @param kernel_uarg   Userspace settings (entry point, stack, ...).
 */
void userspace(uspace_arg_t *kernel_uarg)
{
    dprintf("Userspace:  .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
        (unsigned int)(kernel_uarg->uspace_uarg), kernel_uarg->uspace_entry,
        kernel_uarg->uspace_stack);
 
    volatile ustate_t ustate;
 
    // set first parameter
    ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
 
    // clear other registers
    ustate.r1 = ustate.r2  = ustate.r3  = ustate.r4  =
        ustate.r5 = ustate.r6  = ustate.r7  = ustate.r8  =
        ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
 
    ustate.lr = 3;
 
    //set user stack
    ustate.sp = ((uint32_t)kernel_uarg->uspace_stack) +
            PAGE_SIZE - sizeof(void*);
    //on the bottom of stack there is pointer to TLS
   
    //set where uspace execution starts
    ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
 
    //status register in user mode
    ipl_t cpsr = current_status_reg_read();
    cpsr &= ~STATUS_REG_MODE_MASK | USER_MODE;
   
    ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) | SUPERVISOR_MODE;
 
    asm __volatile__ (
        // save pointer into ustate struct
        "mov r0, %0         \n"
        // save cspr
        "mov r1, %1         \n"
        // change mode into any exception mode
        "msr cpsr_c, %2         \n"
        // set saved cpsr
        "msr spsr_c, r1 \n"
 
        "mov sp, r0 \n"
        // replace almost all registers
        "ldmfd sp!, {r0-r12, sp, lr}^\n"
        //jump to the usermode
        "ldmfd sp!, {pc}^"
    : // no output
    : "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
    : "r0","r1"
    );
 
    while(1) ;
}
 
 
void cpu_halt(void)
{
    machine_cpu_halt();
}
 
/** @}
 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Rev 2329	Rev 2331
1	/*	1	/*
2	* Copyright (c) 2007 Michal Kebrt	2	* Copyright (c) 2007 Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35		35
36	#include <arch.h>	36	#include <arch.h>
37	#include <arch/boot.h>	37	#include <arch/boot.h>
38	#include <config.h>	38	#include <config.h>
39	#include <arch/console.h>	39	#include <arch/console.h>
40	#include <ddi/device.h>	40	#include <ddi/device.h>
41	#include <genarch/fb/fb.h>	41	#include <genarch/fb/fb.h>
42	#include <genarch/fb/visuals.h>	42	#include <genarch/fb/visuals.h>
43	#include <ddi/irq.h>	43	#include <ddi/irq.h>
44	#include <arch/debug/print.h>	44	#include <arch/debug/print.h>
45	#include <print.h>	45	#include <print.h>
46	#include <config.h>	46	#include <config.h>
47	#include <interrupt.h>	47	#include <interrupt.h>
48	#include <arch/regutils.h>	48	#include <arch/regutils.h>
49	#include <arch/machine.h>	49	#include <arch/machine.h>
50	#include <userspace.h>	50	#include <userspace.h>
51		51
52	bootinfo_t bootinfo;	52	bootinfo_t bootinfo;
53	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;	53	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;
54	extern uintptr_t supervisor_sp;	54	extern uintptr_t supervisor_sp;
55		55
56		56
57	void arch_pre_main(void)	57	void arch_pre_main(void)
58	{	58	{
59	int i;	59	int i;
60		60
61	init.cnt = bootinfo.cnt;	61	init.cnt = bootinfo.cnt;
62		62
63	for (i = 0; i < bootinfo.cnt; ++i) {	63	for (i = 0; i < bootinfo.cnt; ++i) {
64	init.tasks[i].addr = bootinfo.tasks[i].addr;	64	init.tasks[i].addr = bootinfo.tasks[i].addr;
65	init.tasks[i].size = bootinfo.tasks[i].size;	65	init.tasks[i].size = bootinfo.tasks[i].size;
66	}	66	}
67		67
68	}	68	}
69		69
70		70
71	void arch_pre_mm_init(void)	71	void arch_pre_mm_init(void)
72	{	72	{
73	/* It is not assumed by default */	73	/* It is not assumed by default */
74	interrupts_disable();	74	interrupts_disable();
75		75
76	setup_exception_stacks();	76	setup_exception_stacks();
77	}	77	}
78		78
79		79
80	void arch_post_mm_init(void)	80	void arch_post_mm_init(void)
81	{	81	{
82	machine_hw_map_init();	82	machine_hw_map_init();
83		83
84	/* Initialize dispatch table */	84	/* Initialize dispatch table */
85	exception_init();	85	exception_init();
86		86
87	interrupt_init();	87	interrupt_init();
88		88
89	console_init(device_assign_devno());	89	console_init(device_assign_devno());
90		-
91	interrupts_enable();	-
92	}	90	}
93		91
94		92
95	void arch_post_cpu_init(void)	93	void arch_post_cpu_init(void)
96	{	94	{
97	}	95	}
98		96
99		97
100	void arch_pre_smp_init(void)	98	void arch_pre_smp_init(void)
101	{	99	{
102	/* TODO */	100	/* TODO */
103	}	101	}
104		102
105		103
106	void arch_post_smp_init(void)	104	void arch_post_smp_init(void)
107	{	105	{
108	/* TODO */	106	/* TODO */
109	}	107	}
110		108
111		109
112	/** Perform arm32 specific tasks needed before the new task is run. */	110	/** Perform arm32 specific tasks needed before the new task is run. */
113	void before_task_runs_arch(void)	111	void before_task_runs_arch(void)
114	{	112	{
115	tlb_invalidate_all();	113	tlb_invalidate_all();
116	}	114	}
117		115
118		116
119	/** Perform arm32 specific tasks needed before the new thread is scheduled. */	117	/** Perform arm32 specific tasks needed before the new thread is scheduled. */
120	void before_thread_runs_arch(void)	118	void before_thread_runs_arch(void)
121	{	119	{
122	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];	120	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
123	}	121	}
124		122
125		123
126	void after_thread_ran_arch(void)	124	void after_thread_ran_arch(void)
127	{	125	{
128	}	126	}
129		127
130		128
131	/** Struct to hold general purpose register values */	129	/** Struct to hold general purpose register values */
132	typedef struct {	130	typedef struct {
133	uint32_t r0;	131	uint32_t r0;
134	uint32_t r1;	132	uint32_t r1;
135	uint32_t r2;	133	uint32_t r2;
136	uint32_t r3;	134	uint32_t r3;
137	uint32_t r4;	135	uint32_t r4;
138	uint32_t r5;	136	uint32_t r5;
139	uint32_t r6;	137	uint32_t r6;
140	uint32_t r7;	138	uint32_t r7;
141	uint32_t r8;	139	uint32_t r8;
142	uint32_t r9;	140	uint32_t r9;
143	uint32_t r10;	141	uint32_t r10;
144	uint32_t r11;	142	uint32_t r11;
145	uint32_t r12;	143	uint32_t r12;
146	uint32_t sp;	144	uint32_t sp;
147	uint32_t lr;	145	uint32_t lr;
148	uint32_t pc;	146	uint32_t pc;
149	} ustate_t;	147	} ustate_t;
150		148
151		149
152	/** Changes processor mode and jumps to the address specified in the first parameter.	150	/** Changes processor mode and jumps to the address specified in the first parameter.
153	*	151	*
154	* @param kernel_uarg Userspace settings (entry point, stack, ...).	152	* @param kernel_uarg Userspace settings (entry point, stack, ...).
155	*/	153	*/
156	void userspace(uspace_arg_t *kernel_uarg)	154	void userspace(uspace_arg_t *kernel_uarg)
157	{	155	{
158	dprintf("Userspace: .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",	156	dprintf("Userspace: .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
159	(unsigned int)(kernel_uarg->uspace_uarg), kernel_uarg->uspace_entry,	157	(unsigned int)(kernel_uarg->uspace_uarg), kernel_uarg->uspace_entry,
160	kernel_uarg->uspace_stack);	158	kernel_uarg->uspace_stack);
161		159
162	volatile ustate_t ustate;	160	volatile ustate_t ustate;
163		161
164	// set first parameter	162	// set first parameter
165	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;	163	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
166		164
167	// clear other registers	165	// clear other registers
168	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =	166	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =
169	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =	167	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =
170	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;	168	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
171		169
172	ustate.lr = 3;	170	ustate.lr = 3;
173		171
174	//set user stack	172	//set user stack
175	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack) +	173	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack) +
176	PAGE_SIZE - sizeof(void*);	174	PAGE_SIZE - sizeof(void*);
177	//on the bottom of stack there is pointer to TLS	175	//on the bottom of stack there is pointer to TLS
178		176
179	//set where uspace execution starts	177	//set where uspace execution starts
180	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;	178	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
181		179
182	//status register in user mode	180	//status register in user mode
183	ipl_t cpsr = current_status_reg_read();	181	ipl_t cpsr = current_status_reg_read();
184	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;	182	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;
185		183
186	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| SUPERVISOR_MODE;	184	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| SUPERVISOR_MODE;
187		185
188	asm __volatile__ (	186	asm __volatile__ (
189	// save pointer into ustate struct	187	// save pointer into ustate struct
190	"mov r0, %0 \n"	188	"mov r0, %0 \n"
191	// save cspr	189	// save cspr
192	"mov r1, %1 \n"	190	"mov r1, %1 \n"
193	// change mode into any exception mode	191	// change mode into any exception mode
194	"msr cpsr_c, %2 \n"	192	"msr cpsr_c, %2 \n"
195	// set saved cpsr	193	// set saved cpsr
196	"msr spsr_c, r1 \n"	194	"msr spsr_c, r1 \n"
197		195
198	"mov sp, r0 \n"	196	"mov sp, r0 \n"
199	// replace almost all registers	197	// replace almost all registers
200	"ldmfd sp!, {r0-r12, sp, lr}^\n"	198	"ldmfd sp!, {r0-r12, sp, lr}^\n"
201	//jump to the usermode	199	//jump to the usermode
202	"ldmfd sp!, {pc}^"	200	"ldmfd sp!, {pc}^"
203	: // no output	201	: // no output
204	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //	202	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
205	: "r0","r1"	203	: "r0","r1"
206	);	204	);
207		205
208	while(1) ;	206	while(1) ;
209	}	207	}
210		208
211		209
212	void cpu_halt(void)	210	void cpu_halt(void)
213	{	211	{
214	machine_cpu_halt();	212	machine_cpu_halt();
215	}	213	}
216		214
217	/** @}	215	/** @}
218	*/	216	*/
219		217
220		218
221		219
222		220
223		221
224		222
225		223
226		224
227		225
228		226
229		227
230		228
231		229
232		230
233		231

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