WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/arm32.c


/*
 * Copyright (c) 2007 Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 */
 
 
#include <arch.h>
#include <arch/boot.h>
#include <config.h>
#include <arch/console.h>
#include <ddi/device.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <ddi/irq.h>
 
#include <arch/debug_print/print.h>
#include <print.h>
#include <config.h>
#include <interrupt.h>
#include <arch/regutils.h>
#include <arch/machine.h>
#include <userspace.h>
 
bootinfo_t bootinfo;
// // uintptr_t supervisor_sp /*__attribute__ ((section (".text")))*/;
extern uintptr_t supervisor_sp;
 
//TODO: Remove include and move into exceptio.c
#include <arch/exception.h>
 
#include <syscall/syscall.h>
void tmp_swi_exception(int exc_no, istate_t* istate);
void tmp_swi_exception(int exc_no, istate_t* istate)
{
    ASSERT(exc_no == EXC_SWI);
    ASSERT(istate);
    // TODO: Alf ... remove aftet swi_exception is tested
    dprintf("\nSWI - istate dump input :\n");
    dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
    dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
    dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
    dprintf("   r12:%X    r13:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
//  dprintf("   prev_lr:%X    prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
    // call kernel to serve syscall
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
 
    // TODO: Alf ... remove aftet swi_exception is tested
    dprintf("\nSWI - Istate dump after :\n");
    dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
    dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
    dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
    dprintf("   r12:%X    r13:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
//  dprintf("   prev_lr:%X    prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
}
 
 
void arch_pre_main(void)
{
    int i;
 
    init.cnt = bootinfo.cnt;
 
    for (i = 0; i < bootinfo.cnt; ++i) {
        init.tasks[i].addr = bootinfo.tasks[i].addr;
        init.tasks[i].size = bootinfo.tasks[i].size;
    }
   
}
 
void arch_pre_mm_init(void)
{
    /* It is not assumed by default */
    interrupts_disable();
 
    setup_exception_stacks();
 
}
 
void prefetch_exception_generator(void);
 
void arch_post_mm_init(void)
{
    machine_hw_map_init();
 
    /* Initialize dispatch table */
    exception_init();
 
    interrupt_init();
   
    console_init(device_assign_devno());
   
    //fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);
   
    interrupts_enable();
}
 
void arch_post_cpu_init(void)
{
    /* TODO */
}
 
void arch_pre_smp_init(void)
{
    /* TODO */
}
 
void arch_post_smp_init(void)
{
    /* TODO */
}
 
/** Perform arm32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
    /* TODO */
}
 
/** Perform arm32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
}
 
void after_thread_ran_arch(void)
{
    /* TODO */
}
 
/** Struct to hold general purpose register values */
typedef struct {
    uint32_t r0;
    uint32_t r1;
    uint32_t r2;
    uint32_t r3;
    uint32_t r4;
    uint32_t r5;
    uint32_t r6;
    uint32_t r7;
    uint32_t r8;
    uint32_t r9;
    uint32_t r10;
    uint32_t r11;
    uint32_t r12;
    uint32_t sp;
    uint32_t lr;
    uint32_t pc;
} ustate_t;
 
 
void prefetch_exception_generator(void)  {
 asm __volatile__ (
    "ldr pc, =0x7000000"
 );
 
}
 
/** Change processor mode and jump into addres specified in
 *  kernel_uarg.uspace_entry
 * \param kernel_uarg information needed for correct setting of userspace
 */
void userspace(uspace_arg_t *kernel_uarg)
{
    dprintf("userspace\n");
 
    dprintf("userspce krnl_uard  .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
      (unsigned int)(kernel_uarg->uspace_uarg),
      kernel_uarg->uspace_entry,
      kernel_uarg->uspace_stack);
 
        volatile ustate_t ustate;
 
    //Step 1 ... prepare user space environment
    //set first paramater
    ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
 
    //clear other registers
    ustate.r1 = ustate.r2  = ustate.r3  = ustate.r4  =
        ustate.r5 = ustate.r6  = ustate.r7  = ustate.r8  =
        ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
        ustate.lr = 3;
 
    //set user stack
        ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;
 
    //set where uspace executin starts
        ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
 
 
    //status register in user mode
    ipl_t cpsr = current_status_reg_read();
        cpsr &= ~STATUS_REG_MODE_MASK | USER_MODE;
   
    ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) | SUPERVISOR_MODE;
 
    asm __volatile__ (
        // save pointer into ustate struct
        "mov r0, %0         \n"
        // save cspr
        "mov r1, %1         \n"
        // change mode into any exception mode
        "msr cpsr_c, %2         \n"
        // set saved cpsr
        "msr spsr_c, r1 \n"
 
        "mov sp, r0 \n"
        // replace almost all registers
        "ldmfd sp!, {r0-r12, sp, lr}^\n"
        //jump to the usermode
        "ldmfd sp!, {pc}^"
    : // no output
    : "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
    : "r0","r1"
    );
 
    while(1) ;
}
 
 
void cpu_halt(void)
{
    machine_cpu_halt();
}
 
/** @}
 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Rev 2298	Rev 2300
1	/*	1	/*
2	* Copyright (c) 2007 Michal Kebrt	2	* Copyright (c) 2007 Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35		35
36	#include <arch.h>	36	#include <arch.h>
37	#include <arch/boot.h>	37	#include <arch/boot.h>
38	#include <config.h>	38	#include <config.h>
39	#include <arch/console.h>	39	#include <arch/console.h>
40	#include <ddi/device.h>	40	#include <ddi/device.h>
41	#include <genarch/fb/fb.h>	41	#include <genarch/fb/fb.h>
42	#include <genarch/fb/visuals.h>	42	#include <genarch/fb/visuals.h>
43	#include <ddi/irq.h>	43	#include <ddi/irq.h>
44		44
45	#include <arch/debug_print/print.h>	45	#include <arch/debug_print/print.h>
46	#include <print.h>	46	#include <print.h>
47	#include <config.h>	47	#include <config.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49	#include <arch/regutils.h>	49	#include <arch/regutils.h>
50	#include <arch/machine.h>	50	#include <arch/machine.h>
51	#include <userspace.h>	51	#include <userspace.h>
52		52
53	bootinfo_t bootinfo;	53	bootinfo_t bootinfo;
54	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;	54	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;
55	extern uintptr_t supervisor_sp;	55	extern uintptr_t supervisor_sp;
56		56
57	//TODO: Remove include and move into exceptio.c	57	//TODO: Remove include and move into exceptio.c
58	#include <arch/exception.h>	58	#include <arch/exception.h>
59		59
60	#include <syscall/syscall.h>	60	#include <syscall/syscall.h>
61	void tmp_swi_exception(int exc_no, istate_t* istate);	61	void tmp_swi_exception(int exc_no, istate_t* istate);
62	void tmp_swi_exception(int exc_no, istate_t* istate)	62	void tmp_swi_exception(int exc_no, istate_t* istate)
63	{	63	{
64	ASSERT(exc_no == EXC_SWI);	64	ASSERT(exc_no == EXC_SWI);
65	ASSERT(istate);	65	ASSERT(istate);
66	// TODO: Alf ... remove aftet swi_exception is tested	66	// TODO: Alf ... remove aftet swi_exception is tested
67	dprintf("\nSWI - istate dump input :\n");	67	dprintf("\nSWI - istate dump input :\n");
68	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);	68	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);
69	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);	69	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);
70	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);	70	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);
71	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);	71	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);
72	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);	72	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
73	// call kernel to serve syscall	73	// call kernel to serve syscall
74	istate->r0 = syscall_handler(	74	istate->r0 = syscall_handler(
75	istate->r0,	75	istate->r0,
76	istate->r1,	76	istate->r1,
77	istate->r2,	77	istate->r2,
78	istate->r3,	78	istate->r3,
79	istate->r4);	79	istate->r4);
80		80
81	// TODO: Alf ... remove aftet swi_exception is tested	81	// TODO: Alf ... remove aftet swi_exception is tested
82	dprintf("\nSWI - Istate dump after :\n");	82	dprintf("\nSWI - Istate dump after :\n");
83	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);	83	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);
84	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);	84	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);
85	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);	85	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);
86	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);	86	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);
87	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);	87	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
88	}	88	}
89		89
90		90
91	void arch_pre_main(void)	91	void arch_pre_main(void)
92	{	92	{
93	int i;	93	int i;
94		94
95	init.cnt = bootinfo.cnt;	95	init.cnt = bootinfo.cnt;
96		96
97	for (i = 0; i < bootinfo.cnt; ++i) {	97	for (i = 0; i < bootinfo.cnt; ++i) {
98	init.tasks[i].addr = bootinfo.tasks[i].addr;	98	init.tasks[i].addr = bootinfo.tasks[i].addr;
99	init.tasks[i].size = bootinfo.tasks[i].size;	99	init.tasks[i].size = bootinfo.tasks[i].size;
100	}	100	}
101		101
102	}	102	}
103		103
104	void arch_pre_mm_init(void)	104	void arch_pre_mm_init(void)
105	{	105	{
106	/* It is not assumed by default */	106	/* It is not assumed by default */
107	interrupts_disable();	107	interrupts_disable();
108		108
109	setup_exception_stacks();	109	setup_exception_stacks();
110		110
111	}	111	}
112		112
113	void prefetch_exception_generator(void);	113	void prefetch_exception_generator(void);
114		114
115	void arch_post_mm_init(void)	115	void arch_post_mm_init(void)
116	{	116	{
117	machine_hw_map_init();	117	machine_hw_map_init();
118		118
119	/* Initialize dispatch table */	119	/* Initialize dispatch table */
120	exception_init();	120	exception_init();
121		121
122	interrupt_init();	122	interrupt_init();
123		123
124	console_init(device_assign_devno());	124	console_init(device_assign_devno());
125		125
126	//fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);	126	//fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);
127		127
128	interrupts_enable();	128	interrupts_enable();
129	}	129	}
130		130
131	void arch_post_cpu_init(void)	131	void arch_post_cpu_init(void)
132	{	132	{
133	/* TODO */	133	/* TODO */
134	}	134	}
135		135
136	void arch_pre_smp_init(void)	136	void arch_pre_smp_init(void)
137	{	137	{
138	/* TODO */	138	/* TODO */
139	}	139	}
140		140
141	void arch_post_smp_init(void)	141	void arch_post_smp_init(void)
142	{	142	{
143	/* TODO */	143	/* TODO */
144	}	144	}
145		145
146	/** Perform arm32 specific tasks needed before the new task is run. */	146	/** Perform arm32 specific tasks needed before the new task is run. */
147	void before_task_runs_arch(void)	147	void before_task_runs_arch(void)
148	{	148	{
149	/* TODO */	149	/* TODO */
150	}	150	}
151		151
152	/** Perform arm32 specific tasks needed before the new thread is scheduled. */	152	/** Perform arm32 specific tasks needed before the new thread is scheduled. */
153	void before_thread_runs_arch(void)	153	void before_thread_runs_arch(void)
154	{	154	{
155	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];	155	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
156	}	156	}
157		157
158	void after_thread_ran_arch(void)	158	void after_thread_ran_arch(void)
159	{	159	{
160	/* TODO */	160	/* TODO */
161	}	161	}
162		162
163	/** Struct to hold general purpose register values */	163	/** Struct to hold general purpose register values */
164	typedef struct {	164	typedef struct {
165	uint32_t r0;	165	uint32_t r0;
166	uint32_t r1;	166	uint32_t r1;
167	uint32_t r2;	167	uint32_t r2;
168	uint32_t r3;	168	uint32_t r3;
169	uint32_t r4;	169	uint32_t r4;
170	uint32_t r5;	170	uint32_t r5;
171	uint32_t r6;	171	uint32_t r6;
172	uint32_t r7;	172	uint32_t r7;
173	uint32_t r8;	173	uint32_t r8;
174	uint32_t r9;	174	uint32_t r9;
175	uint32_t r10;	175	uint32_t r10;
176	uint32_t r11;	176	uint32_t r11;
177	uint32_t r12;	177	uint32_t r12;
178	uint32_t sp;	178	uint32_t sp;
179	uint32_t lr;	179	uint32_t lr;
180	uint32_t pc;	180	uint32_t pc;
181	} ustate_t;	181	} ustate_t;
182		182
183		183
184	void prefetch_exception_generator(void) {	184	void prefetch_exception_generator(void) {
185	asm __volatile__ (	185	asm __volatile__ (
186	"ldr pc, =0x7000000"	186	"ldr pc, =0x7000000"
187	);	187	);
188		188
189	}	189	}
190		190
191	/** Change processor mode and jump into addres specified in	191	/** Change processor mode and jump into addres specified in
192	* kernel_uarg.uspace_entry	192	* kernel_uarg.uspace_entry
193	* \param kernel_uarg information needed for correct setting of userspace	193	* \param kernel_uarg information needed for correct setting of userspace
194	*/	194	*/
195	void userspace(uspace_arg_t *kernel_uarg)	195	void userspace(uspace_arg_t *kernel_uarg)
196	{	196	{
197	dprintf("userspace\n");	197	dprintf("userspace\n");
198		198
199	dprintf("userspce krnl_uard .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",	199	dprintf("userspce krnl_uard .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
200	(unsigned int)(kernel_uarg->uspace_uarg),	200	(unsigned int)(kernel_uarg->uspace_uarg),
201	kernel_uarg->uspace_entry,	201	kernel_uarg->uspace_entry,
202	kernel_uarg->uspace_stack);	202	kernel_uarg->uspace_stack);
203		203
204	volatile ustate_t ustate;	204	volatile ustate_t ustate;
205		205
206	//Step 1 ... prepare user space environment	206	//Step 1 ... prepare user space environment
207	//set first paramater	207	//set first paramater
208	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;	208	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
209		209
210	//clear other registers	210	//clear other registers
211	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =	211	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =
212	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =	212	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =
213	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;	213	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
214	ustate.lr = 3;	214	ustate.lr = 3;
215		215
216	//set user stack	216	//set user stack
217	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;	217	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;
218		218
219	//set where uspace executin starts	219	//set where uspace executin starts
220	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;	220	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
221		221
222		222
223	//status register in user mode	223	//status register in user mode
224	ipl_t cpsr = current_status_reg_read();	224	ipl_t cpsr = current_status_reg_read();
225	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;	225	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;
226		226
227	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| SUPERVISOR_MODE;	227	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| SUPERVISOR_MODE;
228		228
229	asm __volatile__ (	229	asm __volatile__ (
230	// save pointer into ustate struct	230	// save pointer into ustate struct
231	"mov r0, %0 \n"	231	"mov r0, %0 \n"
232	// save cspr	232	// save cspr
233	"mov r1, %1 \n"	233	"mov r1, %1 \n"
234	// change mode into any exception mode	234	// change mode into any exception mode
235	"msr cpsr_c, %2 \n"	235	"msr cpsr_c, %2 \n"
236	// set saved cpsr	236	// set saved cpsr
237	"msr spsr_c, r1 \n"	237	"msr spsr_c, r1 \n"
238		238
239	"mov sp, r0 \n"	239	"mov sp, r0 \n"
240	// replace almost all registers	240	// replace almost all registers
241	"ldmfd sp!, {r0-r12, sp, lr}^\n"	241	"ldmfd sp!, {r0-r12, sp, lr}^\n"
242	//jump to the usermode	242	//jump to the usermode
243	"ldmfd sp!, {pc}^"	243	"ldmfd sp!, {pc}^"
244	: // no output	244	: // no output
245	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //	245	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
246	: "r0","r1"	246	: "r0","r1"
247	);	247	);
248		248
249	while(1) ;	249	while(1) ;
250	}	250	}
-		251
-		252
-		253	void cpu_halt(void)
-		254	{
-		255	machine_cpu_halt();
-		256	}
-		257
251	/** @}	258	/** @}
252	*/	259	*/
253		260
254		261
255		262
256		263
257		264
258		265
259		266
260		267
261		268
262		269
263		270
264		271
265		272
266		273
267		274

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