WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/src/arm32.c


/*
 * Copyright (c) 2007 Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 */
 
 
#include <arch.h>
#include <arch/boot.h>
#include <config.h>
#include <arch/console.h>
#include <ddi/device.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <ddi/irq.h>
 
#include <arch/debug_print/print.h>
#include <print.h>
#include <config.h>
#include <interrupt.h>
#include <arch/regutils.h>
#include <arch/machine.h>
#include <userspace.h>
 
bootinfo_t bootinfo;
// // uintptr_t supervisor_sp /*__attribute__ ((section (".text")))*/;
extern uintptr_t supervisor_sp;
 
//TODO: Remove include and move into exceptio.c
#include <arch/exception.h>
 
#include <syscall/syscall.h>
void tmp_swi_exception(int exc_no, istate_t* istate);
void tmp_swi_exception(int exc_no, istate_t* istate)
{
    ASSERT(exc_no == EXC_SWI);
    ASSERT(istate);
    // TODO: Alf ... remove aftet swi_exception is tested
    dprintf("\nSWI - istate dump input :\n");
    dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
    dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
    dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
    dprintf("   r12:%X    r13:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
//  dprintf("   prev_lr:%X    prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
    // call kernel to serve syscall
    istate->r0 = syscall_handler(
        istate->r0,
        istate->r1,
        istate->r2,
        istate->r3,
        istate->r4);
 
    // TODO: Alf ... remove aftet swi_exception is tested
    dprintf("\nSWI - Istate dump after :\n");
    dprintf("    r0:%X    r1:%X    r2:%X    r3:%X\n", istate->r0,  istate->r1, istate->r2,  istate->r3);
    dprintf("    r4:%X    r5:%X    r6:%X    r7:%X\n", istate->r4,  istate->r5, istate->r6,  istate->r7);
    dprintf("    r8:%X    r8:%X   r10:%X   r11:%X\n", istate->r8,  istate->r9, istate->r10, istate->r11);
    dprintf("   r12:%X    r13:%X    lr:%X  spsr:%X\n", istate->r12, istate->sp, istate->lr,  istate->spsr);
//  dprintf("   prev_lr:%X    prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
}
 
 
void arch_pre_main(void)
{
    int i;
 
    init.cnt = bootinfo.cnt;
 
    for (i = 0; i < bootinfo.cnt; ++i) {
        init.tasks[i].addr = bootinfo.tasks[i].addr;
        init.tasks[i].size = bootinfo.tasks[i].size;
    }
 
}
 
void arch_pre_mm_init(void)
{
    /* It is not assumed by default */
    interrupts_disable();
 
    setup_exception_stacks();
 
}
 
void prefetch_exception_generator(void);
 
void arch_post_mm_init(void)
{
    machine_hw_map_init();
 
    /* Initialize dispatch table */
    exception_init();
 
    interrupt_init();
   
    console_init(device_assign_devno());
   
    //fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);
   
    interrupts_enable();
}
 
void arch_post_cpu_init(void)
{
    /* TODO */
}
 
void arch_pre_smp_init(void)
{
    /* TODO */
}
 
void arch_post_smp_init(void)
{
    /* TODO */
}
 
/** Perform arm32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
    /* TODO */
}
 
/** Perform arm32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
    supervisor_sp = (uintptr_t) &THREAD->kstack/*[THREAD_STACK_SIZE-SP_DELTA]*/;
}
 
void after_thread_ran_arch(void)
{
    /* TODO */
}
 
/** Struct to hold general purpose register values */
typedef struct {
    uint32_t r0;
    uint32_t r1;
    uint32_t r2;
    uint32_t r3;
    uint32_t r4;
    uint32_t r5;
    uint32_t r6;
    uint32_t r7;
    uint32_t r8;
    uint32_t r9;
    uint32_t r10;
    uint32_t r11;
    uint32_t r12;
    uint32_t sp;
    uint32_t lr;
    uint32_t pc;
} ustate_t;
 
 
void prefetch_exception_generator(void)  {
 asm __volatile__ (
    "ldr pc, =0x7000000"
 );
 
}
 
/** Change processor mode and jump into addres specified in
 *  kernel_uarg.uspace_entry
 * \param kernel_uarg information needed for correct setting of userspace
 */
void userspace(uspace_arg_t *kernel_uarg)
{
//  dprintf("userspace\n");
// WILL be changed .. after exception return .. eret will be done
/*
        volatile ustate_t ustate;
    dprintf("userspce krnl_uard  .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
      (unsigned int)(kernel_uarg->uspace_uarg),
      kernel_uarg->uspace_entry,
      kernel_uarg->uspace_stack);
    // Step 1 ... prepare user space environmen
    // set first paramater
    ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
    // clear other registers
    ustate.r1 = ustate.r2  = ustate.r3  = ustate.r4  =
        ustate.r5 = ustate.r6  = ustate.r7  = ustate.r8  =
        ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
        ustate.lr = 3;
        // set user stack
        ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;
        // set where uspace executin starts
        ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
 
    // status register in user mode
    ipl_t cpsr = current_status_reg_read();
        cpsr &= ~STATUS_REG_MODE_MASK | USER_MODE;
    //
    ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) | ABORT_MODE;
 
    asm __volatile__ (
        "mov r0, %0        \n" // save pointer into ustate struct
        "mov r1, %1        \n" // save cspr
        "msr cpsr_c, %2    \n" // change mode into any exception mode
        "msr spsr_c, r1    \n" // set saved cpsr ... as user mode
        "ldmfd r0, {r0-r12, sp, lr, pc}^\n" // jump into user mode
    : // no output
    : "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
    : "r0","r1"
    );
*/
    while(1)
        ;
       
}
/** @}
 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Rev 2290	Rev 2294
1	/*	1	/*
2	* Copyright (c) 2007 Michal Kebrt	2	* Copyright (c) 2007 Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35		35
36	#include <arch.h>	36	#include <arch.h>
37	#include <arch/boot.h>	37	#include <arch/boot.h>
38	#include <config.h>	38	#include <config.h>
39	#include <arch/console.h>	39	#include <arch/console.h>
40	#include <ddi/device.h>	40	#include <ddi/device.h>
41	#include <genarch/fb/fb.h>	41	#include <genarch/fb/fb.h>
42	#include <genarch/fb/visuals.h>	42	#include <genarch/fb/visuals.h>
43	#include <ddi/irq.h>	43	#include <ddi/irq.h>
44		44
45	#include <arch/debug_print/print.h>	45	#include <arch/debug_print/print.h>
46	#include <print.h>	46	#include <print.h>
47	#include <config.h>	47	#include <config.h>
48	#include <interrupt.h>	48	#include <interrupt.h>
49	#include <arch/regutils.h>	49	#include <arch/regutils.h>
50	#include <arch/drivers/gxemul.h>	50	#include <arch/machine.h>
51	#include <userspace.h>	51	#include <userspace.h>
52		52
53	bootinfo_t bootinfo;	53	bootinfo_t bootinfo;
54	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;	54	// // uintptr_t supervisor_sp /__attribute__ ((section (".text")))/;
55	extern uintptr_t supervisor_sp;	55	extern uintptr_t supervisor_sp;
56		56
57	//TODO: Remove include and move into exceptio.c	57	//TODO: Remove include and move into exceptio.c
58	#include <arch/exception.h>	58	#include <arch/exception.h>
59		59
60	#include <syscall/syscall.h>	60	#include <syscall/syscall.h>
61	void tmp_swi_exception(int exc_no, istate_t* istate);	61	void tmp_swi_exception(int exc_no, istate_t* istate);
62	void tmp_swi_exception(int exc_no, istate_t* istate)	62	void tmp_swi_exception(int exc_no, istate_t* istate)
63	{	63	{
64	ASSERT(exc_no == EXC_SWI);	64	ASSERT(exc_no == EXC_SWI);
65	ASSERT(istate);	65	ASSERT(istate);
66	// TODO: Alf ... remove aftet swi_exception is tested	66	// TODO: Alf ... remove aftet swi_exception is tested
67	dprintf("\nSWI - istate dump input :\n");	67	dprintf("\nSWI - istate dump input :\n");
68	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);	68	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);
69	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);	69	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);
70	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);	70	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);
71	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);	71	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);
72	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);	72	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
73	// call kernel to serve syscall	73	// call kernel to serve syscall
74	istate->r0 = syscall_handler(	74	istate->r0 = syscall_handler(
75	istate->r0,	75	istate->r0,
76	istate->r1,	76	istate->r1,
77	istate->r2,	77	istate->r2,
78	istate->r3,	78	istate->r3,
79	istate->r4);	79	istate->r4);
80		80
81	// TODO: Alf ... remove aftet swi_exception is tested	81	// TODO: Alf ... remove aftet swi_exception is tested
82	dprintf("\nSWI - Istate dump after :\n");	82	dprintf("\nSWI - Istate dump after :\n");
83	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);	83	dprintf(" r0:%X r1:%X r2:%X r3:%X\n", istate->r0, istate->r1, istate->r2, istate->r3);
84	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);	84	dprintf(" r4:%X r5:%X r6:%X r7:%X\n", istate->r4, istate->r5, istate->r6, istate->r7);
85	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);	85	dprintf(" r8:%X r8:%X r10:%X r11:%X\n", istate->r8, istate->r9, istate->r10, istate->r11);
86	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);	86	dprintf(" r12:%X r13:%X lr:%X spsr:%X\n", istate->r12, istate->sp, istate->lr, istate->spsr);
87	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);	87	// dprintf(" prev_lr:%X prev_sp:%X\n", istate->r12, istate->prev_lr, istate->prev_sp);
88	}	88	}
89		89
90		90
91	void arch_pre_main(void)	91	void arch_pre_main(void)
92	{	92	{
93	int i;	93	int i;
94		94
95	init.cnt = bootinfo.cnt;	95	init.cnt = bootinfo.cnt;
96		96
97	for (i = 0; i < bootinfo.cnt; ++i) {	97	for (i = 0; i < bootinfo.cnt; ++i) {
98	init.tasks[i].addr = bootinfo.tasks[i].addr;	98	init.tasks[i].addr = bootinfo.tasks[i].addr;
99	init.tasks[i].size = bootinfo.tasks[i].size;	99	init.tasks[i].size = bootinfo.tasks[i].size;
100	}	100	}
-		101
101	}	102	}
102		103
103	void arch_pre_mm_init(void)	104	void arch_pre_mm_init(void)
104	{	105	{
105	/* It is not assumed by default */	106	/* It is not assumed by default */
106	interrupts_disable();	107	interrupts_disable();
107		108
108	setup_exception_stacks();	109	setup_exception_stacks();
-		110
109	}	111	}
110		112
111	void prefetch_exception_generator(void);	113	void prefetch_exception_generator(void);
112		114
113	void arch_post_mm_init(void)	115	void arch_post_mm_init(void)
114	{	116	{
115	gxemul_hw_map_init();	117	machine_hw_map_init();
116		118
117	/* Initialize dispatch table */	119	/* Initialize dispatch table */
118	exception_init();	120	exception_init();
119		121
120	interrupt_init();	122	interrupt_init();
121		123
122	console_init(device_assign_devno());	124	console_init(device_assign_devno());
123		125
124	//fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);	126	//fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);
125		127
126	interrupts_enable();	128	interrupts_enable();
127	}	129	}
128		130
129	void arch_post_cpu_init(void)	131	void arch_post_cpu_init(void)
130	{	132	{
131	/* TODO */	133	/* TODO */
132	}	134	}
133		135
134	void arch_pre_smp_init(void)	136	void arch_pre_smp_init(void)
135	{	137	{
136	/* TODO */	138	/* TODO */
137	}	139	}
138		140
139	void arch_post_smp_init(void)	141	void arch_post_smp_init(void)
140	{	142	{
141	/* TODO */	143	/* TODO */
142	}	144	}
143		145
144	/** Perform arm32 specific tasks needed before the new task is run. */	146	/** Perform arm32 specific tasks needed before the new task is run. */
145	void before_task_runs_arch(void)	147	void before_task_runs_arch(void)
146	{	148	{
147	/* TODO */	149	/* TODO */
148	}	150	}
149		151
150	/** Perform arm32 specific tasks needed before the new thread is scheduled. */	152	/** Perform arm32 specific tasks needed before the new thread is scheduled. */
151	void before_thread_runs_arch(void)	153	void before_thread_runs_arch(void)
152	{	154	{
153	supervisor_sp = (uintptr_t) &THREAD->kstack/[THREAD_STACK_SIZE-SP_DELTA]/;	155	supervisor_sp = (uintptr_t) &THREAD->kstack/[THREAD_STACK_SIZE-SP_DELTA]/;
154	}	156	}
155		157
156	void after_thread_ran_arch(void)	158	void after_thread_ran_arch(void)
157	{	159	{
158	/* TODO */	160	/* TODO */
159	}	161	}
160		162
161	/** Struct to hold general purpose register values */	163	/** Struct to hold general purpose register values */
162	typedef struct {	164	typedef struct {
163	uint32_t r0;	165	uint32_t r0;
164	uint32_t r1;	166	uint32_t r1;
165	uint32_t r2;	167	uint32_t r2;
166	uint32_t r3;	168	uint32_t r3;
167	uint32_t r4;	169	uint32_t r4;
168	uint32_t r5;	170	uint32_t r5;
169	uint32_t r6;	171	uint32_t r6;
170	uint32_t r7;	172	uint32_t r7;
171	uint32_t r8;	173	uint32_t r8;
172	uint32_t r9;	174	uint32_t r9;
173	uint32_t r10;	175	uint32_t r10;
174	uint32_t r11;	176	uint32_t r11;
175	uint32_t r12;	177	uint32_t r12;
176	uint32_t sp;	178	uint32_t sp;
177	uint32_t lr;	179	uint32_t lr;
178	uint32_t pc;	180	uint32_t pc;
179	} ustate_t;	181	} ustate_t;
180		182
181		183
182	void prefetch_exception_generator(void) {	184	void prefetch_exception_generator(void) {
183	asm __volatile__ (	185	asm __volatile__ (
184	"ldr pc, =0x7000000"	186	"ldr pc, =0x7000000"
185	);	187	);
186		188
187	}	189	}
188		190
189	/** Change processor mode and jump into addres specified in	191	/** Change processor mode and jump into addres specified in
190	* kernel_uarg.uspace_entry	192	* kernel_uarg.uspace_entry
191	* \param kernel_uarg information needed for correct setting of userspace	193	* \param kernel_uarg information needed for correct setting of userspace
192	*/	194	*/
193	void userspace(uspace_arg_t *kernel_uarg)	195	void userspace(uspace_arg_t *kernel_uarg)
194	{	196	{
-		197	// dprintf("userspace\n");
195	// WILL be changed .. after exception return .. eret will be done	198	// WILL be changed .. after exception return .. eret will be done
196	/*	199	/*
197	volatile ustate_t ustate;	200	volatile ustate_t ustate;
198	dprintf("userspce krnl_uard .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",	201	dprintf("userspce krnl_uard .uspace_uarg(%X), .uspace_entry(%X), .uspace_stack(%X)\n",
199	(unsigned int)(kernel_uarg->uspace_uarg),	202	(unsigned int)(kernel_uarg->uspace_uarg),
200	kernel_uarg->uspace_entry,	203	kernel_uarg->uspace_entry,
201	kernel_uarg->uspace_stack);	204	kernel_uarg->uspace_stack);
202	// Step 1 ... prepare user space environmen	205	// Step 1 ... prepare user space environmen
203	// set first paramater	206	// set first paramater
204	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;	207	ustate.r0 = (uintptr_t) kernel_uarg->uspace_uarg;
205	// clear other registers	208	// clear other registers
206	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =	209	ustate.r1 = ustate.r2 = ustate.r3 = ustate.r4 =
207	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =	210	ustate.r5 = ustate.r6 = ustate.r7 = ustate.r8 =
208	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;	211	ustate.r9 = ustate.r10 = ustate.r11 = ustate.r12 = 1;
209	ustate.lr = 3;	212	ustate.lr = 3;
210	// set user stack	213	// set user stack
211	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;	214	ustate.sp = ((uint32_t)kernel_uarg->uspace_stack)+PAGE_SIZE;
212	// set where uspace executin starts	215	// set where uspace executin starts
213	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;	216	ustate.pc = (uintptr_t) kernel_uarg->uspace_entry;
214		217
215	// status register in user mode	218	// status register in user mode
216	ipl_t cpsr = current_status_reg_read();	219	ipl_t cpsr = current_status_reg_read();
217	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;	220	cpsr &= ~STATUS_REG_MODE_MASK \| USER_MODE;
218	//	221	//
219	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE;	222	ipl_t tmpsr = (cpsr & ~STATUS_REG_MODE_MASK) \| ABORT_MODE;
220		223
221	asm __volatile__ (	224	asm __volatile__ (
222	"mov r0, %0 \n" // save pointer into ustate struct	225	"mov r0, %0 \n" // save pointer into ustate struct
223	"mov r1, %1 \n" // save cspr	226	"mov r1, %1 \n" // save cspr
224	"msr cpsr_c, %2 \n" // change mode into any exception mode	227	"msr cpsr_c, %2 \n" // change mode into any exception mode
225	"msr spsr_c, r1 \n" // set saved cpsr ... as user mode	228	"msr spsr_c, r1 \n" // set saved cpsr ... as user mode
226	"ldmfd r0, {r0-r12, sp, lr, pc}^\n" // jump into user mode	229	"ldmfd r0, {r0-r12, sp, lr, pc}^\n" // jump into user mode
227	: // no output	230	: // no output
228	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //	231	: "r"(&ustate), "r"(cpsr), "r"(tmpsr) //
229	: "r0","r1"	232	: "r0","r1"
230	);	233	);
231	*/	234	*/
232	while(1)	235	while(1)
233	;	236	;
234		237
235	}	238	}
236	/** @}	239	/** @}
237	*/	240	*/
238		241
239		242
240		243
241		244
242		245
243		246
244		247
245		248
246		249
247		250
248		251
249		252
250		253
251		254
252		255

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