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1 | /* |
1 | /* |
2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** |
32 | /** |
33 | * @file |
33 | * @file |
34 | * @brief Utilities for convenient manipulation with ARM registries. |
34 | * @brief Utilities for convenient manipulation with ARM registries. |
35 | */ |
35 | */ |
36 | 36 | ||
37 | #ifndef KERN_arm32_REGUTILS_H_ |
37 | #ifndef KERN_arm32_REGUTILS_H_ |
38 | #define KERN_arm32_REGUTILS_H_ |
38 | #define KERN_arm32_REGUTILS_H_ |
39 | 39 | ||
- | 40 | ||
40 | #define status_reg_ie_enabled_bit (1 << 7) |
41 | #define STATUS_REG_IE_ENABLED_BIT (1 << 7) |
- | 42 | #define STATUS_REG_MODE_MASK 0x1F |
|
- | 43 | ||
- | 44 | /* ARM Processor Operation Modes */ |
|
- | 45 | #define USER_MODE 0x10 |
|
- | 46 | #define FIQ_MODE 0x11 |
|
- | 47 | #define IRQ_MODE 0x12 |
|
- | 48 | #define SUPERVISOR_MODE 0x13 |
|
- | 49 | #define ABORT_MODE 0x17 |
|
- | 50 | #define UNDEFINED_MODE 0x1b |
|
- | 51 | #define SYSTEM_MODE 0x1f |
|
- | 52 | ||
- | 53 | ||
- | 54 | ||
- | 55 | /* [CS]PRS manipulation macros */ |
|
- | 56 | #define GEN_STATUS_READ(nm,reg) \ |
|
- | 57 | static inline uint32_t nm## _status_reg_read(void) \ |
|
- | 58 | { \ |
|
- | 59 | uint32_t retval; \ |
|
- | 60 | asm("mrs %0, " #reg : "=r"(retval)); \ |
|
- | 61 | return retval; \ |
|
- | 62 | } |
|
- | 63 | ||
- | 64 | #define GEN_STATUS_WRITE(nm,reg,fieldname, field) \ |
|
- | 65 | static void nm## _status_reg_ ##fieldname## _write(uint32_t value) \ |
|
- | 66 | { \ |
|
- | 67 | asm("msr " #reg "_" #field ", %0" : : "r"(value)); \ |
|
- | 68 | } |
|
- | 69 | ||
41 | 70 | ||
42 | /** Returns the value of CPSR (Current Program Status Register). |
71 | /** Returns the value of CPSR (Current Program Status Register). |
43 | */ |
72 | */ |
44 | static inline ipl_t status_reg_read (void) { |
- | |
45 | ipl_t ipl; |
- | |
46 | asm("mrs %0, CPSR" : "=r" (ipl)); |
73 | GEN_STATUS_READ(current, cpsr) |
47 | return ipl; |
- | |
48 | } |
74 | |
49 | 75 | ||
50 | /** Sets control bits of CPSR |
76 | /** Sets control bits of CPSR |
51 | */ |
77 | */ |
- | 78 | GEN_STATUS_WRITE(current, cpsr, control, c); |
|
- | 79 | ||
- | 80 | ||
52 | static inline void status_reg_control_write(ipl_t ipl) { |
81 | /** Returns the value of SPSR (Saved Program Status Register). |
- | 82 | */ |
|
53 | asm("msr CPSR_c, %0" : : "r" (ipl)); |
83 | GEN_STATUS_READ(saved, spsr) |
- | 84 | ||
54 | } |
85 | |
55 | 86 | ||
56 | #endif |
87 | #endif |
57 | 88 | ||
58 | /** @} |
89 | /** @} |
59 | */ |
90 | */ |
60 | 91 |