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/*
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/*
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 * Copyright (c) 2007 Petr Stepan
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 * Copyright (c) 2007 Petr Stepan
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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/** @addtogroup arm32  
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/** @addtogroup arm32  
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 * @{
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 * @{
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 */
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 */
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/**
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/**
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 * @file
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 * @file
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 * @brief   Utilities for convenient manipulation with ARM registries.
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 * @brief   Utilities for convenient manipulation with ARM registries.
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 */
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 */
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#ifndef KERN_arm32_REGUTILS_H_
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#ifndef KERN_arm32_REGUTILS_H_
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#define KERN_arm32_REGUTILS_H_
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#define KERN_arm32_REGUTILS_H_
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- 
 
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#define status_reg_ie_enabled_bit   (1 << 7)
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#define STATUS_REG_IE_ENABLED_BIT   (1 << 7)
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#define STATUS_REG_MODE_MASK        0x1F
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/* ARM Processor Operation Modes */
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#define USER_MODE           0x10
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#define FIQ_MODE            0x11
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#define IRQ_MODE            0x12
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#define SUPERVISOR_MODE         0x13
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#define ABORT_MODE          0x17
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#define UNDEFINED_MODE          0x1b
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#define SYSTEM_MODE         0x1f
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/* [CS]PRS manipulation macros */
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#define GEN_STATUS_READ(nm,reg) \
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  static inline uint32_t nm## _status_reg_read(void) \
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  { \
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      uint32_t retval; \
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      asm("mrs %0, " #reg : "=r"(retval)); \
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      return retval; \
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  }
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#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
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  static void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
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  { \
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      asm("msr " #reg "_" #field ", %0" : : "r"(value)); \
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  }
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/** Returns the value of CPSR (Current Program Status Register).
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/** Returns the value of CPSR (Current Program Status Register).
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*/
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*/
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static inline ipl_t status_reg_read (void) {
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    ipl_t ipl;
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    asm("mrs %0, CPSR" : "=r" (ipl));
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GEN_STATUS_READ(current, cpsr)
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    return ipl;
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}
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/** Sets control bits of CPSR  
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/** Sets control bits of CPSR  
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*/
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*/
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GEN_STATUS_WRITE(current, cpsr, control, c);
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static inline void status_reg_control_write(ipl_t ipl) {
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/** Returns the value of SPSR (Saved Program Status Register).
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*/
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    asm("msr CPSR_c, %0" : : "r" (ipl));
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GEN_STATUS_READ(saved, spsr)
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}
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#endif
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#endif
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/** @}
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/** @}
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 */
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 */
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