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1 | /* |
1 | /* |
2 | * Copyright (c) 2003-2007 Jakub Jermar |
2 | * Copyright (c) 2003-2007 Jakub Jermar |
3 | * All rights reserved. |
3 | * All rights reserved. |
4 | * |
4 | * |
5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
7 | * are met: |
7 | * are met: |
8 | * |
8 | * |
9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
16 | * |
16 | * |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | */ |
27 | */ |
28 | 28 | ||
29 | /** @addtogroup arm32mm |
29 | /** @addtogroup arm32mm |
30 | * @{ |
30 | * @{ |
31 | */ |
31 | */ |
32 | /** @file |
32 | /** @file |
33 | */ |
33 | */ |
34 | 34 | ||
35 | #ifndef KERN_arm32_PAGE_H_ |
35 | #ifndef KERN_arm32_PAGE_H_ |
36 | #define KERN_arm32_PAGE_H_ |
36 | #define KERN_arm32_PAGE_H_ |
37 | 37 | ||
38 | #include <arch/mm/frame.h> |
38 | #include <arch/mm/frame.h> |
39 | #include <mm/mm.h> |
39 | #include <mm/mm.h> |
40 | #include <arch/exception.h> |
40 | #include <arch/exception.h> |
41 | 41 | ||
42 | 42 | ||
43 | #define PAGE_WIDTH FRAME_WIDTH |
43 | #define PAGE_WIDTH FRAME_WIDTH |
44 | #define PAGE_SIZE FRAME_SIZE |
44 | #define PAGE_SIZE FRAME_SIZE |
45 | 45 | ||
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
46 | #define PAGE_COLOR_BITS 0 /* dummy */ |
47 | 47 | ||
48 | #ifndef __ASM__ |
48 | #ifndef __ASM__ |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
49 | # define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
50 | # define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) |
51 | #else |
51 | #else |
52 | # define KA2PA(x) ((x) - 0x80000000) |
52 | # define KA2PA(x) ((x) - 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
53 | # define PA2KA(x) ((x) + 0x80000000) |
54 | #endif |
54 | #endif |
55 | 55 | ||
56 | #ifdef KERNEL |
56 | #ifdef KERNEL |
57 | // Using small pages <==> 4kb |
57 | // Using small pages <==> 4kb |
58 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
58 | #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
59 | #define PTL1_ENTRIES_ARCH 0 |
59 | #define PTL1_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
60 | #define PTL2_ENTRIES_ARCH 0 |
61 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
61 | #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
62 | 62 | ||
63 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
63 | #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) |
64 | #define PTL1_INDEX_ARCH(vaddr) 0 |
64 | #define PTL1_INDEX_ARCH(vaddr) 0 |
65 | #define PTL2_INDEX_ARCH(vaddr) 0 |
65 | #define PTL2_INDEX_ARCH(vaddr) 0 |
66 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
66 | #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) |
67 | 67 | ||
68 | 68 | ||
69 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
69 | #define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 )) |
70 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
70 | #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) |
71 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
71 | #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) |
72 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
72 | #define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 )) |
73 | 73 | ||
74 | #define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_t *)(ptl0)) ) |
74 | #define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_t *)(ptl0)) ) |
75 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
75 | #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10) |
76 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
76 | #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) |
77 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
77 | #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) |
78 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
78 | #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12) |
79 | 79 | ||
80 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
80 | #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i)) |
81 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
81 | #define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT |
82 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
82 | #define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT |
83 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
83 | #define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i)) |
84 | 84 | ||
85 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
85 | #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x)) |
86 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
86 | #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) |
87 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
87 | #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) |
88 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
88 | #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x)) |
89 | 89 | ||
90 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
90 | #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) |
91 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
91 | #define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type ) |
92 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3 |
92 | #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3 |
93 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3 |
93 | #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3 |
94 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
94 | #define PTE_EXECUTABLE_ARCH(pte) 1 |
95 | 95 | ||
96 | #ifndef __ASM__ |
96 | #ifndef __ASM__ |
97 | 97 | ||
98 | /** Set adress of paging level 0 table |
98 | /** Set adress of paging level 0 table |
99 | * \param pt pointer to page table to set |
99 | * \param pt pointer to page table to set |
100 | */ |
100 | */ |
101 | static inline void set_ptl0_addr( pte_level0_t* pt){ |
101 | static inline void set_ptl0_addr( pte_level0_t* pt){ |
102 | asm volatile ( "mrc p15, 0, %0, c2, c0, 0 \n" |
102 | asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n" |
103 | : |
103 | : |
104 | : "r"(pt) |
104 | : "r"(pt) |
105 | ); |
105 | ); |
106 | 106 | ||
107 | } |
107 | } |
108 | 108 | ||
109 | //TODO Comment: Page table structure as in other architectures |
109 | //TODO Comment: Page table structure as in other architectures |
110 | 110 | ||
111 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
111 | static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) |
112 | { |
112 | { |
113 | pte_level0_t *p = &pt[i]; |
113 | pte_level0_t *p = &pt[i]; |
114 | 114 | ||
115 | return ( |
115 | return ( |
116 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
116 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
117 | ( 1 << PAGE_READ_SHIFT ) | |
117 | ( 1 << PAGE_READ_SHIFT ) | |
118 | ( 1 << PAGE_EXEC_SHIFT ) | |
118 | ( 1 << PAGE_EXEC_SHIFT ) | |
119 | ( 1 << PAGE_CACHEABLE ) |
119 | ( 1 << PAGE_CACHEABLE ) |
120 | ); |
120 | ); |
121 | 121 | ||
122 | } |
122 | } |
123 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
123 | static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) |
124 | { |
124 | { |
125 | pte_level1_t *p = &pt[i]; |
125 | pte_level1_t *p = &pt[i]; |
126 | 126 | ||
127 | return ( |
127 | return ( |
128 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
128 | ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT | |
129 | ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
129 | ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) | |
130 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
130 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) | |
131 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
131 | ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) | |
132 | ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
132 | ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) | |
133 | ( 1 << PAGE_EXEC_SHIFT ) | |
133 | ( 1 << PAGE_EXEC_SHIFT ) | |
134 | ( p->bufferable << PAGE_CACHEABLE ) |
134 | ( p->bufferable << PAGE_CACHEABLE ) |
135 | 135 | ||
136 | 136 | ||
137 | ); |
137 | ); |
138 | 138 | ||
139 | } |
139 | } |
140 | 140 | ||
141 | 141 | ||
142 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
142 | static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) |
143 | { |
143 | { |
144 | pte_level0_t *p = &pt[i]; |
144 | pte_level0_t *p = &pt[i]; |
145 | 145 | ||
146 | if ( flags & PAGE_NOT_PRESENT ) { |
146 | if ( flags & PAGE_NOT_PRESENT ) { |
147 | p->descriptor_type = pte_descriptor_not_preset; |
147 | p->descriptor_type = pte_descriptor_not_preset; |
148 | p->should_be_zero = 1; |
148 | p->should_be_zero = 1; |
149 | } else |
149 | } else |
150 | { |
150 | { |
151 | p->descriptor_type = pte_descriptor_coarse_table; |
151 | p->descriptor_type = pte_descriptor_coarse_table; |
152 | p->should_be_zero = 0; |
152 | p->should_be_zero = 0; |
153 | } |
153 | } |
154 | return; |
154 | return; |
155 | } |
155 | } |
156 | 156 | ||
157 | /* We use same acess rights for whole page, so if page is set as not preset then |
157 | /* We use same acess rights for whole page, so if page is set as not preset then |
158 | * in acess_rigts_3 set value 1 |
158 | * in acess_rigts_3 set value 1 |
159 | */ |
159 | */ |
160 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
160 | static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) |
161 | { |
161 | { |
162 | pte_level1_t *p = &pt[i]; |
162 | pte_level1_t *p = &pt[i]; |
163 | 163 | ||
164 | if ( flags & PAGE_NOT_PRESENT ) { |
164 | if ( flags & PAGE_NOT_PRESENT ) { |
165 | p->descriptor_type = pte_descriptor_not_preset; |
165 | p->descriptor_type = pte_descriptor_not_preset; |
166 | p->access_permission_3 = 1; |
166 | p->access_permission_3 = 1; |
167 | } else |
167 | } else |
168 | { |
168 | { |
169 | p->descriptor_type = pte_descriptor_coarse_table; |
169 | p->descriptor_type = pte_descriptor_coarse_table; |
170 | p->access_permission_3 = p->access_permission_0; |
170 | p->access_permission_3 = p->access_permission_0; |
171 | } |
171 | } |
172 | 172 | ||
173 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
173 | p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; |
174 | // default kernel rw, user none |
174 | // default kernel rw, user none |
175 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw; |
175 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw; |
176 | if ( flags & PAGE_USER ) { |
176 | if ( flags & PAGE_USER ) { |
177 | if ( flags & PAGE_READ ) |
177 | if ( flags & PAGE_READ ) |
178 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw; |
178 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw; |
179 | if ( flags & PAGE_WRITE ) |
179 | if ( flags & PAGE_WRITE ) |
180 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw; |
180 | p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw; |
181 | } |
181 | } |
182 | return; return; |
182 | return; return; |
183 | } |
183 | } |
184 | 184 | ||
185 | extern void page_arch_init(void); |
185 | extern void page_arch_init(void); |
186 | 186 | ||
187 | #endif /* __ASM__ */ |
187 | #endif /* __ASM__ */ |
188 | 188 | ||
189 | #endif /* KERNEL */ |
189 | #endif /* KERNEL */ |
190 | 190 | ||
191 | #endif |
191 | #endif |
192 | 192 | ||
193 | /** @} |
193 | /** @} |
194 | */ |
194 | */ |
195 | 195 | ||
196 | 196 |