WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/include/mm/page.h


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_arm32_PAGE_H_
#define KERN_arm32_PAGE_H_
 
#include <arch/mm/frame.h>
#include <mm/mm.h>
#include <arch/exception.h>
 
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
#define PAGE_COLOR_BITS 0           /* dummy */
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
#ifdef KERNEL
 
#define PTL0_ENTRIES_ARCH    (2<<12)    // 4096
#define PTL1_ENTRIES_ARCH     0 
#define PTL2_ENTRIES_ARCH     0 
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH    (2<<8)     // 256
 
#define PTL0_SIZE_ARCH       FOUR_FRAMES
#define PTL1_SIZE_ARCH       0
#define PTL2_SIZE_ARCH       0
#define PTL3_SIZE_ARCH       ONE_FRAME
 
#define PTL0_INDEX_ARCH(vaddr)    (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr)    0 
#define PTL2_INDEX_ARCH(vaddr)    0
#define PTL3_INDEX_ARCH(vaddr)    (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
// TODO: ?? != 0
#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) 
 
#define PTE_EXECUTABLE_ARCH(pte)            1
 
#ifndef __ASM__
 
/**
 * Sets the address of level 0 page table.
 *
 * \param pt    pointer to the page table to set
 */  
static inline void set_ptl0_addr( pte_level0_t* pt)
{
    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
        :
        : "r"(pt)
    );
   
}
 
/**
 * Returns level 0 page table entry flags.
 *
 * \param pt     level 0 page table
 * \param i      index of the entry to return
 */
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
    pte_level0_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
        ( 1 << PAGE_USER_SHIFT )  |
        ( 1 << PAGE_READ_SHIFT )  |
        ( 1 << PAGE_WRITE_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT )  |
        ( 1 << PAGE_CACHEABLE_SHIFT  )
    ;
}
 
/**
 * Returns level 1 page table entry flags.
 *
 * \param pt     level 1 page table
 * \param i      index of the entry to return
 */
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
    pte_level1_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT)   << PAGE_PRESENT_SHIFT) |
        ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
        ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT ) |
        ( p->bufferable << PAGE_CACHEABLE )
    ;
}
 
/**
 * Sets flags of level 0 page table entry.
 *
 * \param pt     level 0 page table
 * \param i      index of the entry to be changed
 * \param flags  new flags
 *
 * TODO: why should_be_zero set to 1?
 */
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
    pte_level0_t *p = &pt[i];
 
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
        p->should_be_zero  = 1;
// TODO: remove in final version
// For Michal: Have to be here ... ensures this entry contains at least 1 non zero bit
//              all zero bits signals PTE_VALID_ARCH , it's different from not_present
    } else {
        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
        p->should_be_zero  = 0;
    }
}
 
/**
 * Sets flags of level 1 page table entry.
 *
 * We use same access rights for the whole page. When page is not preset then
 * store 1 in acess_rigts_3.
 * TODO: why access_right_3?
 *
 * \param pt     level 1 page table
 * \param i      index of the entry to be changed
 * \param flags  new flags
 */  
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
    pte_level1_t *p = &pt[i];
   
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type      = PTE_DESCRIPTOR_NOT_PRESENT;
        p->access_permission_3  = 1;
    } else {
        p->descriptor_type      = PTE_DESCRIPTOR_SMALL_PAGE;
        p->access_permission_3  = p->access_permission_0;
    }
 
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 
    /* default access permission */
    p->access_permission_0 = p->access_permission_1 =
        p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
 
    if (flags & PAGE_USER)  {
        if (flags & PAGE_READ) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RO_KERNEL_RW;
        }
        if (flags & PAGE_WRITE) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RW_KERNEL_RW;
        }
    }
}
 
 
extern void page_arch_init(void);
 
extern void prefetch_abourt(int n, istate_t *istate);
extern void data_abourt(int n, istate_t *istate);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 
 

Subversion Repositories HelenOS

(root)/branches/arm/kernel/arch/arm32/include/mm/page.h @ 2279 – Rev 2258 → 2259

Rev 2258		Rev 2259
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32mm	29	/** @addtogroup arm32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_arm32_PAGE_H_	35	#ifndef KERN_arm32_PAGE_H_
36	#define KERN_arm32_PAGE_H_	36	#define KERN_arm32_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39	#include <mm/mm.h>	39	#include <mm/mm.h>
40	#include <arch/exception.h>	40	#include <arch/exception.h>
41		41
42		42
43	#define PAGE_WIDTH FRAME_WIDTH	43	#define PAGE_WIDTH FRAME_WIDTH
44	#define PAGE_SIZE FRAME_SIZE	44	#define PAGE_SIZE FRAME_SIZE
45		45
46	#define PAGE_COLOR_BITS 0 /* dummy */	46	#define PAGE_COLOR_BITS 0 /* dummy */
47		47
48	#ifndef __ASM__	48	#ifndef __ASM__
49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
51	#else	51	#else
52	# define KA2PA(x) ((x) - 0x80000000)	52	# define KA2PA(x) ((x) - 0x80000000)
53	# define PA2KA(x) ((x) + 0x80000000)	53	# define PA2KA(x) ((x) + 0x80000000)
54	#endif	54	#endif
55		55
56	#ifdef KERNEL	56	#ifdef KERNEL
57		57
58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096	58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096
59	#define PTL1_ENTRIES_ARCH 0	59	#define PTL1_ENTRIES_ARCH 0
60	#define PTL2_ENTRIES_ARCH 0	60	#define PTL2_ENTRIES_ARCH 0
61	/* coarse page tables used (2564 = 1KB per page) /	61	/* coarse page tables used (2564 = 1KB per page) /
62	#define PTL3_ENTRIES_ARCH (2<<8) // 256	62	#define PTL3_ENTRIES_ARCH (2<<8) // 256
63		63
64	#define PTL0_SIZE_ARCH FOUR_FRAMES	64	#define PTL0_SIZE_ARCH FOUR_FRAMES
65	#define PTL1_SIZE_ARCH 0	65	#define PTL1_SIZE_ARCH 0
66	#define PTL2_SIZE_ARCH 0	66	#define PTL2_SIZE_ARCH 0
67	#define PTL3_SIZE_ARCH ONE_FRAME	67	#define PTL3_SIZE_ARCH ONE_FRAME
68		68
69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)	69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
70	#define PTL1_INDEX_ARCH(vaddr) 0	70	#define PTL1_INDEX_ARCH(vaddr) 0
71	#define PTL2_INDEX_ARCH(vaddr) 0	71	#define PTL2_INDEX_ARCH(vaddr) 0
72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)	72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
73		73
74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))	74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))
75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)	75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)	76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))	77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
78		78
79	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))	79	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
80	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)	80	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
81	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	81	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
82	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	82	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
83	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)	83	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
84		84
85	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))	85	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
86	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT	86	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
87	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT	87	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
88	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))	88	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
89		89
90	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))	90	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
91	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	91	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
92	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	92	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
93	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))	93	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
94		94
95	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	95	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
96	// TODO: ?? != 0	96	// TODO: ?? != 0
97	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )	97	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
98		98
99	/* pte should point into ptl3 */	99	/* pte should point into ptl3 */
100	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)	100	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
101	/* pte should point into ptl3 */	101	/* pte should point into ptl3 */
102	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )	102	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
103		103
104	#define PTE_EXECUTABLE_ARCH(pte) 1	104	#define PTE_EXECUTABLE_ARCH(pte) 1
105		105
106	#ifndef __ASM__	106	#ifndef __ASM__
107		107
108	/**	108	/**
109	* Sets the address of level 0 page table.	109	* Sets the address of level 0 page table.
110	*	110	*
111	* \param pt pointer to the page table to set	111	* \param pt pointer to the page table to set
112	*/	112	*/
113	static inline void set_ptl0_addr( pte_level0_t* pt)	113	static inline void set_ptl0_addr( pte_level0_t* pt)
114	{	114	{
115	asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"	115	asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
116	:	116	:
117	: "r"(pt)	117	: "r"(pt)
118	);	118	);
119		119
120	}	120	}
121		121
122	/**	122	/**
123	* Returns level 0 page table entry flags.	123	* Returns level 0 page table entry flags.
124	*	124	*
125	* \param pt level 0 page table	125	* \param pt level 0 page table
126	* \param i index of the entry to return	126	* \param i index of the entry to return
127	*/	127	*/
128	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)	128	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
129	{	129	{
130	pte_level0_t *p = &pt[i];	130	pte_level0_t *p = &pt[i];
131		131
132	return	132	return
133	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) \|	133	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) \|
134	( 1 << PAGE_USER_SHIFT ) \|	134	( 1 << PAGE_USER_SHIFT ) \|
135	( 1 << PAGE_READ_SHIFT ) \|	135	( 1 << PAGE_READ_SHIFT ) \|
136	( 1 << PAGE_WRITE_SHIFT ) \|	136	( 1 << PAGE_WRITE_SHIFT ) \|
137	( 1 << PAGE_EXEC_SHIFT ) \|	137	( 1 << PAGE_EXEC_SHIFT ) \|
138	( 1 << PAGE_CACHEABLE_SHIFT )	138	( 1 << PAGE_CACHEABLE_SHIFT )
139	;	139	;
140	}	140	}
141		141
142	/**	142	/**
143	* Returns level 1 page table entry flags.	143	* Returns level 1 page table entry flags.
144	*	144	*
145	* \param pt level 1 page table	145	* \param pt level 1 page table
146	* \param i index of the entry to return	146	* \param i index of the entry to return
147	*/	147	*/
148	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)	148	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
149	{	149	{
150	pte_level1_t *p = &pt[i];	150	pte_level1_t *p = &pt[i];
151		151
152	return	152	return
153	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) \|	153	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) \|
154	( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) \|	154	( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) \|
155	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) \|	155	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) \|
156	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|	156	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|
157	( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) \|	157	( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) \|
-		158	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) \|
-		159	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|
158	( 1 << PAGE_EXEC_SHIFT ) \|	160	( 1 << PAGE_EXEC_SHIFT ) \|
159	( p->bufferable << PAGE_CACHEABLE )	161	( p->bufferable << PAGE_CACHEABLE )
160	;	162	;
161	}	163	}
162		164
163	/**	165	/**
164	* Sets flags of level 0 page table entry.	166	* Sets flags of level 0 page table entry.
165	*	167	*
166	* \param pt level 0 page table	168	* \param pt level 0 page table
167	* \param i index of the entry to be changed	169	* \param i index of the entry to be changed
168	* \param flags new flags	170	* \param flags new flags
169	*	171	*
170	* TODO: why should_be_zero set to 1?	172	* TODO: why should_be_zero set to 1?
171	*/	173	*/
172	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)	174	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
173	{	175	{
174	pte_level0_t *p = &pt[i];	176	pte_level0_t *p = &pt[i];
175		177
176	if (flags & PAGE_NOT_PRESENT) {	178	if (flags & PAGE_NOT_PRESENT) {
177	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;	179	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
178	// p->should_be_zero = 1;	180	p->should_be_zero = 1;
-		181	// TODO: remove in final version
-		182	// For Michal: Have to be here ... ensures this entry contains at least 1 non zero bit
-		183	// all zero bits signals PTE_VALID_ARCH , it's different from not_present
179	} else {	184	} else {
180	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;	185	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
181	// p->should_be_zero = 0;	186	p->should_be_zero = 0;
182	}	187	}
183	}	188	}
184		189
185	/**	190	/**
186	* Sets flags of level 1 page table entry.	191	* Sets flags of level 1 page table entry.
187	*	192	*
188	* We use same access rights for the whole page. When page is not preset then	193	* We use same access rights for the whole page. When page is not preset then
189	* store 1 in acess_rigts_3.	194	* store 1 in acess_rigts_3.
190	* TODO: why access_right_3?	195	* TODO: why access_right_3?
191	*	196	*
192	* \param pt level 1 page table	197	* \param pt level 1 page table
193	* \param i index of the entry to be changed	198	* \param i index of the entry to be changed
194	* \param flags new flags	199	* \param flags new flags
195	*/	200	*/
196	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)	201	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
197	{	202	{
198	pte_level1_t *p = &pt[i];	203	pte_level1_t *p = &pt[i];
199		204
200	if (flags & PAGE_NOT_PRESENT) {	205	if (flags & PAGE_NOT_PRESENT) {
201	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;	206	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
202	// p->access_permission_3 = 1;	207	p->access_permission_3 = 1;
203	} else {	208	} else {
204	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;	209	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
205	// p->access_permission_3 = p->access_permission_0;	210	p->access_permission_3 = p->access_permission_0;
206	}	211	}
207		212
208	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;	213	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
209		214
210	/* default access permission */	215	/* default access permission */
211	p->access_permission_0 = p->access_permission_1 =	216	p->access_permission_0 = p->access_permission_1 =
212	p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;	217	p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
213		218
214	if (flags & PAGE_USER) {	219	if (flags & PAGE_USER) {
215	if (flags & PAGE_READ) {	220	if (flags & PAGE_READ) {
216	p->access_permission_0 = p->access_permission_1 =	221	p->access_permission_0 = p->access_permission_1 =
217	p->access_permission_2 = p->access_permission_3 =	222	p->access_permission_2 = p->access_permission_3 =
218	PTE_AP_USER_RO_KERNEL_RW;	223	PTE_AP_USER_RO_KERNEL_RW;
219	}	224	}
220	if (flags & PAGE_WRITE) {	225	if (flags & PAGE_WRITE) {
221	p->access_permission_0 = p->access_permission_1 =	226	p->access_permission_0 = p->access_permission_1 =
222	p->access_permission_2 = p->access_permission_3 =	227	p->access_permission_2 = p->access_permission_3 =
223	PTE_AP_USER_RW_KERNEL_RW;	228	PTE_AP_USER_RW_KERNEL_RW;
224	}	229	}
225	}	230	}
226	}	231	}
227		232
228		233
229	extern void page_arch_init(void);	234	extern void page_arch_init(void);
230		235
231	extern void prefetch_abourt(int n, istate_t *istate);	236	extern void prefetch_abourt(int n, istate_t *istate);
232	extern void data_abourt(int n, istate_t *istate);	237	extern void data_abourt(int n, istate_t *istate);
233		238
234	#endif /* __ASM__ */	239	#endif /* __ASM__ */
235		240
236	#endif /* KERNEL */	241	#endif /* KERNEL */
237		242
238	#endif	243	#endif
239		244
240	/** @}	245	/** @}
241	*/	246	*/
242		247
243		248