WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/include/mm/page.h


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_arm32_PAGE_H_
#define KERN_arm32_PAGE_H_
 
#include <arch/mm/frame.h>
#include <mm/mm.h>
#include <arch/exception.h>
 
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
#define PAGE_COLOR_BITS 0           /* dummy */
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
#ifdef KERNEL
 
#define PTL0_ENTRIES_ARCH   (2<<12)    // 4096
#define PTL1_ENTRIES_ARCH   0
#define PTL2_ENTRIES_ARCH   0
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH   (2<<8)     // 256
 
#define PTL0_SIZE_ARCH      FOUR_FRAMES
#define PTL1_SIZE_ARCH      0
#define PTL2_SIZE_ARCH      0
#define PTL3_SIZE_ARCH      ONE_FRAME
 
#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr)  0
#define PTL2_INDEX_ARCH(vaddr)  0
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte)             (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte)           ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte)         ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte)          ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
#define PTE_EXECUTABLE_ARCH(pte)        1
 
#ifndef __ASM__
 
/** Level 0 page table entry. */
typedef struct {
    /* 01b for coarse tables, see below for details */
    unsigned descriptor_type     : 2;
    unsigned impl_specific       : 3;
    unsigned domain              : 4;
    unsigned should_be_zero      : 1;
    /* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
     * or large (64KB) pages. ARM also supports fine 2nd level page tables that
     * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
     * with 1KB per the coarse table)
    */
    unsigned coarse_table_addr   : 22;
} __attribute__ ((packed)) pte_level0_t;
 
/** Level 1 page table entry (small (4KB) pages used) */
typedef struct {
    /* 0b10 for small pages */
    unsigned descriptor_type     : 2;
    unsigned bufferable          : 1;
    unsigned cacheable           : 1;
    /* access permissions for each of 4 subparts of a page
     * (for each 1KB when small pages used */
    unsigned access_permission_0 : 2;
    unsigned access_permission_1 : 2;
    unsigned access_permission_2 : 2;
    unsigned access_permission_3 : 2;
    unsigned frame_base_addr     : 20;
} __attribute__ ((packed)) pte_level1_t;
 
 
/* Level 1 page tables access permissions */
 
/** User mode: no access, privileged mode: no access */
#define PTE_AP_USER_NO_KERNEL_NO 0
/** User mode: no access, privileged mode: read/write */
#define PTE_AP_USER_NO_KERNEL_RW 1
/** User mode: read only, privileged mode: read/write */
#define PTE_AP_USER_RO_KERNEL_RW 2
/** User mode: read/write, privileged mode: read/write */
#define PTE_AP_USER_RW_KERNEL_RW 3
 
 
/* pte_level0_t and pte_level1_t descriptor_type flags */
 
/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_NOT_PRESENT  0
/** pte_level0_t coarse page table flag (used in descriptor_type) */
#define PTE_DESCRIPTOR_COARSE_TABLE 1
/** pte_level1_t small page table flag (used in descriptor type) */
#define PTE_DESCRIPTOR_SMALL_PAGE   2
 
 
/**
 * Sets the address of level 0 page table.
 *
 * \param pt    pointer to the page table to set
 */  
static inline void set_ptl0_addr( pte_level0_t* pt)
{
    asm volatile (
        "mcr p15, 0, %0, c2, c0, 0 \n"
        :
        : "r"(pt)
    );
}
 
/** Returns level 0 page table entry flags.
 *
 *  \param pt     level 0 page table
 *  \param i      index of the entry to return
 */
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
    pte_level0_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
        ( 1 << PAGE_USER_SHIFT )  |
        ( 1 << PAGE_READ_SHIFT )  |
        ( 1 << PAGE_WRITE_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT )  |
        ( 1 << PAGE_CACHEABLE_SHIFT  )
    ;
}
 
/** Returns level 1 page table entry flags.
 *
 *  \param pt     level 1 page table
 *  \param i      index of the entry to return
 */
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
    pte_level1_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT)   << PAGE_PRESENT_SHIFT) |
        ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
        ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT ) |
        ( p->bufferable << PAGE_CACHEABLE )
    ;
}
 
/** Sets flags of level 0 page table entry.
 *
 *  \param pt     level 0 page table
 *  \param i      index of the entry to be changed
 *  \param flags  new flags
 */
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
    pte_level0_t *p = &pt[i];
 
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
        // ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied
        p->should_be_zero  = 1;
    } else {
        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
        p->should_be_zero  = 0;
    }
}
 
/** Sets flags of level 1 page table entry.
 *
 *  We use same access rights for the whole page. When page is not preset we
 *  store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
 *  page entry, see #PAGE_VALID_ARCH).
 *
 *  \param pt     level 1 page table
 *  \param i      index of the entry to be changed
 *  \param flags  new flags
 */  
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
    pte_level1_t *p = &pt[i];
   
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type      = PTE_DESCRIPTOR_NOT_PRESENT;
        p->access_permission_3  = 1;
    } else {
        p->descriptor_type      = PTE_DESCRIPTOR_SMALL_PAGE;
        p->access_permission_3  = p->access_permission_0;
    }
 
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 
    /* default access permission */
    p->access_permission_0 = p->access_permission_1 =
        p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
 
    if (flags & PAGE_USER)  {
        if (flags & PAGE_READ) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RO_KERNEL_RW;
        }
        if (flags & PAGE_WRITE) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RW_KERNEL_RW;
        }
    }
}
 
 
extern void page_arch_init(void);
 
 
 
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 
 

Subversion Repositories HelenOS

(root)/branches/arm/kernel/arch/arm32/include/mm/page.h – Rev 2277 → 2278

Rev 2277		Rev 2278
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32mm	29	/** @addtogroup arm32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_arm32_PAGE_H_	35	#ifndef KERN_arm32_PAGE_H_
36	#define KERN_arm32_PAGE_H_	36	#define KERN_arm32_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39	#include <mm/mm.h>	39	#include <mm/mm.h>
40	#include <arch/exception.h>	40	#include <arch/exception.h>
41		41
42		42
43	#define PAGE_WIDTH FRAME_WIDTH	43	#define PAGE_WIDTH FRAME_WIDTH
44	#define PAGE_SIZE FRAME_SIZE	44	#define PAGE_SIZE FRAME_SIZE
45		45
46	#define PAGE_COLOR_BITS 0 /* dummy */	46	#define PAGE_COLOR_BITS 0 /* dummy */
47		47
48	#ifndef __ASM__	48	#ifndef __ASM__
49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
51	#else	51	#else
52	# define KA2PA(x) ((x) - 0x80000000)	52	# define KA2PA(x) ((x) - 0x80000000)
53	# define PA2KA(x) ((x) + 0x80000000)	53	# define PA2KA(x) ((x) + 0x80000000)
54	#endif	54	#endif
55		55
56	#ifdef KERNEL	56	#ifdef KERNEL
57		57
58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096	58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096
59	#define PTL1_ENTRIES_ARCH 0	59	#define PTL1_ENTRIES_ARCH 0
60	#define PTL2_ENTRIES_ARCH 0	60	#define PTL2_ENTRIES_ARCH 0
61	/* coarse page tables used (2564 = 1KB per page) /	61	/* coarse page tables used (2564 = 1KB per page) /
62	#define PTL3_ENTRIES_ARCH (2<<8) // 256	62	#define PTL3_ENTRIES_ARCH (2<<8) // 256
63		63
64	#define PTL0_SIZE_ARCH FOUR_FRAMES	64	#define PTL0_SIZE_ARCH FOUR_FRAMES
65	#define PTL1_SIZE_ARCH 0	65	#define PTL1_SIZE_ARCH 0
66	#define PTL2_SIZE_ARCH 0	66	#define PTL2_SIZE_ARCH 0
67	#define PTL3_SIZE_ARCH ONE_FRAME	67	#define PTL3_SIZE_ARCH ONE_FRAME
68		68
69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)	69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
70	#define PTL1_INDEX_ARCH(vaddr) 0	70	#define PTL1_INDEX_ARCH(vaddr) 0
71	#define PTL2_INDEX_ARCH(vaddr) 0	71	#define PTL2_INDEX_ARCH(vaddr) 0
72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)	72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
73		73
74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))	74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))
75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)	75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)	76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))	77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
78		78
79	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))	79	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
80	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)	80	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
81	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	81	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
82	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	82	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
83	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)	83	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
84		84
85	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))	85	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
86	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT	86	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
87	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT	87	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
88	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))	88	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
89		89
90	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))	90	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
91	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	91	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
92	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	92	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
93	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))	93	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
94		94
95	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	95	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
96	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )	96	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
97		97
98	/* pte should point into ptl3 */	98	/* pte should point into ptl3 */
99	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)	99	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
100	/* pte should point into ptl3 */	100	/* pte should point into ptl3 */
101	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )	101	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
102	#define PTE_EXECUTABLE_ARCH(pte) 1	102	#define PTE_EXECUTABLE_ARCH(pte) 1
103		103
104	#ifndef __ASM__	104	#ifndef __ASM__
105		105
106	/** Level 0 page table entry. */	106	/** Level 0 page table entry. */
107	typedef struct {	107	typedef struct {
108	/* 01b for coarse tables, see below for details */	108	/* 01b for coarse tables, see below for details */
109	unsigned descriptor_type : 2;	109	unsigned descriptor_type : 2;
110	unsigned impl_specific : 3;	110	unsigned impl_specific : 3;
111	unsigned domain : 4;	111	unsigned domain : 4;
112	unsigned should_be_zero : 1;	112	unsigned should_be_zero : 1;
113	/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)	113	/* Pointer to the coarse 2nd level page table (holding entries for small (4KB)
114	* or large (64KB) pages. ARM also supports fine 2nd level page tables that	114	* or large (64KB) pages. ARM also supports fine 2nd level page tables that
115	* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison	115	* may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison
116	* with 1KB per the coarse table)	116	* with 1KB per the coarse table)
117	*/	117	*/
118	unsigned coarse_table_addr : 22;	118	unsigned coarse_table_addr : 22;
119	} __attribute__ ((packed)) pte_level0_t;	119	} __attribute__ ((packed)) pte_level0_t;
120		120
121	/** Level 1 page table entry (small (4KB) pages used) */	121	/** Level 1 page table entry (small (4KB) pages used) */
122	typedef struct {	122	typedef struct {
123	/* 0b10 for small pages */	123	/* 0b10 for small pages */
124	unsigned descriptor_type : 2;	124	unsigned descriptor_type : 2;
125	unsigned bufferable : 1;	125	unsigned bufferable : 1;
126	unsigned cacheable : 1;	126	unsigned cacheable : 1;
127	/* access permissions for each of 4 subparts of a page	127	/* access permissions for each of 4 subparts of a page
128	* (for each 1KB when small pages used */	128	* (for each 1KB when small pages used */
129	unsigned access_permission_0 : 2;	129	unsigned access_permission_0 : 2;
130	unsigned access_permission_1 : 2;	130	unsigned access_permission_1 : 2;
131	unsigned access_permission_2 : 2;	131	unsigned access_permission_2 : 2;
132	unsigned access_permission_3 : 2;	132	unsigned access_permission_3 : 2;
133	unsigned frame_base_addr : 20;	133	unsigned frame_base_addr : 20;
134	} __attribute__ ((packed)) pte_level1_t;	134	} __attribute__ ((packed)) pte_level1_t;
135		135
136		136
137	/* Level 1 page tables access permissions */	137	/* Level 1 page tables access permissions */
138		138
139	/** User mode: no access, privileged mode: no access */	139	/** User mode: no access, privileged mode: no access */
140	#define PTE_AP_USER_NO_KERNEL_NO 0	140	#define PTE_AP_USER_NO_KERNEL_NO 0
141	/** User mode: no access, privileged mode: read/write */	141	/** User mode: no access, privileged mode: read/write */
142	#define PTE_AP_USER_NO_KERNEL_RW 1	142	#define PTE_AP_USER_NO_KERNEL_RW 1
143	/** User mode: read only, privileged mode: read/write */	143	/** User mode: read only, privileged mode: read/write */
144	#define PTE_AP_USER_RO_KERNEL_RW 2	144	#define PTE_AP_USER_RO_KERNEL_RW 2
145	/** User mode: read/write, privileged mode: read/write */	145	/** User mode: read/write, privileged mode: read/write */
146	#define PTE_AP_USER_RW_KERNEL_RW 3	146	#define PTE_AP_USER_RW_KERNEL_RW 3
147		147
148		148
149	/* pte_level0_t and pte_level1_t descriptor_type flags */	149	/* pte_level0_t and pte_level1_t descriptor_type flags */
150		150
151	/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */	151	/** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type) */
152	#define PTE_DESCRIPTOR_NOT_PRESENT 0	152	#define PTE_DESCRIPTOR_NOT_PRESENT 0
153	/** pte_level0_t coarse page table flag (used in descriptor_type) */	153	/** pte_level0_t coarse page table flag (used in descriptor_type) */
154	#define PTE_DESCRIPTOR_COARSE_TABLE 1	154	#define PTE_DESCRIPTOR_COARSE_TABLE 1
155	/** pte_level1_t small page table flag (used in descriptor type) */	155	/** pte_level1_t small page table flag (used in descriptor type) */
156	#define PTE_DESCRIPTOR_SMALL_PAGE 2	156	#define PTE_DESCRIPTOR_SMALL_PAGE 2
157		157
158		158
159	/**	159	/**
160	* Sets the address of level 0 page table.	160	* Sets the address of level 0 page table.
161	*	161	*
162	* \param pt pointer to the page table to set	162	* \param pt pointer to the page table to set
163	*/	163	*/
164	static inline void set_ptl0_addr( pte_level0_t* pt)	164	static inline void set_ptl0_addr( pte_level0_t* pt)
165	{	165	{
166	asm volatile (	166	asm volatile (
167	"mcr p15, 0, %0, c2, c0, 0 \n"	167	"mcr p15, 0, %0, c2, c0, 0 \n"
168	:	168	:
169	: "r"(pt)	169	: "r"(pt)
170	);	170	);
171	}	171	}
172		172
173	/** Returns level 0 page table entry flags.	173	/** Returns level 0 page table entry flags.
174	*	174	*
175	* \param pt level 0 page table	175	* \param pt level 0 page table
176	* \param i index of the entry to return	176	* \param i index of the entry to return
177	*/	177	*/
178	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)	178	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
179	{	179	{
180	pte_level0_t *p = &pt[i];	180	pte_level0_t *p = &pt[i];
181		181
182	return	182	return
183	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) \|	183	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) \|
184	( 1 << PAGE_USER_SHIFT ) \|	184	( 1 << PAGE_USER_SHIFT ) \|
185	( 1 << PAGE_READ_SHIFT ) \|	185	( 1 << PAGE_READ_SHIFT ) \|
186	( 1 << PAGE_WRITE_SHIFT ) \|	186	( 1 << PAGE_WRITE_SHIFT ) \|
187	( 1 << PAGE_EXEC_SHIFT ) \|	187	( 1 << PAGE_EXEC_SHIFT ) \|
188	( 1 << PAGE_CACHEABLE_SHIFT )	188	( 1 << PAGE_CACHEABLE_SHIFT )
189	;	189	;
190	}	190	}
191		191
192	/** Returns level 1 page table entry flags.	192	/** Returns level 1 page table entry flags.
193	*	193	*
194	* \param pt level 1 page table	194	* \param pt level 1 page table
195	* \param i index of the entry to return	195	* \param i index of the entry to return
196	*/	196	*/
197	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)	197	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
198	{	198	{
199	pte_level1_t *p = &pt[i];	199	pte_level1_t *p = &pt[i];
200		200
201	return	201	return
202	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) \|	202	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) \|
203	( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) \|	203	( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) \|
204	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) \|	204	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) \|
205	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|	205	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|
206	( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) \|	206	( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) \|
207	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) \|	207	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT ) \|
208	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|	208	( (p->access_permission_0 == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|
209	( 1 << PAGE_EXEC_SHIFT ) \|	209	( 1 << PAGE_EXEC_SHIFT ) \|
210	( p->bufferable << PAGE_CACHEABLE )	210	( p->bufferable << PAGE_CACHEABLE )
211	;	211	;
212	}	212	}
213		213
214	/** Sets flags of level 0 page table entry.	214	/** Sets flags of level 0 page table entry.
215	*	215	*
216	* \param pt level 0 page table	216	* \param pt level 0 page table
217	* \param i index of the entry to be changed	217	* \param i index of the entry to be changed
218	* \param flags new flags	218	* \param flags new flags
219	*/	219	*/
220	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)	220	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
221	{	221	{
222	pte_level0_t *p = &pt[i];	222	pte_level0_t *p = &pt[i];
223		223
224	if (flags & PAGE_NOT_PRESENT) {	224	if (flags & PAGE_NOT_PRESENT) {
225	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;	225	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
226	// ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied	226	// ensures that the entry will be recognized as valid when PTE_VALID_ARCH applied
227	p->should_be_zero = 1;	227	p->should_be_zero = 1;
228	} else {	228	} else {
229	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;	229	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
230	p->should_be_zero = 0;	230	p->should_be_zero = 0;
231	}	231	}
232	}	232	}
233		233
234	/** Sets flags of level 1 page table entry.	234	/** Sets flags of level 1 page table entry.
235	*	235	*
236	* We use same access rights for the whole page. When page is not preset we	236	* We use same access rights for the whole page. When page is not preset we
237	* store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct	237	* store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct
238	* page entry, see #PAGE_VALID_ARCH).	238	* page entry, see #PAGE_VALID_ARCH).
239	*	239	*
240	* \param pt level 1 page table	240	* \param pt level 1 page table
241	* \param i index of the entry to be changed	241	* \param i index of the entry to be changed
242	* \param flags new flags	242	* \param flags new flags
243	*/	243	*/
244	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)	244	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
245	{	245	{
246	pte_level1_t *p = &pt[i];	246	pte_level1_t *p = &pt[i];
247		247
248	if (flags & PAGE_NOT_PRESENT) {	248	if (flags & PAGE_NOT_PRESENT) {
249	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;	249	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
250	p->access_permission_3 = 1;	250	p->access_permission_3 = 1;
251	} else {	251	} else {
252	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;	252	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
253	p->access_permission_3 = p->access_permission_0;	253	p->access_permission_3 = p->access_permission_0;
254	}	254	}
255		255
256	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;	256	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
257		257
258	/* default access permission */	258	/* default access permission */
259	p->access_permission_0 = p->access_permission_1 =	259	p->access_permission_0 = p->access_permission_1 =
260	p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;	260	p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
261		261
262	if (flags & PAGE_USER) {	262	if (flags & PAGE_USER) {
263	if (flags & PAGE_READ) {	263	if (flags & PAGE_READ) {
264	p->access_permission_0 = p->access_permission_1 =	264	p->access_permission_0 = p->access_permission_1 =
265	p->access_permission_2 = p->access_permission_3 =	265	p->access_permission_2 = p->access_permission_3 =
266	PTE_AP_USER_RO_KERNEL_RW;	266	PTE_AP_USER_RO_KERNEL_RW;
267	}	267	}
268	if (flags & PAGE_WRITE) {	268	if (flags & PAGE_WRITE) {
269	p->access_permission_0 = p->access_permission_1 =	269	p->access_permission_0 = p->access_permission_1 =
270	p->access_permission_2 = p->access_permission_3 =	270	p->access_permission_2 = p->access_permission_3 =
271	PTE_AP_USER_RW_KERNEL_RW;	271	PTE_AP_USER_RW_KERNEL_RW;
272	}	272	}
273	}	273	}
274	}	274	}
275		275
276		276
277	extern void page_arch_init(void);	277	extern void page_arch_init(void);
278		278
279	extern void prefetch_abort(int n, istate_t *istate);	-
280	extern void data_abort(int n, istate_t *istate);	-
281		279
282	#endif /* __ASM__ */	280	#endif /* __ASM__ */
283		281
284	#endif /* KERNEL */	282	#endif /* KERNEL */
285		283
286	#endif	284	#endif
287		285
288	/** @}	286	/** @}
289	*/	287	*/
290		288
291		289