WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/include/mm/page.h


/*
 * Copyright (c) 2003-2007 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_arm32_PAGE_H_
#define KERN_arm32_PAGE_H_
 
#include <arch/mm/frame.h>
#include <mm/mm.h>
#include <arch/exception.h>
 
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
#define PAGE_COLOR_BITS 0           /* dummy */
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
#ifdef KERNEL
// Using small pages <==> 4kb
#define PTL0_ENTRIES_ARCH   (2<<12) // 4096
#define PTL1_ENTRIES_ARCH   0   
#define PTL2_ENTRIES_ARCH   0   
#define PTL3_ENTRIES_ARCH   (2<<8)  // 256
 
#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr)  0   
#define PTL2_INDEX_ARCH(vaddr)  0   
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x0ff)
 
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)(  (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0)         ( set_ptl0_addr((pte_level0_t *)(ptl0)) )
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type )
#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)  // pte should point into ptl3 
#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw )  // pte should point into ptl3
#define PTE_EXECUTABLE_ARCH(pte)               1
 
#ifndef __ASM__
 
/** Set adress of paging level 0 table
 * \param pt pointer to page table to set
 */  
static inline void set_ptl0_addr( pte_level0_t* pt){
    asm volatile ( "mrc p15, 0, %0, c2, c0, 0 \n"
    :
    : "r"(pt)
    );
   
}
 
//TODO Comment: Page table structure as in other architectures
 
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
  pte_level0_t *p = &pt[i];
 
    return (
        ( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
        ( 1 << PAGE_READ_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT ) |
        ( 1 << PAGE_CACHEABLE  )
 
 
    );
 
}
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
  pte_level1_t *p = &pt[i];
 
    return (
        ( p->descriptor_type != pte_descriptor_not_preset )    << PAGE_PRESENT_SHIFT |
        ( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
        ( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT )  |
        ( 1 << PAGE_EXEC_SHIFT ) |
        ( p->bufferable << PAGE_CACHEABLE  )
 
 
 
    );
 
}
 
 
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
    pte_level0_t *p = &pt[i];
   
    if ( flags & PAGE_NOT_PRESENT ) {
      p->descriptor_type = pte_descriptor_not_preset;
      p->should_be_zero  = 1;
    } else
    {
      p->descriptor_type = pte_descriptor_coarse_table;
      p->should_be_zero  = 0;
    }
    return;
}
 
/* We use same acess rights for whole page, so if page is set as not preset then
 * in acess_rigts_3 set value 1
 */  
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
    pte_level1_t *p = &pt[i];
   
    if ( flags & PAGE_NOT_PRESENT ) {
      p->descriptor_type      = pte_descriptor_not_preset;
      p->access_permission_3  = 1;
    } else
    {
      p->descriptor_type      = pte_descriptor_coarse_table;
      p->access_permission_3  = p->access_permission_0;
    }
 
  p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
  // default kernel rw, user none
  p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
  if ( flags & PAGE_USER )  {
      if ( flags & PAGE_READ )
          p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw;
      if ( flags & PAGE_WRITE )
          p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw;
  }
    return; return;
}
 
extern void page_arch_init(void);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 
 

Subversion Repositories HelenOS

(root)/branches/arm/kernel/arch/arm32/include/mm/page.h – Rev 2149 → 2182

Rev 2149		Rev 2182
1	/*	1	/*
2	* Copyright (c) 2003-2007 Jakub Jermar	2	* Copyright (c) 2003-2007 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32mm	29	/** @addtogroup arm32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_arm32_PAGE_H_	35	#ifndef KERN_arm32_PAGE_H_
36	#define KERN_arm32_PAGE_H_	36	#define KERN_arm32_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
-		39	#include <mm/mm.h>
-		40	#include <arch/exception.h>
-		41
39		42
40	#define PAGE_WIDTH FRAME_WIDTH	43	#define PAGE_WIDTH FRAME_WIDTH
41	#define PAGE_SIZE FRAME_SIZE	44	#define PAGE_SIZE FRAME_SIZE
42		45
43	#define PAGE_COLOR_BITS 0 /* dummy */	46	#define PAGE_COLOR_BITS 0 /* dummy */
44		47
45	#ifndef __ASM__	48	#ifndef __ASM__
46	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
47	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
48	#else	51	#else
49	# define KA2PA(x) ((x) - 0x80000000)	52	# define KA2PA(x) ((x) - 0x80000000)
50	# define PA2KA(x) ((x) + 0x80000000)	53	# define PA2KA(x) ((x) + 0x80000000)
51	#endif	54	#endif
52		55
53	#ifdef KERNEL	56	#ifdef KERNEL
54	// Using small pages <==> 4kb	57	// Using small pages <==> 4kb
55	#define PTL0_ENTRIES_ARCH (2<<12) // 4096	58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096
56	#define PTL1_ENTRIES_ARCH 0	59	#define PTL1_ENTRIES_ARCH 0
57	#define PTL2_ENTRIES_ARCH 0	60	#define PTL2_ENTRIES_ARCH 0
58	#define PTL3_ENTRIES_ARCH (2<<8) // 256	61	#define PTL3_ENTRIES_ARCH (2<<8) // 256
59		62
60	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)	63	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
61	#define PTL1_INDEX_ARCH(vaddr) 0	64	#define PTL1_INDEX_ARCH(vaddr) 0
62	#define PTL2_INDEX_ARCH(vaddr) 0	65	#define PTL2_INDEX_ARCH(vaddr) 0
63	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)	66	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
64		67
65		68
66	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))	69	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))
67	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)	70	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
68	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)	71	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
69	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))	72	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
70		73
71	#define SET_PTL0_ADDRESS_ARCH(ptl0) // TODO	74	#define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_t *)(ptl0)) )
72	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)	75	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
73	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	76	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
74	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	77	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
75	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)	78	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
76		79
77	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))	80	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
78	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT	81	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
79	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT	82	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
80	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))	83	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
81		84
82	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))	85	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
83	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	86	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
84	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	87	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
85	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))	88	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
86		89
87	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	90	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
88	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type )	91	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type )
89	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3	92	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3
90	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3	93	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3
91	#define PTE_EXECUTABLE_ARCH(pte) 1	94	#define PTE_EXECUTABLE_ARCH(pte) 1
92		95
93	#ifndef __ASM__	96	#ifndef __ASM__
94		97
95	#include <mm/mm.h>	98	/** Set adress of paging level 0 table
96	#include <arch/exception.h>	99	* \param pt pointer to page table to set
-		100	*/
-		101	static inline void set_ptl0_addr( pte_level0_t* pt){
-		102	asm volatile ( "mrc p15, 0, %0, c2, c0, 0 \n"
-		103	:
-		104	: "r"(pt)
-		105	);
-		106
-		107	}
97		108
98	//TODO Comment: Page table structure as in other architectures	109	//TODO Comment: Page table structure as in other architectures
99		110
100	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)	111	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
101	{	112	{
102	pte_level0_t *p = &pt[i];	113	pte_level0_t *p = &pt[i];
103		114
104	return (	115	return (
105	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|	116	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|
106	( 1 << PAGE_READ_SHIFT ) \|	117	( 1 << PAGE_READ_SHIFT ) \|
107	( 1 << PAGE_EXEC_SHIFT ) \|	118	( 1 << PAGE_EXEC_SHIFT ) \|
108	( 1 << PAGE_CACHEABLE )	119	( 1 << PAGE_CACHEABLE )
109	// Alf Note: MayBe return WriteAble because level0 should use only kernel which can write	-
110	// Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly)	-
111	);	120	);
112		121
113	}	122	}
114	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)	123	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
115	{	124	{
116	pte_level1_t *p = &pt[i];	125	pte_level1_t *p = &pt[i];
117		126
118	return (	127	return (
119	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|	128	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|
120	( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) \|	129	( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) \|
121	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) \|	130	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) \|
122	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) \|	131	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) \|
123	( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) \|	132	( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) \|
124	( 1 << PAGE_EXEC_SHIFT ) \|	133	( 1 << PAGE_EXEC_SHIFT ) \|
125	( p->bufferable << PAGE_CACHEABLE )	134	( p->bufferable << PAGE_CACHEABLE )
126	// Alf Note: MayBe return global flag if index i > 2048 (horni 2GB because kernel is mapped globaly)	-
127		135
128		136
129	);	137	);
130		138
131	}	139	}
132		140
133		141
134	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)	142	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
135	{	143	{
136	pte_level0_t *p = &pt[i];	144	pte_level0_t *p = &pt[i];
137		145
138	if ( flags & PAGE_NOT_PRESENT ) {	146	if ( flags & PAGE_NOT_PRESENT ) {
139	p->descriptor_type = pte_descriptor_not_preset;	147	p->descriptor_type = pte_descriptor_not_preset;
140	p->should_be_zero = 1;	148	p->should_be_zero = 1;
141	} else	149	} else
142	{	150	{
143	p->descriptor_type = pte_descriptor_coarse_table;	151	p->descriptor_type = pte_descriptor_coarse_table;
144	p->should_be_zero = 0;	152	p->should_be_zero = 0;
145	}	153	}
146	return;	154	return;
147	}	155	}
148		156
149	/* We use same acess rights for whole page, so if page is set as not preset then	157	/* We use same acess rights for whole page, so if page is set as not preset then
150	* in acess_rigts_3 set value 1	158	* in acess_rigts_3 set value 1
151	*/	159	*/
152	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)	160	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
153	{	161	{
154	pte_level1_t *p = &pt[i];	162	pte_level1_t *p = &pt[i];
155		163
156	if ( flags & PAGE_NOT_PRESENT ) {	164	if ( flags & PAGE_NOT_PRESENT ) {
157	p->descriptor_type = pte_descriptor_not_preset;	165	p->descriptor_type = pte_descriptor_not_preset;
158	p->access_permission_3 = 1; // Ensure not all bits set to zero ... correct acess rights are stored in other 0-2 access permission entries	166	p->access_permission_3 = 1;
159	} else	167	} else
160	{	168	{
161	p->descriptor_type = pte_descriptor_coarse_table;	169	p->descriptor_type = pte_descriptor_coarse_table;
162	p->access_permission_3 = p->access_permission_0;	170	p->access_permission_3 = p->access_permission_0;
163	}	171	}
164		172
165	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;	173	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
166	// default kernel rw, user none	174	// default kernel rw, user none
167	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;	175	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
168	if ( flags & PAGE_USER ) {	176	if ( flags & PAGE_USER ) {
169	if ( flags & PAGE_READ )	177	if ( flags & PAGE_READ )
170	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw;	178	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw;
171	if ( flags & PAGE_WRITE )	179	if ( flags & PAGE_WRITE )
172	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw;	180	p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw;
173	}	181	}
174	return; return;	182	return; return;
175	}	183	}
176		184
177	extern void page_arch_init(void);	185	extern void page_arch_init(void);
178		186
179	#endif /* __ASM__ */	187	#endif /* __ASM__ */
180		188
181	#endif /* KERNEL */	189	#endif /* KERNEL */
182		190
183	#endif	191	#endif
184		192
185	/** @}	193	/** @}
186	*/	194	*/
187		195
188		196