WebSVN – HelenOS – Diff – /branches/arm/kernel/arch/arm32/include/mm/page.h/


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_arm32_PAGE_H_
#define KERN_arm32_PAGE_H_
 
#include <arch/mm/frame.h>
#include <mm/mm.h>
#include <arch/exception.h>
 
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
#define PAGE_COLOR_BITS 0           /* dummy */
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
#ifdef KERNEL
 
#define PTL0_ENTRIES_ARCH    (2<<12)    // 4096
#define PTL1_ENTRIES_ARCH     0 
#define PTL2_ENTRIES_ARCH     0 
/* coarse page tables used (256*4 = 1KB per page) */
#define PTL3_ENTRIES_ARCH    (2<<8)     // 256
 
#define PTL0_SIZE_ARCH       FOUR_FRAMES
#define PTL1_SIZE_ARCH       0
#define PTL2_SIZE_ARCH       0
#define PTL3_SIZE_ARCH       ONE_FRAME
 
#define PTL0_INDEX_ARCH(vaddr)    (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr)    0 
#define PTL2_INDEX_ARCH(vaddr)    0
 
#define PTL3_INDEX_ARCH(vaddr)    (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i)      ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i)      (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i)      (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i)     ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0)         (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a)   (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a)  (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i)        get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i)        PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i)        PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i)       get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x)     set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x)    set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte)                 (*((uint32_t *) (pte)) != 0)
// TODO: ?? != 0
#define PTE_PRESENT_ARCH(pte)               ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
 
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte)             ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte)              ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) 
 
#define PTE_EXECUTABLE_ARCH(pte)            1
 
#ifndef __ASM__
 
/**
 * Sets the address of level 0 page table.
 *
 * \param pt    pointer to the page table to set
 */  
static inline void set_ptl0_addr( pte_level0_t* pt)
{
    asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
        :
        : "r"(pt)
    );
   
}
 
/**
 * Returns level 0 page table entry flags.
 *
 * \param pt     level 0 page table
 * \param i      index of the entry to return
 */
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
    pte_level0_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
        ( 1 << PAGE_USER_SHIFT )  |
        ( 1 << PAGE_READ_SHIFT )  |
        ( 1 << PAGE_WRITE_SHIFT ) |
        ( 1 << PAGE_EXEC_SHIFT )  |
        ( 1 << PAGE_CACHEABLE_SHIFT  )
    ;
}
 
/**
 * Returns level 1 page table entry flags.
 *
 * \param pt     level 1 page table
 * \param i      index of the entry to return
 */
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
    pte_level1_t *p = &pt[i];
 
    return
        ( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT)   << PAGE_PRESENT_SHIFT) |
        ( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT )  |
        ( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
        ( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT )  |
        ( 1 << PAGE_EXEC_SHIFT ) |
        ( p->bufferable << PAGE_CACHEABLE )
    ;
}
 
/**
 * Sets flags of level 0 page table entry.
 *
 * \param pt     level 0 page table
 * \param i      index of the entry to be changed
 * \param flags  new flags
 *
 * TODO: why should_be_zero set to 1?
 */
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
    pte_level0_t *p = &pt[i];
 
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
//      p->should_be_zero  = 1;
    } else {
        p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
//      p->should_be_zero  = 0;
    }
}
 
/**
 * Sets flags of level 1 page table entry.
 *
 * We use same access rights for the whole page. When page is not preset then
 * store 1 in acess_rigts_3.
 * TODO: why access_right_3?
 *
 * \param pt     level 1 page table
 * \param i      index of the entry to be changed
 * \param flags  new flags
 */  
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
{
    pte_level1_t *p = &pt[i];
   
    if (flags & PAGE_NOT_PRESENT) {
        p->descriptor_type      = PTE_DESCRIPTOR_NOT_PRESENT;
//      p->access_permission_3  = 1; 
    } else {
        p->descriptor_type      = PTE_DESCRIPTOR_SMALL_PAGE;
//      p->access_permission_3  = p->access_permission_0;
    }
 
    p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 
    /* default access permission */
    p->access_permission_0 = p->access_permission_1 =
        p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
 
    if (flags & PAGE_USER)  {
        if (flags & PAGE_READ) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RO_KERNEL_RW;
        }
        if (flags & PAGE_WRITE) {
            p->access_permission_0 = p->access_permission_1 =
                p->access_permission_2 = p->access_permission_3 =
                PTE_AP_USER_RW_KERNEL_RW;
        }
    }
}
 
extern void page_arch_init(void);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 
 

Subversion Repositories HelenOS

(root)/branches/arm/kernel/arch/arm32/include/mm/page.h/ @ 2276 – Rev 2242 → 2256

Rev 2242		Rev 2256
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32mm	29	/** @addtogroup arm32mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_arm32_PAGE_H_	35	#ifndef KERN_arm32_PAGE_H_
36	#define KERN_arm32_PAGE_H_	36	#define KERN_arm32_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39	#include <mm/mm.h>	39	#include <mm/mm.h>
40	#include <arch/exception.h>	40	#include <arch/exception.h>
41		41
42		42
43	#define PAGE_WIDTH FRAME_WIDTH	43	#define PAGE_WIDTH FRAME_WIDTH
44	#define PAGE_SIZE FRAME_SIZE	44	#define PAGE_SIZE FRAME_SIZE
45		45
46	#define PAGE_COLOR_BITS 0 /* dummy */	46	#define PAGE_COLOR_BITS 0 /* dummy */
47		47
48	#ifndef __ASM__	48	#ifndef __ASM__
49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	49	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	50	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
51	#else	51	#else
52	# define KA2PA(x) ((x) - 0x80000000)	52	# define KA2PA(x) ((x) - 0x80000000)
53	# define PA2KA(x) ((x) + 0x80000000)	53	# define PA2KA(x) ((x) + 0x80000000)
54	#endif	54	#endif
55		55
56	#ifdef KERNEL	56	#ifdef KERNEL
57		57
58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096	58	#define PTL0_ENTRIES_ARCH (2<<12) // 4096
59	#define PTL1_ENTRIES_ARCH 0	59	#define PTL1_ENTRIES_ARCH 0
60	#define PTL2_ENTRIES_ARCH 0	60	#define PTL2_ENTRIES_ARCH 0
61	/* coarse page tables used (2564 = 1KB per page) /	61	/* coarse page tables used (2564 = 1KB per page) /
62	#define PTL3_ENTRIES_ARCH (2<<8) // 256	62	#define PTL3_ENTRIES_ARCH (2<<8) // 256
63		63
64	#define PTL0_SIZE_ARCH FOUR_FRAMES	64	#define PTL0_SIZE_ARCH FOUR_FRAMES
65	#define PTL1_SIZE_ARCH 0	65	#define PTL1_SIZE_ARCH 0
66	#define PTL2_SIZE_ARCH 0	66	#define PTL2_SIZE_ARCH 0
67	#define PTL3_SIZE_ARCH ONE_FRAME	67	#define PTL3_SIZE_ARCH ONE_FRAME
68		68
69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)	69	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
70	#define PTL1_INDEX_ARCH(vaddr) 0	70	#define PTL1_INDEX_ARCH(vaddr) 0
71	#define PTL2_INDEX_ARCH(vaddr) 0	71	#define PTL2_INDEX_ARCH(vaddr) 0
72	/* TODO: ?? 0xfff or 0x0ff */	-
73	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0xfff)	72	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
74		73
75	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))	74	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t )( (((pte_level0_t)(ptl0))[(i)]).coarse_table_addr << 10 ))
76	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)	75	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
77	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)	76	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
78	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))	77	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
79		78
80	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))	79	#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
81	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)	80	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
82	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	81	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
83	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	82	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
84	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)	83	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
85		84
86	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))	85	#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
87	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT	86	#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
88	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT	87	#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
89	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))	88	#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
90		89
91	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))	90	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
92	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	91	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
93	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	92	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
94	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))	93	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
95		94
96	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	95	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
97	// TODO: ?? != 0	96	// TODO: ?? != 0
98	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )	97	#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type != 0 )
99		98
100	/* pte should point into ptl3 */	99	/* pte should point into ptl3 */
101	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)	100	#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
102	/* pte should point into ptl3 */	101	/* pte should point into ptl3 */
103	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw )	102	#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
104		103
105	#define PTE_EXECUTABLE_ARCH(pte) 1	104	#define PTE_EXECUTABLE_ARCH(pte) 1
106		105
107	#ifndef __ASM__	106	#ifndef __ASM__
108		107
109	/**	108	/**
110	* Sets the address of level 0 page table.	109	* Sets the address of level 0 page table.
111	*	110	*
112	* \param pt pointer to the page table to set	111	* \param pt pointer to the page table to set
113	*/	112	*/
114	static inline void set_ptl0_addr( pte_level0_t* pt)	113	static inline void set_ptl0_addr( pte_level0_t* pt)
115	{	114	{
116	asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"	115	asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
117	:	116	:
118	: "r"(pt)	117	: "r"(pt)
119	);	118	);
120		119
121	}	120	}
122		121
123	/**	122	/**
124	* Returns level 0 page table entry flags.	123	* Returns level 0 page table entry flags.
125	*	124	*
126	* \param pt level 0 page table	125	* \param pt level 0 page table
127	* \param i index of the entry to return	126	* \param i index of the entry to return
128	*/	127	*/
129	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)	128	static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
130	{	129	{
131	pte_level0_t *p = &pt[i];	130	pte_level0_t *p = &pt[i];
132		131
133	return (	132	return
134	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|	133	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) \|
135	( 1 << PAGE_USER_SHIFT ) \|	134	( 1 << PAGE_USER_SHIFT ) \|
136	( 1 << PAGE_READ_SHIFT ) \|	135	( 1 << PAGE_READ_SHIFT ) \|
137	( 1 << PAGE_WRITE_SHIFT ) \|	136	( 1 << PAGE_WRITE_SHIFT ) \|
138	( 1 << PAGE_EXEC_SHIFT ) \|	137	( 1 << PAGE_EXEC_SHIFT ) \|
139	( 1 << PAGE_CACHEABLE_SHIFT )	138	( 1 << PAGE_CACHEABLE_SHIFT )
140	);	139	;
141	}	140	}
142		141
143	/**	142	/**
144	* Returns level 1 page table entry flags.	143	* Returns level 1 page table entry flags.
145	*	144	*
146	* \param pt level 1 page table	145	* \param pt level 1 page table
147	* \param i index of the entry to return	146	* \param i index of the entry to return
148	*/	147	*/
149	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)	148	static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
150	{	149	{
151	pte_level1_t *p = &pt[i];	150	pte_level1_t *p = &pt[i];
152		151
153	return (	152	return
154	( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT \|	153	( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) \|
155	( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) \|	154	( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) \|
156	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) \|	155	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) \|
157	( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) \|	156	( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) \|
158	( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) \|	157	( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) \|
159	( 1 << PAGE_EXEC_SHIFT ) \|	158	( 1 << PAGE_EXEC_SHIFT ) \|
160	( p->bufferable << PAGE_CACHEABLE )	159	( p->bufferable << PAGE_CACHEABLE )
161	);	160	;
162	}	161	}
163		162
164	/**	163	/**
165	* Sets flags of level 0 page table entry.	164	* Sets flags of level 0 page table entry.
166	*	165	*
167	* \param pt level 0 page table	166	* \param pt level 0 page table
168	* \param i index of the entry to be changed	167	* \param i index of the entry to be changed
169	* \param flags new flags	168	* \param flags new flags
170	*	169	*
171	* TODO: why should_be_zero set to 1?	170	* TODO: why should_be_zero set to 1?
172	*/	171	*/
173	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)	172	static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
174	{	173	{
175	pte_level0_t *p = &pt[i];	174	pte_level0_t *p = &pt[i];
176		175
177	if (flags & PAGE_NOT_PRESENT) {	176	if (flags & PAGE_NOT_PRESENT) {
178	p->descriptor_type = pte_descriptor_not_preset;	177	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
179	p->should_be_zero = 1;	178	// p->should_be_zero = 1;
180	} else {	179	} else {
181	p->descriptor_type = pte_descriptor_coarse_table;	180	p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
182	p->should_be_zero = 0;	181	// p->should_be_zero = 0;
183	}	182	}
184	}	183	}
185		184
186	/**	185	/**
187	* Sets flags of level 1 page table entry.	186	* Sets flags of level 1 page table entry.
188	*	187	*
189	* We use same access rights for the whole page. When page is not preset then	188	* We use same access rights for the whole page. When page is not preset then
190	* store 1 in acess_rigts_3.	189	* store 1 in acess_rigts_3.
191	* TODO: why access_right_3?	190	* TODO: why access_right_3?
192	*	191	*
193	* \param pt level 1 page table	192	* \param pt level 1 page table
194	* \param i index of the entry to be changed	193	* \param i index of the entry to be changed
195	* \param flags new flags	194	* \param flags new flags
196	*/	195	*/
197	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)	196	static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
198	{	197	{
199	pte_level1_t *p = &pt[i];	198	pte_level1_t *p = &pt[i];
200		199
201	if (flags & PAGE_NOT_PRESENT) {	200	if (flags & PAGE_NOT_PRESENT) {
202	p->descriptor_type = pte_descriptor_not_preset;	201	p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
203	p->access_permission_3 = 1;	202	// p->access_permission_3 = 1;
204	} else {	203	} else {
205	p->descriptor_type = pte_descriptor_small_page;	204	p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
206	p->access_permission_3 = p->access_permission_0;	205	// p->access_permission_3 = p->access_permission_0;
207	}	206	}
208		207
209	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;	208	p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
210		209
211	/* default access permission */	210	/* default access permission */
212	p->access_permission_0 = p->access_permission_1 =	211	p->access_permission_0 = p->access_permission_1 =
213	p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;	212	p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
214		213
215	if (flags & PAGE_USER) {	214	if (flags & PAGE_USER) {
216	if (flags & PAGE_READ) {	215	if (flags & PAGE_READ) {
217	p->access_permission_0 = p->access_permission_1 =	216	p->access_permission_0 = p->access_permission_1 =
218	p->access_permission_2 = p->access_permission_3 =	217	p->access_permission_2 = p->access_permission_3 =
219	pte_ap_user_ro_kernel_rw;	218	PTE_AP_USER_RO_KERNEL_RW;
220	}	219	}
221	if (flags & PAGE_WRITE) {	220	if (flags & PAGE_WRITE) {
222	p->access_permission_0 = p->access_permission_1 =	221	p->access_permission_0 = p->access_permission_1 =
223	p->access_permission_2 = p->access_permission_3 =	222	p->access_permission_2 = p->access_permission_3 =
224	pte_ap_user_rw_kernel_rw;	223	PTE_AP_USER_RW_KERNEL_RW;
225	}	224	}
226	}	225	}
227	}	226	}
228		227
229	extern void page_arch_init(void);	228	extern void page_arch_init(void);
230		229
231	#endif /* __ASM__ */	230	#endif /* __ASM__ */
232		231
233	#endif /* KERNEL */	232	#endif /* KERNEL */
234		233
235	#endif	234	#endif
236		235
237	/** @}	236	/** @}
238	*/	237	*/
239		238
240		239