WebSVN – HelenOS – Diff – /branches/arm/boot/arch/arm32/loader/mm.h


/*
 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
 
/** @addtogroup arm32boot
 * @{
 */
/** @file
 */
 
 
#ifndef BOOT_arm32__MM_H
#define BOOT_arm32__MM_H
 
 
#ifndef __ASM__
#include "types.h"
#endif
 
 
/** Frame width. */
#define FRAME_WIDTH                 20                  /* 4KB frames */
 
/** Frame size. */
#define FRAME_SIZE                  (1 << FRAME_WIDTH)
 
/** Page size in 2-level paging which is switched on later in the kernel initialization. */
#define PAGE_SIZE                   (1 << 12)
 
 
#ifndef __ASM__
#   define KA2PA(x)                 (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x)                 (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x)                 ((x) - 0x80000000)
#   define PA2KA(x)                 ((x) + 0x80000000)
#endif
 
 
/** Number of entries in PTL0. */
#define PTL0_ENTRIES                (1<<12)             /* 4096 */
 
/** Size of an entry in PTL0. */
#define PTL0_ENTRY_SIZE             4
 
 
 
 
/** Returns number of frame the address belongs to. */
#define ADDR2PFN( addr )            ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
 
/** Describes "section" page table entry (one-level paging with 1MB sized pages). */  
#define PTE_DESCRIPTOR_SECTION      0x2
 
/** Page table access rights: user - no access, kernel - read/write. */
#define PTE_AP_USER_NO_KERNEL_RW    0x1
 
 
#ifndef __ASM__
 
 
/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
 * pages). Used only while booting the kernel. */
typedef struct {
    unsigned descriptor_type     : 2;
    unsigned bufferable          : 1;
    unsigned cacheable           : 1;
    unsigned impl_specific       : 1;
    unsigned domain              : 4;
    unsigned should_be_zero_1    : 1;
    unsigned access_permission   : 2;  
    unsigned should_be_zero_2    : 8;
    unsigned section_base_addr   : 12;
} __attribute__ ((packed)) pte_level0_section_t;
 
 
/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
extern pte_level0_section_t page_table[PTL0_ENTRIES];
 
extern void mmu_start(void);
 
 
/** Enables paging. */
static inline void enable_paging()
{
    /* c3 - each two bits controls access to the one of domains (16)
     *      0b01 - behave as a client (user) of a domain
     */
    asm volatile (
        // behave as a client of domains
        "ldr r0, =0x55555555       \n"
        "mcr p15, 0, r0, c3, c0, 0 \n"
 
        // current settings
        "mrc p15, 0, r0, c1, c0, 0 \n"
 
        // mask to enable paging
        "ldr r1, =0x00000001       \n"
        "orr r0, r0, r1            \n"
 
        // store settings
        "mcr p15, 0, r0, c1, c0, 0 \n"
        :
        :
        : "r0", "r1"
    );
}
 
 
/** Sets the address of level 0 page table to CP15 register 2.
 *
 * @param pt Address of a page table to set.
 */  
static inline void set_ptl0_address(pte_level0_section_t* pt)
{
    asm volatile (
        "mcr p15, 0, %0, c2, c0, 0 \n"
        :
        : "r"(pt)
    );
}
 
 
#endif
 
#endif
 
/** @}
 */
 
 

Rev 2323	Rev 2339
1	/*	1	/*
2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt	2	* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29		29
30	/** @addtogroup arm32boot	30	/** @addtogroup arm32boot
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36		36
37	#ifndef BOOT_arm32__MM_H	37	#ifndef BOOT_arm32__MM_H
38	#define BOOT_arm32__MM_H	38	#define BOOT_arm32__MM_H
39		39
40		40
41	#ifndef __ASM__	41	#ifndef __ASM__
42	#include "types.h"	42	#include "types.h"
43	#endif	43	#endif
44		44
45		45
46	/** Frame width. */	46	/** Frame width. */
47	#define FRAME_WIDTH 12 /* 4KB frames */	47	#define FRAME_WIDTH 20 /* 4KB frames */
48		48
49	/** Frame size. */	49	/** Frame size. */
50	#define FRAME_SIZE (1 << FRAME_WIDTH)	50	#define FRAME_SIZE (1 << FRAME_WIDTH)
51		51
52	/** Page size in 2-level paging which is switched on later in the kernel initialization. */	52	/** Page size in 2-level paging which is switched on later in the kernel initialization. */
53	#define PAGE_SIZE FRAME_SIZE	53	#define PAGE_SIZE (1 << 12)
54		54
55		55
56	#ifndef __ASM__	56	#ifndef __ASM__
57	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	57	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
58	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	58	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
59	#else	59	#else
60	# define KA2PA(x) ((x) - 0x80000000)	60	# define KA2PA(x) ((x) - 0x80000000)
61	# define PA2KA(x) ((x) + 0x80000000)	61	# define PA2KA(x) ((x) + 0x80000000)
62	#endif	62	#endif
63		63
64		64
65	/** Number of entries in PTL0. */	65	/** Number of entries in PTL0. */
66	#define PTL0_ENTRIES (1<<12) /* 4096 */	66	#define PTL0_ENTRIES (1<<12) /* 4096 */
67		67
68	/** Size of an entry in PTL0. */	68	/** Size of an entry in PTL0. */
69	#define PTL0_ENTRY_SIZE 4	69	#define PTL0_ENTRY_SIZE 4
70		70
71	/** Number of frames per 1MB section. */	-
72	#define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE )	-
73		-
74	/** Returns number of frame the address belongs to. */	71	/** Returns number of frame the address belongs to. */
75	#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH )	72	#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
76		73
77	/** Describes "section" page table entry (one-level paging with 1MB sized pages). */	74	/** Describes "section" page table entry (one-level paging with 1MB sized pages). */
78	#define PTE_DESCRIPTOR_SECTION 0x2	75	#define PTE_DESCRIPTOR_SECTION 0x2
79		76
80	/** Page table access rights: user - no access, kernel - read/write. */	77	/** Page table access rights: user - no access, kernel - read/write. */
81	#define PTE_AP_USER_NO_KERNEL_RW 0x1	78	#define PTE_AP_USER_NO_KERNEL_RW 0x1
82		79
83		80
84	#ifndef __ASM__	81	#ifndef __ASM__
85		82
86		83
87	/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized	84	/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
88	* pages). Used only while booting the kernel. */	85	* pages). Used only while booting the kernel. */
89	typedef struct {	86	typedef struct {
90	unsigned descriptor_type : 2;	87	unsigned descriptor_type : 2;
91	unsigned bufferable : 1;	88	unsigned bufferable : 1;
92	unsigned cacheable : 1;	89	unsigned cacheable : 1;
93	unsigned impl_specific : 1;	90	unsigned impl_specific : 1;
94	unsigned domain : 4;	91	unsigned domain : 4;
95	unsigned should_be_zero_1 : 1;	92	unsigned should_be_zero_1 : 1;
96	unsigned access_permission : 2;	93	unsigned access_permission : 2;
97	unsigned should_be_zero_2 : 8;	94	unsigned should_be_zero_2 : 8;
98	unsigned section_base_addr : 12;	95	unsigned section_base_addr : 12;
99	} __attribute__ ((packed)) pte_level0_section_t;	96	} __attribute__ ((packed)) pte_level0_section_t;
100		97
101		98
102	/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */	99	/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
103	extern pte_level0_section_t page_table[PTL0_ENTRIES];	100	extern pte_level0_section_t page_table[PTL0_ENTRIES];
104		101
105	extern void mmu_start(void);	102	extern void mmu_start(void);
106		103
107		104
108	/** Enables paging. */	105	/** Enables paging. */
109	static inline void enable_paging()	106	static inline void enable_paging()
110	{	107	{
111	/* c3 - each two bits controls access to the one of domains (16)	108	/* c3 - each two bits controls access to the one of domains (16)
112	* 0b01 - behave as a client (user) of a domain	109	* 0b01 - behave as a client (user) of a domain
113	*/	110	*/
114	asm volatile (	111	asm volatile (
115	// behave as a client of domains	112	// behave as a client of domains
116	"ldr r0, =0x55555555 \n"	113	"ldr r0, =0x55555555 \n"
117	"mcr p15, 0, r0, c3, c0, 0 \n"	114	"mcr p15, 0, r0, c3, c0, 0 \n"
118		115
119	// current settings	116	// current settings
120	"mrc p15, 0, r0, c1, c0, 0 \n"	117	"mrc p15, 0, r0, c1, c0, 0 \n"
121		118
122	// mask to enable paging	119	// mask to enable paging
123	"ldr r1, =0x00000001 \n"	120	"ldr r1, =0x00000001 \n"
124	"orr r0, r0, r1 \n"	121	"orr r0, r0, r1 \n"
125		122
126	// store settings	123	// store settings
127	"mcr p15, 0, r0, c1, c0, 0 \n"	124	"mcr p15, 0, r0, c1, c0, 0 \n"
128	:	125	:
129	:	126	:
130	: "r0", "r1"	127	: "r0", "r1"
131	);	128	);
132	}	129	}
133		130
134		131
135	/** Sets the address of level 0 page table to CP15 register 2.	132	/** Sets the address of level 0 page table to CP15 register 2.
136	*	133	*
137	* @param pt Address of a page table to set.	134	* @param pt Address of a page table to set.
138	*/	135	*/
139	static inline void set_ptl0_address(pte_level0_section_t* pt)	136	static inline void set_ptl0_address(pte_level0_section_t* pt)
140	{	137	{
141	asm volatile (	138	asm volatile (
142	"mcr p15, 0, %0, c2, c0, 0 \n"	139	"mcr p15, 0, %0, c2, c0, 0 \n"
143	:	140	:
144	: "r"(pt)	141	: "r"(pt)
145	);	142	);
146	}	143	}
147		144
148		145
149	#endif	146	#endif
150		147
151	#endif	148	#endif
152		149
153	/** @}	150	/** @}
154	*/	151	*/
155		152
156		153

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(root)/branches/arm/boot/arch/arm32/loader/mm.h – Rev 2323 → 2339