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1 | # |
1 | # |
2 | # Copyright (C) 2006 Martin Decky |
2 | # Copyright (C) 2006 Martin Decky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | #include "asm.h" |
29 | #include "asm.h" |
30 | #include "regname.h" |
30 | #include "regname.h" |
31 | 31 | ||
32 | .data |
32 | .data |
33 | 33 | ||
34 | flush_buffer: |
34 | flush_buffer: |
35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
35 | .space (L1_CACHE_LINES * L1_CACHE_BYTES) |
36 | 36 | ||
37 | .text |
37 | .text |
38 | 38 | ||
39 | .global halt |
39 | .global halt |
40 | .global memcpy |
40 | .global memcpy |
41 | .global jump_to_kernel |
41 | .global jump_to_kernel |
42 | 42 | ||
43 | halt: |
43 | halt: |
44 | b halt |
44 | b halt |
45 | 45 | ||
46 | memcpy: |
46 | memcpy: |
47 | srwi. r7, r5, 3 |
47 | srwi. r7, r5, 3 |
48 | addi r6, r3, -4 |
48 | addi r6, r3, -4 |
49 | addi r4, r4, -4 |
49 | addi r4, r4, -4 |
50 | beq 2f |
50 | beq 2f |
51 | 51 | ||
52 | andi. r0, r6, 3 |
52 | andi. r0, r6, 3 |
53 | mtctr r7 |
53 | mtctr r7 |
54 | bne 5f |
54 | bne 5f |
55 | 55 | ||
56 | 1: |
56 | 1: |
57 | 57 | ||
58 | lwz r7, 4(r4) |
58 | lwz r7, 4(r4) |
59 | lwzu r8, 8(r4) |
59 | lwzu r8, 8(r4) |
60 | stw r7, 4(r6) |
60 | stw r7, 4(r6) |
61 | stwu r8, 8(r6) |
61 | stwu r8, 8(r6) |
62 | bdnz 1b |
62 | bdnz 1b |
63 | 63 | ||
64 | andi. r5, r5, 7 |
64 | andi. r5, r5, 7 |
65 | 65 | ||
66 | 2: |
66 | 2: |
67 | 67 | ||
68 | cmplwi 0, r5, 4 |
68 | cmplwi 0, r5, 4 |
69 | blt 3f |
69 | blt 3f |
70 | 70 | ||
71 | lwzu r0, 4(r4) |
71 | lwzu r0, 4(r4) |
72 | addi r5, r5, -4 |
72 | addi r5, r5, -4 |
73 | stwu r0, 4(r6) |
73 | stwu r0, 4(r6) |
74 | 74 | ||
75 | 3: |
75 | 3: |
76 | 76 | ||
77 | cmpwi 0, r5, 0 |
77 | cmpwi 0, r5, 0 |
78 | beqlr |
78 | beqlr |
79 | mtctr r5 |
79 | mtctr r5 |
80 | addi r4, r4, 3 |
80 | addi r4, r4, 3 |
81 | addi r6, r6, 3 |
81 | addi r6, r6, 3 |
82 | 82 | ||
83 | 4: |
83 | 4: |
84 | 84 | ||
85 | lbzu r0, 1(r4) |
85 | lbzu r0, 1(r4) |
86 | stbu r0, 1(r6) |
86 | stbu r0, 1(r6) |
87 | bdnz 4b |
87 | bdnz 4b |
88 | blr |
88 | blr |
89 | 89 | ||
90 | 5: |
90 | 5: |
91 | 91 | ||
92 | subfic r0, r0, 4 |
92 | subfic r0, r0, 4 |
93 | mtctr r0 |
93 | mtctr r0 |
94 | 94 | ||
95 | 6: |
95 | 6: |
96 | 96 | ||
97 | lbz r7, 4(r4) |
97 | lbz r7, 4(r4) |
98 | addi r4, r4, 1 |
98 | addi r4, r4, 1 |
99 | stb r7, 4(r6) |
99 | stb r7, 4(r6) |
100 | addi r6, r6, 1 |
100 | addi r6, r6, 1 |
101 | bdnz 6b |
101 | bdnz 6b |
102 | subf r5, r0, r5 |
102 | subf r5, r0, r5 |
103 | rlwinm. r7, r5, 32-3, 3, 31 |
103 | rlwinm. r7, r5, 32-3, 3, 31 |
104 | beq 2b |
104 | beq 2b |
105 | mtctr r7 |
105 | mtctr r7 |
106 | b 1b |
106 | b 1b |
107 | 107 | ||
108 | 108 | ||
109 | jump_to_kernel: |
109 | jump_to_kernel: |
110 | 110 | ||
111 | # r3 = bootinfo (pa) |
111 | # r3 = bootinfo (pa) |
112 | # r4 = bootinfo_size |
112 | # r4 = bootinfo_size |
113 | # r5 = trans (pa) |
113 | # r5 = trans (pa) |
114 | # r6 = kernel size |
114 | # r6 = kernel size |
- | 115 | # r7 = framebuffer (pa) |
|
115 | # r7 = real_mode (pa) |
116 | # r8 = real_mode (pa) |
116 | 117 | ||
117 | mtspr srr0, r7 |
118 | mtspr srr0, r8 |
118 | 119 | ||
119 | # jumps to real_mode |
120 | # jumps to real_mode |
120 | 121 | ||
121 | mfmsr r31 |
122 | mfmsr r31 |
122 | lis r30, ~0@h |
123 | lis r30, ~0@h |
123 | ori r30, r30, ~(msr_ir | msr_dr)@l |
124 | ori r30, r30, ~(msr_ir | msr_dr)@l |
124 | and r31, r31, r30 |
125 | and r31, r31, r30 |
125 | mtspr srr1, r31 |
126 | mtspr srr1, r31 |
126 | rfi |
127 | rfi |
127 | 128 | ||
128 | .section REALMODE |
129 | .section REALMODE |
129 | .align PAGE_WIDTH |
130 | .align PAGE_WIDTH |
130 | .global real_mode |
131 | .global real_mode |
131 | 132 | ||
132 | real_mode: |
133 | real_mode: |
133 | 134 | ||
134 | # copy kernel to proper location |
135 | # copy kernel to proper location |
135 | # |
136 | # |
136 | # r5 = trans (pa) |
137 | # r5 = trans (pa) |
137 | # r6 = kernel size |
138 | # r6 = kernel size |
- | 139 | # r7 = framebuffer (pa) |
|
138 | 140 | ||
139 | li r31, PAGE_SIZE >> 2 |
141 | li r31, PAGE_SIZE >> 2 |
140 | li r30, 0 |
142 | li r30, 0 |
141 | 143 | ||
142 | page_copy: |
144 | page_copy: |
143 | 145 | ||
144 | cmpwi r6, 0 |
146 | cmpwi r6, 0 |
145 | beq copy_end |
147 | beq copy_end |
146 | 148 | ||
147 | # copy page |
149 | # copy page |
148 | 150 | ||
149 | mtctr r31 |
151 | mtctr r31 |
150 | lwz r29, 0(r5) |
152 | lwz r29, 0(r5) |
151 | 153 | ||
152 | copy_loop: |
154 | copy_loop: |
153 | 155 | ||
154 | lwz r28, 0(r29) |
156 | lwz r28, 0(r29) |
155 | stw r28, 0(r30) |
157 | stw r28, 0(r30) |
156 | 158 | ||
157 | addi r29, r29, 4 |
159 | addi r29, r29, 4 |
158 | addi r30, r30, 4 |
160 | addi r30, r30, 4 |
159 | subi r6, r6, 4 |
161 | subi r6, r6, 4 |
160 | 162 | ||
161 | cmpwi r6, 0 |
163 | cmpwi r6, 0 |
162 | beq copy_end |
164 | beq copy_end |
163 | 165 | ||
164 | bdnz copy_loop |
166 | bdnz copy_loop |
165 | 167 | ||
166 | addi r5, r5, 4 |
168 | addi r5, r5, 4 |
167 | b page_copy |
169 | b page_copy |
168 | 170 | ||
169 | copy_end: |
171 | copy_end: |
170 | 172 | ||
171 | # invalidate segment registers |
173 | # invalidate segment registers |
172 | 174 | ||
173 | li r31, 16 |
175 | li r31, 16 |
174 | mtctr r31 |
176 | mtctr r31 |
175 | li r31, 0 |
177 | li r31, 0 |
176 | li r30, 0 |
178 | li r30, 0 |
177 | 179 | ||
178 | seg_fill: |
180 | seg_fill: |
179 | 181 | ||
180 | mtsrin r30, r31 |
182 | mtsrin r30, r31 |
181 | addis r31, r31, 0x1000 # move to next SR |
183 | addis r31, r31, 0x1000 # move to next SR |
182 | 184 | ||
183 | bdnz seg_fill |
185 | bdnz seg_fill |
184 | 186 | ||
185 | # invalidate block address translation registers |
187 | # invalidate block address translation registers |
186 | 188 | ||
187 | mtspr ibat0u, r30 |
189 | mtspr ibat0u, r30 |
188 | mtspr ibat0l, r30 |
190 | mtspr ibat0l, r30 |
189 | 191 | ||
190 | mtspr ibat1u, r30 |
192 | mtspr ibat1u, r30 |
191 | mtspr ibat1l, r30 |
193 | mtspr ibat1l, r30 |
192 | 194 | ||
193 | mtspr ibat2u, r30 |
195 | mtspr ibat2u, r30 |
194 | mtspr ibat2l, r30 |
196 | mtspr ibat2l, r30 |
195 | 197 | ||
196 | mtspr ibat3u, r30 |
198 | mtspr ibat3u, r30 |
197 | mtspr ibat3l, r30 |
199 | mtspr ibat3l, r30 |
198 | 200 | ||
199 | mtspr dbat0u, r30 |
201 | mtspr dbat0u, r30 |
200 | mtspr dbat0l, r30 |
202 | mtspr dbat0l, r30 |
201 | 203 | ||
202 | mtspr dbat1u, r30 |
204 | mtspr dbat1u, r30 |
203 | mtspr dbat1l, r30 |
205 | mtspr dbat1l, r30 |
204 | 206 | ||
205 | mtspr dbat2u, r30 |
207 | mtspr dbat2u, r30 |
206 | mtspr dbat2l, r30 |
208 | mtspr dbat2l, r30 |
207 | 209 | ||
208 | mtspr dbat3u, r30 |
210 | mtspr dbat3u, r30 |
209 | mtspr dbat3l, r30 |
211 | mtspr dbat3l, r30 |
210 | 212 | ||
211 | # create identity mapping |
213 | # create identity mapping |
212 | 214 | ||
213 | # FIXME: map exactly the size of RAM |
215 | # FIXME: map exactly the size of RAM |
214 | 216 | ||
215 | lis r31, 0x8000 |
217 | lis r31, 0x8000 |
216 | ori r31, r31, 0x0ffe |
218 | ori r31, r31, 0x0ffe |
217 | 219 | ||
218 | lis r30, 0x0000 |
220 | lis r30, 0x0000 |
219 | ori r30, r30, 0x0002 |
221 | ori r30, r30, 0x0002 |
220 | 222 | ||
221 | mtspr ibat0u, r31 |
223 | mtspr ibat0u, r31 |
222 | mtspr ibat0l, r30 |
224 | mtspr ibat0l, r30 |
223 | 225 | ||
224 | mtspr dbat0u, r31 |
226 | mtspr dbat0u, r31 |
225 | mtspr dbat0l, r30 |
227 | mtspr dbat0l, r30 |
226 | 228 | ||
227 | # FIXME: temporal framebuffer mapping |
229 | # FIXME: temporal framebuffer mapping |
228 | 230 | ||
229 | lis r31, 0xf000 |
231 | lis r31, 0xf000 |
230 | ori r31, r31, 0x0ffe |
232 | ori r31, r31, 0x0ffe |
231 | 233 | ||
232 | lis r30, 0x8400 |
234 | mr r30, r7 |
233 | ori r30, r30, 0x0002 |
235 | ori r30, r30, 0x0002 |
234 | 236 | ||
235 | mtspr dbat1u, r31 |
237 | mtspr dbat1u, r31 |
236 | mtspr dbat1l, r30 |
238 | mtspr dbat1l, r30 |
237 | 239 | ||
238 | tlbia |
240 | tlbia |
239 | 241 | ||
240 | # start the kernel |
242 | # start the kernel |
241 | # |
243 | # |
242 | # r3 = bootinfo (pa) |
244 | # r3 = bootinfo (pa) |
243 | 245 | ||
244 | lis r31, KERNEL_START_ADDR@ha |
246 | lis r31, KERNEL_START_ADDR@ha |
245 | addi r31, r31, KERNEL_START_ADDR@l |
247 | addi r31, r31, KERNEL_START_ADDR@l |
246 | 248 | ||
247 | mtspr srr0, r31 |
249 | mtspr srr0, r31 |
248 | 250 | ||
249 | mfmsr r31 |
251 | mfmsr r31 |
250 | ori r31, r31, (msr_ir | msr_dr)@l |
252 | ori r31, r31, (msr_ir | msr_dr)@l |
251 | mtspr srr1, r31 |
253 | mtspr srr1, r31 |
252 | 254 | ||
- | 255 | sync |
|
- | 256 | isync |
|
253 | rfi |
257 | rfi |
254 | 258 | ||
255 | .align PAGE_WIDTH |
259 | .align PAGE_WIDTH |
256 | .global trans |
260 | .global trans |
257 | trans: |
261 | trans: |
258 | .space (TRANS_SIZE * TRANS_ITEM_SIZE) |
262 | .space (TRANS_SIZE * TRANS_ITEM_SIZE) |
259 | 263 |