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| Rev 1 | Rev 51 | ||
|---|---|---|---|
| 1 | + implement true memory management |
1 | + implement true memory management |
| 2 | + [ia32] use int 0x15 ax=0xe820 to get memory map and memory size |
2 | + [ia32] use int 0x15 ax=0xe820 to get memory map and memory size |
| 3 | + [mips] use some heuristics to get memory map and memory size |
3 | + [mips] use some heuristics to get memory map and memory size |
| 4 | + reimplement heap so that it can allocate/deallocate itself frames as necessary |
4 | + reimplement heap so that it can allocate/deallocate itself frames as necessary |
| 5 | + provide native four-level portable page table interface |
5 | + provide native four-level portable page table interface |
| 6 | + every architecture uses its native page table format |
6 | + every architecture uses its native page table format |
| 7 | + kernel provides unified four-level page table interface for all architectures |
7 | + kernel provides unified four-level page table interface for all architectures |
| 8 | + track usage of frames containing middle-level page tables (frame leak) |
8 | + track usage of frames containing middle-level page tables (frame leak) |
| 9 | 9 | ||
| 10 | + get user mode support for all architectures |
10 | + get user mode support for all architectures |
| 11 | 11 | ||
| 12 | + when a new thread enters scheduler, at least one CPU in |
- | |
| 13 | cpu_sleep() should be woken up by an IPI |
- | |
| 14 | + save/restore floating point context on context switch |
12 | + save/restore floating point context on context switch |
| 15 | + [ia32] lazy context switch using TS flag |
13 | + [ia32] lazy context switch using TS flag |
| 16 | + [ia32] review privilege separation |
14 | + [ia32] review privilege separation |
| 17 | + zero IOPL in EFLAGS |
15 | + zero IOPL in EFLAGS |
| 18 | + before IRET (from SYSCALL), zero NT in EFLAGS |
16 | + before IRET (from SYSCALL), zero NT in EFLAGS |
| 19 | + [ia32] review the cache controling bits in CR0 register |
17 | + [ia32] review the cache controling bits in CR0 register |
| 20 | + [ia32] zero the alignment exception bit in EFLAGS |
18 | + [ia32] zero the alignment exception bit in EFLAGS |
| 21 | + make emulated architectures also work on real hardware |
19 | + make emulated architectures also work on real hardware |
| 22 | + bring in support for other architectures (e.g. PowerPC) |
20 | + bring in support for other architectures (e.g. PowerPC) |
| 23 | 21 | ||