WebSVN – HelenOS-historic – Diff – /SPARTAN/trunk/arch/mips/src/interrupt.c


/*
 * Copyright (C) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <arch/cp0.h>
#include <time/clock.h>
#include <panic.h>
 
pri_t cpu_priority_high(void)
{
    pri_t pri = (pri_t) cp0_status_read();
    cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
    return pri;
}
 
pri_t cpu_priority_low(void)
{
    pri_t pri = (pri_t) cp0_status_read();
    cp0_status_write(pri | cp0_status_ie_enabled_bit);
    return pri;
}
 
void cpu_priority_restore(pri_t pri)
{
    cp0_status_write(cp0_status_read() | (pri & cp0_status_ie_enabled_bit));
}
 
pri_t cpu_priority_read(void)
{
    return cp0_status_read();
}
 
 
void interrupt(void)
{
    __u32 cause;
    int i;
   
    /* decode interrupt number and process the interrupt */
    cause = (cp0_cause_read() >> 8) &0xff;
   
    for (i = 0; i < 8; i++) {
        if (cause & (1 << i)) {
            switch (i) {
                case 0: /* SW0 - Software interrupt 0 */
                    cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */
                    break;
                case 1: /* SW1 - Software interrupt 1 */
                    cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */
                    break;
                case 2: /* IRQ0 */
                case 3: /* IRQ1 */
                case 4: /* IRQ2 */
                case 5: /* IRQ3 */
                case 6: /* IRQ4 */
                    panic("unhandled interrupt %d\n", i);
                    break;
                case 7: /* Timer Interrupt */
                    cp0_compare_write(cp0_compare_value); /* clear timer interrupt */
                    /* start counting over again */
                    cp0_count_write(0);
                    clock();
                    break;
            }
        }
    }
 
}
 

Rev 125	Rev 319
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/interrupt.h>	29	#include <arch/interrupt.h>
30	#include <arch/types.h>	30	#include <arch/types.h>
31	#include <arch.h>	31	#include <arch.h>
32	#include <arch/cp0.h>	32	#include <arch/cp0.h>
33	#include <time/clock.h>	33	#include <time/clock.h>
34	#include <panic.h>	34	#include <panic.h>
35		35
36	pri_t cpu_priority_high(void)	36	pri_t cpu_priority_high(void)
37	{	37	{
38	pri_t pri = (pri_t) cp0_status_read();	38	pri_t pri = (pri_t) cp0_status_read();
39	cp0_status_write(pri & ~cp0_status_ie_enabled_bit);	39	cp0_status_write(pri & ~cp0_status_ie_enabled_bit);
40	return pri;	40	return pri;
41	}	41	}
42		42
43	pri_t cpu_priority_low(void)	43	pri_t cpu_priority_low(void)
44	{	44	{
45	pri_t pri = (pri_t) cp0_status_read();	45	pri_t pri = (pri_t) cp0_status_read();
46	cp0_status_write(pri \| cp0_status_ie_enabled_bit);	46	cp0_status_write(pri \| cp0_status_ie_enabled_bit);
47	return pri;	47	return pri;
48	}	48	}
49		49
50	void cpu_priority_restore(pri_t pri)	50	void cpu_priority_restore(pri_t pri)
51	{	51	{
52	cp0_status_write(cp0_status_read() \| (pri & cp0_status_ie_enabled_bit));	52	cp0_status_write(cp0_status_read() \| (pri & cp0_status_ie_enabled_bit));
53	}	53	}
54		54
55	pri_t cpu_priority_read(void)	55	pri_t cpu_priority_read(void)
56	{	56	{
57	return cp0_status_read();	57	return cp0_status_read();
58	}	58	}
59		59
60		60
61	void interrupt(void)	61	void interrupt(void)
62	{	62	{
63	__u32 cause;	63	__u32 cause;
64	int i;	64	int i;
65		65
66	/* decode interrupt number and process the interrupt */	66	/* decode interrupt number and process the interrupt */
67	cause = (cp0_cause_read() >> 8) &0xff;	67	cause = (cp0_cause_read() >> 8) &0xff;
68		68
69	for (i = 0; i < 8; i++) {	69	for (i = 0; i < 8; i++) {
70	if (cause & (1 << i)) {	70	if (cause & (1 << i)) {
71	switch (i) {	71	switch (i) {
72	case 0: /* SW0 - Software interrupt 0 */	72	case 0: /* SW0 - Software interrupt 0 */
73	cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */	73	cp0_cause_write(cause & ~(1 << 8)); /* clear SW0 interrupt */
74	break;	74	break;
75	case 1: /* SW1 - Software interrupt 1 */	75	case 1: /* SW1 - Software interrupt 1 */
76	cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */	76	cp0_cause_write(cause & ~(1 << 9)); /* clear SW1 interrupt */
77	break;	77	break;
78	case 2: /* IRQ0 */	78	case 2: /* IRQ0 */
79	case 3: /* IRQ1 */	79	case 3: /* IRQ1 */
80	case 4: /* IRQ2 */	80	case 4: /* IRQ2 */
81	case 5: /* IRQ3 */	81	case 5: /* IRQ3 */
82	case 6: /* IRQ4 */	82	case 6: /* IRQ4 */
83	panic("unhandled interrupt %d\n", i);	83	panic("unhandled interrupt %d\n", i);
84	break;	84	break;
85	case 7: /* Timer Interrupt */	85	case 7: /* Timer Interrupt */
86	cp0_compare_write(cp0_compare_value); /* clear timer interrupt */	86	cp0_compare_write(cp0_compare_value); /* clear timer interrupt */
87	/* start counting over again */	87	/* start counting over again */
88	cp0_count_write(0);	88	cp0_count_write(0);
89	clock();	89	clock();
90	break;	90	break;
91	}	91	}
92	}	92	}
93	}	93	}
94		94
95	}	95	}
96		96

Subversion Repositories HelenOS-historic

(root)/SPARTAN/trunk/arch/mips/src/interrupt.c – Rev 125 → 319