WebSVN – HelenOS – Diff – /SPARTAN/trunk/arch/ia64/src/context.S


#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
#   notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
#   notice, this list of conditions and the following disclaimer in the
#   documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
#   derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
.text
 
.global context_save_arch
.global context_restore_arch
 
context_save_arch:
	alloc loc0 = ar.pfs, 1, 8, 0, 0
	mov loc1 = ar.unat	;;
	/* loc2 */
	mov loc3 = ar.rsc
 
	.auto
 
	/*
	 * Flush dirty registers to backing store.
	 * After this ar.bsp and ar.bspstore are equal.
	 */
	flushrs
	mov loc4 = ar.bsp	
	
	/*
	 * Put RSE to enforced lazy mode.
	 * So that ar.rnat can be read.
	 */
	movl loc5 = ~3
	and loc5 = loc3, loc5
	mov ar.rsc = loc5
	mov loc5 = ar.rnat
 
	.explicit
 
	mov loc6 = ar.lc
	
	/*
	 * Save application registers
	 */
	st8 [in0] = loc0, 8	;;	/* save ar.pfs */
	st8 [in0] = loc1, 8	;;	/* save ar.unat (caller) */
	mov loc2 = in0		;;
	add in0 = 8, in0	;;	/* skip ar.unat (callee) */
	st8 [in0] = loc3, 8	;;	/* save ar.rsc */
	st8 [in0] = loc4, 8	;;	/* save ar.bsp */
	st8 [in0] = loc5, 8	;;	/* save ar.rnat */
	st8 [in0] = loc6, 8	;;	/* save ar.lc */
	
	/*
	 * Save general registers including NaT bits
	 */
	st8.spill [in0] = r1, 8		;;
	st8.spill [in0] = r4, 8		;;
	st8.spill [in0] = r5, 8		;;
	st8.spill [in0] = r6, 8		;;
	st8.spill [in0] = r7, 8		;;
	st8.spill [in0] = r12, 8	;;	/* save sp */
	st8.spill [in0] = r13, 8	;;
 
	mov loc3 = ar.unat		;;
	st8 [loc2] = loc3		/* save ar.unat (callee) */
 
	/*
	 * Save branch registers
	 */
	mov loc2 = b0		;;
	st8 [in0] = loc2, 8		/* save pc */
	mov loc3 = b1		;;
	st8 [in0] = loc3, 8
	mov loc4 = b2		;;
	st8 [in0] = loc4, 8
	mov loc5 = b3		;;
	st8 [in0] = loc5, 8
	mov loc6 = b4		;;
	st8 [in0] = loc6, 8
	mov loc7 = b5		;;
	st8 [in0] = loc7, 8
 
	/*
	 * Save predicate registers
	 */
	mov loc2 = pr		;;
	st8 [in0] = loc2, 8
	
	mov ar.unat = loc1
	
	add r8 = r0, r0, 1 		/* context_save returns 1 */
	br.ret.sptk.many b0
 
context_restore_arch:
	alloc loc0 = ar.pfs, 1, 9, 0, 0	;;
 
	ld8 loc0 = [in0], 8	;;	/* load ar.pfs */
	ld8 loc1 = [in0], 8	;;	/* load ar.unat (caller) */
	ld8 loc2 = [in0], 8	;;	/* load ar.unat (callee) */
	ld8 loc3 = [in0], 8	;;	/* load ar.rsc */
	ld8 loc4 = [in0], 8	;;	/* load ar.bsp */
	ld8 loc5 = [in0], 8	;;	/* load ar.rnat */
	ld8 loc6 = [in0], 8	;;	/* load ar.lc */
	
	.auto	
 
	/*
	 * Invalidate the ALAT
	 */
	invala
 
	/*
	 * Put RSE to enforced lazy mode.
	 * So that ar.bspstore and ar.rnat can be written.
	 */
	movl loc8 = ~3
	and loc8 = loc3, loc8
	mov ar.rsc = loc8
 
	/*
	 * Flush dirty registers to backing store.
	 * We do this because we want the following move
	 * to ar.bspstore to assign the same value to ar.bsp.
	 */
	flushrs
 
	/*
	 * Restore application registers
	 */
	mov ar.bspstore = loc4	/* rse.bspload = ar.bsp = ar.bspstore = loc4 */
	mov ar.rnat = loc5
	mov ar.pfs = loc0
	mov ar.rsc = loc3
 
	.explicit
 
	mov ar.unat = loc2	;;
	mov ar.lc = loc6
	
	/*
	 * Restore general registers including NaT bits
	 */
	ld8.fill r1 = [in0], 8	;;
	ld8.fill r4 = [in0], 8	;;
	ld8.fill r5 = [in0], 8	;;
	ld8.fill r6 = [in0], 8	;;
	ld8.fill r7 = [in0], 8	;;
	ld8.fill r12 = [in0], 8	;;	/* restore sp */
	ld8.fill r13 = [in0], 8	;;
 
	/* 
	 * Restore branch registers
	 */
	ld8 loc2 = [in0], 8	;;	/* restore pc */
	mov b0 = loc2
	ld8 loc3 = [in0], 8	;;
	mov b1 = loc3
	ld8 loc4 = [in0], 8	;;
	mov b2 = loc4
	ld8 loc5 = [in0], 8	;;
	mov b3 = loc5
	ld8 loc6 = [in0], 8	;;
	mov b4 = loc6
	ld8 loc7 = [in0], 8	;;
	mov b5 = loc7
 
	/*
	 * Restore predicate registers
	 */
	ld8 loc2 = [in0], 8	;;
	mov pr = loc2, ~0
	
	mov ar.unat = loc1
	
	mov r8 = r0			/* context_restore returns 0 */
	br.ret.sptk.many b0
 

Rev 414	Rev 416
1	#	1	#
2	# Copyright (C) 2005 Jakub Jermar	2	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	3	# All rights reserved.
4	#	4	#
5	# Redistribution and use in source and binary forms, with or without	5	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	6	# modification, are permitted provided that the following conditions
7	# are met:	7	# are met:
8	#	8	#
9	# - Redistributions of source code must retain the above copyright	9	# - Redistributions of source code must retain the above copyright
10	# notice, this list of conditions and the following disclaimer.	10	# notice, this list of conditions and the following disclaimer.
11	# - Redistributions in binary form must reproduce the above copyright	11	# - Redistributions in binary form must reproduce the above copyright
12	# notice, this list of conditions and the following disclaimer in the	12	# notice, this list of conditions and the following disclaimer in the
13	# documentation and/or other materials provided with the distribution.	13	# documentation and/or other materials provided with the distribution.
14	# - The name of the author may not be used to endorse or promote products	14	# - The name of the author may not be used to endorse or promote products
15	# derived from this software without specific prior written permission.	15	# derived from this software without specific prior written permission.
16	#	16	#
17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	27	#
28		28
29	.text	29	.text
30		30
31	.global context_save_arch	31	.global context_save_arch
32	.global context_restore_arch	32	.global context_restore_arch
33		33
34	context_save_arch:	34	context_save_arch:
35	alloc loc0 = ar.pfs, 1, 8, 0, 0	35	alloc loc0 = ar.pfs, 1, 8, 0, 0
36	mov loc1 = ar.unat ;;	36	mov loc1 = ar.unat ;;
37	/* loc2 */	37	/* loc2 */
38	mov loc3 = ar.rsc	38	mov loc3 = ar.rsc
39		39
40	.auto	40	.auto
41		41
42	/*	42	/*
43	* Flush dirty registers to backing store.	43	* Flush dirty registers to backing store.
44	* After this ar.bsp and ar.bspstore are equal.	44	* After this ar.bsp and ar.bspstore are equal.
45	*/	45	*/
46	flushrs	46	flushrs
47	mov loc4 = ar.bsp	47	mov loc4 = ar.bsp
48		48
49	/*	49	/*
50	* Put RSE to enforced lazy mode.	50	* Put RSE to enforced lazy mode.
51	* So that ar.rnat can be read.	51	* So that ar.rnat can be read.
52	*/	52	*/
53	movl loc5 = ~3	53	movl loc5 = ~3
54	and loc5 = loc3, loc5	54	and loc5 = loc3, loc5
55	mov ar.rsc = loc5	55	mov ar.rsc = loc5
56	mov loc5 = ar.rnat	56	mov loc5 = ar.rnat
57		57
58	.explicit	58	.explicit
59		59
60	mov loc6 = ar.lc	60	mov loc6 = ar.lc
61		61
62	/*	62	/*
63	* Save application registers	63	* Save application registers
64	*/	64	*/
65	st8 [in0] = loc0, 8 ;; /* save ar.pfs */	65	st8 [in0] = loc0, 8 ;; /* save ar.pfs */
66	st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */	66	st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */
67	mov loc2 = in0 ;;	67	mov loc2 = in0 ;;
68	add in0 = 8, in0 ;; /* skip ar.unat (callee) */	68	add in0 = 8, in0 ;; /* skip ar.unat (callee) */
69	st8 [in0] = loc3, 8 ;; /* save ar.rsc */	69	st8 [in0] = loc3, 8 ;; /* save ar.rsc */
70	st8 [in0] = loc4, 8 ;; /* save ar.bsp */	70	st8 [in0] = loc4, 8 ;; /* save ar.bsp */
71	st8 [in0] = loc5, 8 ;; /* save ar.rnat */	71	st8 [in0] = loc5, 8 ;; /* save ar.rnat */
72	st8 [in0] = loc6, 8 ;; /* save ar.lc */	72	st8 [in0] = loc6, 8 ;; /* save ar.lc */
73		73
74	/*	74	/*
75	* Save general registers including NaT bits	75	* Save general registers including NaT bits
76	*/	76	*/
77	st8.spill [in0] = r1, 8 ;;	77	st8.spill [in0] = r1, 8 ;;
78	st8.spill [in0] = r4, 8 ;;	78	st8.spill [in0] = r4, 8 ;;
79	st8.spill [in0] = r5, 8 ;;	79	st8.spill [in0] = r5, 8 ;;
80	st8.spill [in0] = r6, 8 ;;	80	st8.spill [in0] = r6, 8 ;;
81	st8.spill [in0] = r7, 8 ;;	81	st8.spill [in0] = r7, 8 ;;
82	st8.spill [in0] = r12, 8 ;; /* save sp */	82	st8.spill [in0] = r12, 8 ;; /* save sp */
83	st8.spill [in0] = r13, 8 ;;	83	st8.spill [in0] = r13, 8 ;;
84		84
85	mov loc3 = ar.unat ;;	85	mov loc3 = ar.unat ;;
86	st8 [loc2] = loc3 /* save ar.unat (callee) */	86	st8 [loc2] = loc3 /* save ar.unat (callee) */
87		87
88	/*	88	/*
89	* Save branch registers	89	* Save branch registers
90	*/	90	*/
91	mov loc2 = b0 ;;	91	mov loc2 = b0 ;;
92	st8 [in0] = loc2, 8 /* save pc */	92	st8 [in0] = loc2, 8 /* save pc */
93	mov loc3 = b1 ;;	93	mov loc3 = b1 ;;
94	st8 [in0] = loc3, 8	94	st8 [in0] = loc3, 8
95	mov loc4 = b2 ;;	95	mov loc4 = b2 ;;
96	st8 [in0] = loc4, 8	96	st8 [in0] = loc4, 8
97	mov loc5 = b3 ;;	97	mov loc5 = b3 ;;
98	st8 [in0] = loc5, 8	98	st8 [in0] = loc5, 8
99	mov loc6 = b4 ;;	99	mov loc6 = b4 ;;
100	st8 [in0] = loc6, 8	100	st8 [in0] = loc6, 8
101	mov loc7 = b5 ;;	101	mov loc7 = b5 ;;
102	st8 [in0] = loc7, 8	102	st8 [in0] = loc7, 8
103		103
104	/*	104	/*
105	* Save predicate registers	105	* Save predicate registers
106	*/	106	*/
107	mov loc2 = pr ;;	107	mov loc2 = pr ;;
108	st8 [in0] = loc2, 8	108	st8 [in0] = loc2, 8
109		109
110	mov ar.unat = loc1	110	mov ar.unat = loc1
111		111
112	add r8 = r0, r0, 1 /* context_save returns 1 */	112	add r8 = r0, r0, 1 /* context_save returns 1 */
113	br.ret.sptk.many b0	113	br.ret.sptk.many b0
114		114
115	context_restore_arch:	115	context_restore_arch:
116	alloc loc0 = ar.pfs, 1, 8, 0, 0 ;;	116	alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
117		117
118	ld8 loc0 = [in0], 8 ;; /* load ar.pfs */	118	ld8 loc0 = [in0], 8 ;; /* load ar.pfs */
119	ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */	119	ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */
120	ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */	120	ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */
121	ld8 loc3 = [in0], 8 ;; /* load ar.rsc */	121	ld8 loc3 = [in0], 8 ;; /* load ar.rsc */
122	ld8 loc4 = [in0], 8 ;; /* load ar.bsp */	122	ld8 loc4 = [in0], 8 ;; /* load ar.bsp */
123	ld8 loc5 = [in0], 8 ;; /* load ar.rnat */	123	ld8 loc5 = [in0], 8 ;; /* load ar.rnat */
124	ld8 loc6 = [in0], 8 ;; /* load ar.lc */	124	ld8 loc6 = [in0], 8 ;; /* load ar.lc */
125		125
126	.auto	126	.auto
127		127
128	/*	128	/*
129	* Invalidate the ALAT	129	* Invalidate the ALAT
130	*/	130	*/
131	invala	131	invala
132		132
133	/*	133	/*
-		134	* Put RSE to enforced lazy mode.
134	* Restore application registers	135	* So that ar.bspstore and ar.rnat can be written.
-		136	*/
-		137	movl loc8 = ~3
-		138	and loc8 = loc3, loc8
-		139	mov ar.rsc = loc8
-		140
-		141	/*
-		142	* Flush dirty registers to backing store.
-		143	* We do this because we want the following move
-		144	* to ar.bspstore to assign the same value to ar.bsp.
135	*/	145	*/
-		146	flushrs
136		147
-		148	/*
137	/* TODO: ensure RSE lazy mode */	149	* Restore application registers
-		150	*/
138	mov ar.bspstore = loc4	151	mov ar.bspstore = loc4 /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
139	mov ar.rnat = loc5	152	mov ar.rnat = loc5
140	mov ar.pfs = loc0	153	mov ar.pfs = loc0
141	mov ar.rsc = loc3	154	mov ar.rsc = loc3
142		155
143	.explicit	156	.explicit
144		157
145	mov ar.unat = loc2 ;;	158	mov ar.unat = loc2 ;;
146	mov ar.lc = loc6	159	mov ar.lc = loc6
147		160
148	/*	161	/*
149	* Restore general registers including NaT bits	162	* Restore general registers including NaT bits
150	*/	163	*/
151	ld8.fill r1 = [in0], 8 ;;	164	ld8.fill r1 = [in0], 8 ;;
152	ld8.fill r4 = [in0], 8 ;;	165	ld8.fill r4 = [in0], 8 ;;
153	ld8.fill r5 = [in0], 8 ;;	166	ld8.fill r5 = [in0], 8 ;;
154	ld8.fill r6 = [in0], 8 ;;	167	ld8.fill r6 = [in0], 8 ;;
155	ld8.fill r7 = [in0], 8 ;;	168	ld8.fill r7 = [in0], 8 ;;
156	ld8.fill r12 = [in0], 8 ;; /* restore sp */	169	ld8.fill r12 = [in0], 8 ;; /* restore sp */
157	ld8.fill r13 = [in0], 8 ;;	170	ld8.fill r13 = [in0], 8 ;;
158		171
159	/*	172	/*
160	* Restore branch registers	173	* Restore branch registers
161	*/	174	*/
162	ld8 loc2 = [in0], 8 ;; /* restore pc */	175	ld8 loc2 = [in0], 8 ;; /* restore pc */
163	mov b0 = loc2	176	mov b0 = loc2
164	ld8 loc3 = [in0], 8 ;;	177	ld8 loc3 = [in0], 8 ;;
165	mov b1 = loc3	178	mov b1 = loc3
166	ld8 loc4 = [in0], 8 ;;	179	ld8 loc4 = [in0], 8 ;;
167	mov b2 = loc4	180	mov b2 = loc4
168	ld8 loc5 = [in0], 8 ;;	181	ld8 loc5 = [in0], 8 ;;
169	mov b3 = loc5	182	mov b3 = loc5
170	ld8 loc6 = [in0], 8 ;;	183	ld8 loc6 = [in0], 8 ;;
171	mov b4 = loc6	184	mov b4 = loc6
172	ld8 loc7 = [in0], 8 ;;	185	ld8 loc7 = [in0], 8 ;;
173	mov b5 = loc7	186	mov b5 = loc7
174		187
175	/*	188	/*
176	* Restore predicate registers	189	* Restore predicate registers
177	*/	190	*/
178	ld8 loc2 = [in0], 8 ;;	191	ld8 loc2 = [in0], 8 ;;
179	mov pr = loc2, ~0	192	mov pr = loc2, ~0
180		193
181	mov ar.unat = loc1	194	mov ar.unat = loc1
182		195
183	mov r8 = r0 /* context_restore returns 0 */	196	mov r8 = r0 /* context_restore returns 0 */
184	br.ret.sptk.many b0	197	br.ret.sptk.many b0
185		198

Subversion Repositories HelenOS

(root)/SPARTAN/trunk/arch/ia64/src/context.S – Rev 414 → 416