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| 1 | /* |
1 | /* |
| 2 | * Copyright (C) 2005 Jakub Jermar |
2 | * Copyright (C) 2005 Jakub Jermar |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __ia64_REGISTER_H__ |
29 | #ifndef __ia64_REGISTER_H__ |
| 30 | #define __ia64_REGISTER_H__ |
30 | #define __ia64_REGISTER_H__ |
| 31 | 31 | ||
| - | 32 | #ifndef __ASM__ |
|
| 32 | #include <arch/types.h> |
33 | #include <arch/types.h> |
| - | 34 | #endif |
|
| 33 | 35 | ||
| 34 | #define CR_IVR_MASK 0xf |
36 | #define CR_IVR_MASK 0xf |
| 35 | #define PSR_I_MASK 0x4000 |
37 | #define PSR_I_MASK 0x4000 |
| - | 38 | #define PSR_IC_MASK 0x2000 |
|
| 36 | 39 | ||
| 37 | /** Application registers. */ |
40 | /** Application registers. */ |
| 38 | #define AR_KR0 0 |
41 | #define AR_KR0 0 |
| 39 | #define AR_KR1 1 |
42 | #define AR_KR1 1 |
| 40 | #define AR_KR2 2 |
43 | #define AR_KR2 2 |
| 41 | #define AR_KR3 3 |
44 | #define AR_KR3 3 |
| 42 | #define AR_KR4 4 |
45 | #define AR_KR4 4 |
| 43 | #define AR_KR5 5 |
46 | #define AR_KR5 5 |
| 44 | #define AR_KR6 6 |
47 | #define AR_KR6 6 |
| 45 | #define AR_KR7 7 |
48 | #define AR_KR7 7 |
| 46 | /* AR 8-15 reserved */ |
49 | /* AR 8-15 reserved */ |
| 47 | #define AR_RSC 16 |
50 | #define AR_RSC 16 |
| 48 | #define AR_BSP 17 |
51 | #define AR_BSP 17 |
| 49 | #define AR_BSPSTORE 18 |
52 | #define AR_BSPSTORE 18 |
| 50 | #define AR_RNAT 19 |
53 | #define AR_RNAT 19 |
| 51 | /* AR 20 reserved */ |
54 | /* AR 20 reserved */ |
| 52 | #define AR_FCR 21 |
55 | #define AR_FCR 21 |
| 53 | /* AR 22-23 reserved */ |
56 | /* AR 22-23 reserved */ |
| 54 | #define AR_EFLAG 24 |
57 | #define AR_EFLAG 24 |
| 55 | #define AR_CSD 25 |
58 | #define AR_CSD 25 |
| 56 | #define AR_SSD 26 |
59 | #define AR_SSD 26 |
| 57 | #define AR_CFLG 27 |
60 | #define AR_CFLG 27 |
| 58 | #define AR_FSR 28 |
61 | #define AR_FSR 28 |
| 59 | #define AR_FIR 29 |
62 | #define AR_FIR 29 |
| 60 | #define AR_FDR 30 |
63 | #define AR_FDR 30 |
| 61 | /* AR 31 reserved */ |
64 | /* AR 31 reserved */ |
| 62 | #define AR_CCV 32 |
65 | #define AR_CCV 32 |
| 63 | /* AR 33-35 reserved */ |
66 | /* AR 33-35 reserved */ |
| 64 | #define AR_UNAT 36 |
67 | #define AR_UNAT 36 |
| 65 | /* AR 37-39 reserved */ |
68 | /* AR 37-39 reserved */ |
| 66 | #define AR_FPSR 40 |
69 | #define AR_FPSR 40 |
| 67 | /* AR 41-43 reserved */ |
70 | /* AR 41-43 reserved */ |
| 68 | #define AR_ITC 44 |
71 | #define AR_ITC 44 |
| 69 | /* AR 45-47 reserved */ |
72 | /* AR 45-47 reserved */ |
| 70 | /* AR 48-63 ignored */ |
73 | /* AR 48-63 ignored */ |
| 71 | #define AR_PFS 64 |
74 | #define AR_PFS 64 |
| 72 | #define AR_LC 65 |
75 | #define AR_LC 65 |
| 73 | #define AR_EC 66 |
76 | #define AR_EC 66 |
| 74 | /* AR 67-111 reserved */ |
77 | /* AR 67-111 reserved */ |
| 75 | /* AR 112-127 ignored */ |
78 | /* AR 112-127 ignored */ |
| 76 | 79 | ||
| 77 | /** Control registers. */ |
80 | /** Control registers. */ |
| 78 | #define CR_DCR 0 |
81 | #define CR_DCR 0 |
| 79 | #define CR_ITM 1 |
82 | #define CR_ITM 1 |
| 80 | #define CR_IVA 2 |
83 | #define CR_IVA 2 |
| 81 | /* CR3-CR7 reserved */ |
84 | /* CR3-CR7 reserved */ |
| 82 | #define CR_PTA 8 |
85 | #define CR_PTA 8 |
| 83 | /* CR9-CR15 reserved */ |
86 | /* CR9-CR15 reserved */ |
| 84 | #define CR_IPSR 16 |
87 | #define CR_IPSR 16 |
| 85 | #define CR_ISR 17 |
88 | #define CR_ISR 17 |
| 86 | /* CR18 reserved */ |
89 | /* CR18 reserved */ |
| 87 | #define CR_IIP 19 |
90 | #define CR_IIP 19 |
| 88 | #define CR_IFA 20 |
91 | #define CR_IFA 20 |
| 89 | #define CR_ITIR 21 |
92 | #define CR_ITIR 21 |
| 90 | #define CR_IIPA 22 |
93 | #define CR_IIPA 22 |
| 91 | #define CR_IFS 23 |
94 | #define CR_IFS 23 |
| 92 | #define CR_IIM 24 |
95 | #define CR_IIM 24 |
| 93 | #define CR_IHA 25 |
96 | #define CR_IHA 25 |
| 94 | /* CR26-CR63 reserved */ |
97 | /* CR26-CR63 reserved */ |
| 95 | #define CR_LID 64 |
98 | #define CR_LID 64 |
| 96 | #define CR_IVR 65 |
99 | #define CR_IVR 65 |
| 97 | #define CR_TPR 66 |
100 | #define CR_TPR 66 |
| 98 | #define CR_EOI 67 |
101 | #define CR_EOI 67 |
| 99 | #define CR_IRR0 68 |
102 | #define CR_IRR0 68 |
| 100 | #define CR_IRR1 69 |
103 | #define CR_IRR1 69 |
| 101 | #define CR_IRR2 70 |
104 | #define CR_IRR2 70 |
| 102 | #define CR_IRR3 71 |
105 | #define CR_IRR3 71 |
| 103 | #define CR_ITV 72 |
106 | #define CR_ITV 72 |
| 104 | #define CR_PMV 73 |
107 | #define CR_PMV 73 |
| 105 | #define CR_CMCV 74 |
108 | #define CR_CMCV 74 |
| 106 | /* CR75-CR79 reserved */ |
109 | /* CR75-CR79 reserved */ |
| 107 | #define CR_LRR0 80 |
110 | #define CR_LRR0 80 |
| 108 | #define CR_LRR1 81 |
111 | #define CR_LRR1 81 |
| 109 | /* CR82-CR127 reserved */ |
112 | /* CR82-CR127 reserved */ |
| 110 | 113 | ||
| - | 114 | #ifndef __ASM__ |
|
| 111 | /** External Interrupt Vector Register */ |
115 | /** External Interrupt Vector Register */ |
| 112 | union cr_ivr { |
116 | union cr_ivr { |
| 113 | __u8 vector; |
117 | __u8 vector; |
| 114 | __u64 value; |
118 | __u64 value; |
| 115 | }; |
119 | }; |
| 116 | 120 | ||
| 117 | typedef union cr_ivr cr_ivr_t; |
121 | typedef union cr_ivr cr_ivr_t; |
| 118 | 122 | ||
| 119 | /** Task Priority Register */ |
123 | /** Task Priority Register */ |
| 120 | union cr_tpr { |
124 | union cr_tpr { |
| 121 | struct { |
125 | struct { |
| 122 | unsigned : 4; |
126 | unsigned : 4; |
| 123 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
127 | unsigned mic: 4; /**< Mask Interrupt Class. */ |
| 124 | unsigned : 8; |
128 | unsigned : 8; |
| 125 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
129 | unsigned mmi: 1; /**< Mask Maskable Interrupts. */ |
| 126 | } __attribute__ ((packed)); |
130 | } __attribute__ ((packed)); |
| 127 | __u64 value; |
131 | __u64 value; |
| 128 | }; |
132 | }; |
| 129 | 133 | ||
| 130 | typedef union cr_tpr cr_tpr_t; |
134 | typedef union cr_tpr cr_tpr_t; |
| 131 | 135 | ||
| 132 | /** Interval Timer Vector */ |
136 | /** Interval Timer Vector */ |
| 133 | union cr_itv { |
137 | union cr_itv { |
| 134 | struct { |
138 | struct { |
| 135 | unsigned vector : 8; |
139 | unsigned vector : 8; |
| 136 | unsigned : 4; |
140 | unsigned : 4; |
| 137 | unsigned : 1; |
141 | unsigned : 1; |
| 138 | unsigned : 3; |
142 | unsigned : 3; |
| 139 | unsigned m : 1; /**< Mask. */ |
143 | unsigned m : 1; /**< Mask. */ |
| 140 | } __attribute__ ((packed)); |
144 | } __attribute__ ((packed)); |
| 141 | __u64 value; |
145 | __u64 value; |
| 142 | }; |
146 | }; |
| 143 | 147 | ||
| 144 | typedef union cr_itv cr_itv_t; |
148 | typedef union cr_itv cr_itv_t; |
| 145 | 149 | ||
| - | 150 | /** Interruption Status Register */ |
|
| - | 151 | union cr_isr { |
|
| - | 152 | struct { |
|
| - | 153 | union { |
|
| - | 154 | /** General Exception code field structuring. */ |
|
| - | 155 | struct { |
|
| - | 156 | unsigned ge_na : 4; |
|
| - | 157 | unsigned ge_code : 4; |
|
| - | 158 | } __attribute__ ((packed)); |
|
| - | 159 | __u16 code; |
|
| - | 160 | }; |
|
| - | 161 | __u8 vector; |
|
| - | 162 | unsigned : 8; |
|
| - | 163 | unsigned x : 1; /**< Execute exception. */ |
|
| - | 164 | unsigned w : 1; /**< Write exception. */ |
|
| - | 165 | unsigned r : 1; /**< Read exception. */ |
|
| - | 166 | unsigned na : 1; /**< Non-access exception. */ |
|
| - | 167 | unsigned sp : 1; /**< Speculative load exception. */ |
|
| - | 168 | unsigned rs : 1; /**< Register stack. */ |
|
| - | 169 | unsigned ir : 1; /**< Incomplete Register frame. */ |
|
| - | 170 | unsigned ni : 1; /**< Nested Interruption. */ |
|
| - | 171 | unsigned so : 1; /**< IA-32 Supervisor Override. */ |
|
| - | 172 | unsigned ei : 2; /**< Excepting Instruction. */ |
|
| - | 173 | unsigned ed : 1; /**< Exception Deferral. */ |
|
| - | 174 | unsigned : 20; |
|
| - | 175 | } __attribute__ ((packed)); |
|
| - | 176 | __u64 value; |
|
| - | 177 | }; |
|
| - | 178 | ||
| - | 179 | typedef union cr_isr cr_isr_t; |
|
| - | 180 | ||
| - | 181 | #endif /* !__ASM__ */ |
|
| - | 182 | ||
| 146 | #endif |
183 | #endif |
| 147 | 184 | ||