WebSVN – HelenOS – Diff – /SPARTAN/trunk/arch/ia32/src/smp/apic.c


/*
 * Copyright (C) 2001-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <mm/page.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
 
#ifdef __SMP__
 
/*
 * This is functional, far-from-general-enough interface to the APIC.
 * Advanced Programmable Interrupt Controller for MP systems.
 * Tested on:
 *  Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
 *  Simics 2.0.28
 *  ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
 */
 
/*
 * These variables either stay configured as initilalized, or are changed by
 * the MP configuration code.
 *
 * Pay special attention to the volatile keyword. Without it, gcc -O2 would
 * optimize the code too much and accesses to l_apic and io_apic, that must
 * always be 32-bit, would use byte oriented instructions.
 */
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
 
__u32 apic_id_mask = 0;
 
int apic_poll_errors(void);
 
void apic_init(void)
{
    __u32 tmp, id, i;
 
    trap_register(VECTOR_APIC_SPUR, apic_spurious);
 
    enable_irqs_function = io_apic_enable_irqs;
    disable_irqs_function = io_apic_disable_irqs;
    eoi_function = l_apic_eoi;
   
    /*
     * Configure interrupt routing.
     * IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
     * Other interrupts will be forwarded to the lowest priority CPU.
     */
    io_apic_disable_irqs(0xffff);
    trap_register(VECTOR_CLK, l_apic_timer_interrupt);
    for (i=1; i<16; i++) {
        int pin;
   
        if ((pin = mps_irq_to_pin(i)) != -1)
                io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
    }
   
 
    /*
     * Ensure that io_apic has unique ID.
     */
    tmp = io_apic_read(IOAPICID);
    id = (tmp >> 24) & 0xf;
    if ((1<<id) & apic_id_mask) {
        int i;
       
        for (i=0; i<15; i++) {
            if (!((1<<i) & apic_id_mask)) {
                io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) | (i<<24));
                break;
            }
        }
    }
 
    /*
     * Configure the BSP's lapic.
     */
    l_apic_init();
    l_apic_debug();
}
 
void apic_spurious(__u8 n, __u32 stack[])
{
    printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
 
int apic_poll_errors(void)
{
    __u32 esr;
   
    esr = l_apic[ESR] & ~ESRClear;
   
    if ((esr>>0) & 1)
        printf("Send CS Error\n");
    if ((esr>>1) & 1)
        printf("Receive CS Error\n");
    if ((esr>>2) & 1)
        printf("Send Accept Error\n");
    if ((esr>>3) & 1)
        printf("Receive Accept Error\n");
    if ((esr>>5) & 1)
        printf("Send Illegal Vector\n");
    if ((esr>>6) & 1)
        printf("Received Illegal Vector\n");
    if ((esr>>7) & 1)
        printf("Illegal Register Address\n");
   
    return !esr;
}
 
/*
 * Send all CPUs excluding CPU IPI vector.
 */
int l_apic_broadcast_custom_ipi(__u8 vector)
{
    __u32 lo;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
 
    lo |= DLVRMODE_FIXED | DESTMODE_LOGIC | LEVEL_ASSERT | SHORTHAND_EXCL | TRGRMODE_LEVEL | vector;
   
    l_apic[ICRlo] = lo;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    return apic_poll_errors();
}
 
/*
 * Universal Start-up Algorithm for bringing up the AP processors.
 */
int l_apic_send_init_ipi(__u8 apicid)
{
    __u32 lo, hi;
    int i;
 
    /*
     * Read the ICR register in and zero all non-reserved fields.
     */
    lo = l_apic[ICRlo] & ICRloClear;
    hi = l_apic[ICRhi] & ICRhiClear;
   
    lo |= DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
    hi |= apicid << 24;
   
    l_apic[ICRhi] = hi;
    l_apic[ICRlo] = lo;
 
    /*
     * According to MP Specification, 20us should be enough to
     * deliver the IPI.
     */
    delay(20);
 
    if (!apic_poll_errors()) return 0;
 
    lo = l_apic[ICRlo] & ICRloClear;
    if (lo & SEND_PENDING)
        printf("IPI is pending.\n");
 
    l_apic[ICRlo] = lo | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
 
    /*
     * Wait 10ms as MP Specification specifies.
     */
    delay(10000);
 
    if (!is_82489DX_apic(l_apic[LAVR])) {
        /*
         * If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
         */
        for (i = 0; i<2; i++) {
            lo = l_apic[ICRlo] & ICRloClear;
            lo |= ((__address) ap_boot) / 4096; /* calculate the reset vector */
            l_apic[ICRlo] = lo | DLVRMODE_STUP | DESTMODE_PHYS | LEVEL_ASSERT | SHORTHAND_DEST | TRGRMODE_LEVEL;
            delay(200);
        }
    }
   
   
    return apic_poll_errors();
}
 
void l_apic_init(void)
{
    __u32 tmp, t1, t2;
 
    l_apic[LVT_Err] |= (1<<16);
    l_apic[LVT_LINT0] |= (1<<16);
    l_apic[LVT_LINT1] |= (1<<16);
 
    tmp = l_apic[SVR] & SVRClear;
    l_apic[SVR] = tmp | (1<<8) | (VECTOR_APIC_SPUR);
 
    l_apic[TPR] &= TPRClear;
 
    if (CPU->arch.family >= 6)
        enable_l_apic_in_msr();
   
    tmp = l_apic[ICRlo] & ICRloClear;
    l_apic[ICRlo] = tmp | DLVRMODE_INIT | DESTMODE_PHYS | LEVEL_DEASSERT | SHORTHAND_INCL | TRGRMODE_LEVEL;
   
    /*
     * Program the timer for periodic mode and respective vector.
     */
 
    l_apic[TDCR] &= TDCRClear;
    l_apic[TDCR] |= 0xb;
    tmp = l_apic[LVT_Tm] | (1<<17) | (VECTOR_CLK);
    l_apic[LVT_Tm] = tmp & ~(1<<16);
 
    t1 = l_apic[CCRT];
    l_apic[ICRT] = 0xffffffff;
 
    while (l_apic[CCRT] == t1)
        ;
       
    t1 = l_apic[CCRT];
    delay(1000);
    t2 = l_apic[CCRT];
   
    l_apic[ICRT] = t1-t2;
   
}
 
void l_apic_eoi(void)
{
    l_apic[EOI] = 0;
}
 
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
    int i, lint;
 
    printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
 
    printf("LVT_Tm: ");
    if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');   
    if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Tm] & 0xff);
   
    for (i=0; i<2; i++) {
        lint = i ? LVT_LINT1 : LVT_LINT0;
        printf("LVT_LINT%d: ", i);
        if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
        printf("%d", l_apic[lint] & (1<<14)); putchar(',');
        printf("%d", l_apic[lint] & (1<<13)); putchar(',');
        if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
   
        switch ((l_apic[lint]>>8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[lint] & 0xff);   
    }
 
    printf("LVT_Err: ");
    if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
    if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
    printf("%B\n", l_apic[LVT_Err] & 0xff);
 
    /*
     * This register is supported only on P6 and higher.
     */
    if (CPU->arch.family > 5) {
        printf("LVT_PCINT: ");
        if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
        if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
        switch ((l_apic[LVT_PCINT] >> 8)&7) {
            case 0: printf("fixed"); break;
            case 4: printf("NMI"); break;
            case 7: printf("ExtINT"); break;
        }
        putchar(',');
        printf("%B\n", l_apic[LVT_PCINT] & 0xff);
    }
#endif
}
 
void l_apic_timer_interrupt(__u8 n, __u32 stack[])
{
    l_apic_eoi();
    clock();
}
 
__u8 l_apic_id(void)
{
    return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
}
 
__u32 io_apic_read(__u8 address)
{
    __u32 tmp;
   
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    return io_apic[IOWIN];
}
 
void io_apic_write(__u8 address, __u32 x)
{
    __u32 tmp;
 
    tmp = io_apic[IOREGSEL] & ~0xf;
    io_apic[IOREGSEL] = tmp | address;
    io_apic[IOWIN] = x;
}
 
void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
{
    __u32 reglo, reghi;
    int dlvr = 0;
   
    if (flags & LOPRI)
        dlvr = 1;
   
    reglo = io_apic_read(IOREDTBL + signal*2);
    reghi = io_apic_read(IOREDTBL + signal*2 + 1);
   
    reghi &= ~0x0f000000;
    reghi |= (dest<<24);
 
    reglo &= (~0x1ffff) | (1<<16); /* don't touch the mask */
    reglo |= (0<<15) | (0<<13) | (0<<11) | (dlvr<<8) | v;
 
    io_apic_write(IOREDTBL + signal*2, reglo);     
    io_apic_write(IOREDTBL + signal*2 + 1, reghi);
}
 
void io_apic_disable_irqs(__u16 irqmask)
{
    int i,pin;
    __u32 reglo;
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Mask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = mps_irq_to_pin(i);
            if (pin != -1) {
                reglo = io_apic_read(IOREDTBL + pin*2);
                reglo |= (1<<16);
                io_apic_write(IOREDTBL + pin*2,reglo);
            }
           
        }
    }
}
 
void io_apic_enable_irqs(__u16 irqmask)
{
    int i,pin;
    __u32 reglo;
   
    for (i=0;i<16;i++) {
        if ((irqmask>>i) & 1) {
            /*
             * Unmask the signal input in IO APIC if there is a
             * mapping for the respective IRQ number.
             */
            pin = mps_irq_to_pin(i);
            if (pin != -1) {
                reglo = io_apic_read(IOREDTBL + pin*2);
                reglo &= ~(1<<16);
                io_apic_write(IOREDTBL + pin*2,reglo);
            }
           
        }
    }
 
}
 
#endif /* __SMP__ */
 

Rev 112	Rev 115
1	/*	1	/*
2	* Copyright (C) 2001-2004 Jakub Jermar	2	* Copyright (C) 2001-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	#include <arch/types.h>	29	#include <arch/types.h>
30	#include <arch/smp/apic.h>	30	#include <arch/smp/apic.h>
31	#include <arch/smp/ap.h>	31	#include <arch/smp/ap.h>
32	#include <arch/smp/mps.h>	32	#include <arch/smp/mps.h>
33	#include <mm/page.h>	33	#include <mm/page.h>
34	#include <time/delay.h>	34	#include <time/delay.h>
35	#include <arch/interrupt.h>	35	#include <arch/interrupt.h>
36	#include <print.h>	36	#include <print.h>
37	#include <arch/asm.h>	37	#include <arch/asm.h>
38	#include <arch.h>	38	#include <arch.h>
39		39
40	#ifdef __SMP__	40	#ifdef __SMP__
41		41
42	/*	42	/*
43	* This is functional, far-from-general-enough interface to the APIC.	43	* This is functional, far-from-general-enough interface to the APIC.
44	* Advanced Programmable Interrupt Controller for MP systems.	44	* Advanced Programmable Interrupt Controller for MP systems.
45	* Tested on:	45	* Tested on:
46	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs	46	* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
-		47	* Simics 2.0.28
47	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs	48	* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
48	*/	49	*/
49		50
50	/*	51	/*
51	* These variables either stay configured as initilalized, or are changed by	52	* These variables either stay configured as initilalized, or are changed by
52	* the MP configuration code.	53	* the MP configuration code.
53	*	54	*
54	* Pay special attention to the volatile keyword. Without it, gcc -O2 would	55	* Pay special attention to the volatile keyword. Without it, gcc -O2 would
55	* optimize the code too much and accesses to l_apic and io_apic, that must	56	* optimize the code too much and accesses to l_apic and io_apic, that must
56	* always be 32-bit, would use byte oriented instructions.	57	* always be 32-bit, would use byte oriented instructions.
57	*/	58	*/
58	volatile __u32 l_apic = (__u32 ) 0xfee00000;	59	volatile __u32 l_apic = (__u32 ) 0xfee00000;
59	volatile __u32 io_apic = (__u32 ) 0xfec00000;	60	volatile __u32 io_apic = (__u32 ) 0xfec00000;
60		61
61	__u32 apic_id_mask = 0;	62	__u32 apic_id_mask = 0;
62		63
63	int apic_poll_errors(void);	64	int apic_poll_errors(void);
64		65
65	void apic_init(void)	66	void apic_init(void)
66	{	67	{
67	__u32 tmp, id, i;	68	__u32 tmp, id, i;
68		69
69	trap_register(VECTOR_APIC_SPUR, apic_spurious);	70	trap_register(VECTOR_APIC_SPUR, apic_spurious);
70		71
71	enable_irqs_function = io_apic_enable_irqs;	72	enable_irqs_function = io_apic_enable_irqs;
72	disable_irqs_function = io_apic_disable_irqs;	73	disable_irqs_function = io_apic_disable_irqs;
73	eoi_function = l_apic_eoi;	74	eoi_function = l_apic_eoi;
74		75
75	/*	76	/*
76	* Configure interrupt routing.	77	* Configure interrupt routing.
77	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.	78	* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
78	* Other interrupts will be forwarded to the lowest priority CPU.	79	* Other interrupts will be forwarded to the lowest priority CPU.
79	*/	80	*/
80	io_apic_disable_irqs(0xffff);	81	io_apic_disable_irqs(0xffff);
81	trap_register(VECTOR_CLK, l_apic_timer_interrupt);	82	trap_register(VECTOR_CLK, l_apic_timer_interrupt);
82	for (i=1; i<16; i++) {	83	for (i=1; i<16; i++) {
83	int pin;	84	int pin;
84		85
85	if ((pin = mps_irq_to_pin(i)) != -1)	86	if ((pin = mps_irq_to_pin(i)) != -1)
86	io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);	87	io_apic_change_ioredtbl(pin,0xf,IVT_IRQBASE+i,LOPRI);
87	}	88	}
88		89
89		90
90	/*	91	/*
91	* Ensure that io_apic has unique ID.	92	* Ensure that io_apic has unique ID.
92	*/	93	*/
93	tmp = io_apic_read(IOAPICID);	94	tmp = io_apic_read(IOAPICID);
94	id = (tmp >> 24) & 0xf;	95	id = (tmp >> 24) & 0xf;
95	if ((1<<id) & apic_id_mask) {	96	if ((1<<id) & apic_id_mask) {
96	int i;	97	int i;
97		98
98	for (i=0; i<15; i++) {	99	for (i=0; i<15; i++) {
99	if (!((1<<i) & apic_id_mask)) {	100	if (!((1<<i) & apic_id_mask)) {
100	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));	101	io_apic_write(IOAPICID, (tmp & (~(0xf<<24))) \| (i<<24));
101	break;	102	break;
102	}	103	}
103	}	104	}
104	}	105	}
105		106
106	/*	107	/*
107	* Configure the BSP's lapic.	108	* Configure the BSP's lapic.
108	*/	109	*/
109	l_apic_init();	110	l_apic_init();
110	l_apic_debug();	111	l_apic_debug();
111	}	112	}
112		113
113	void apic_spurious(__u8 n, __u32 stack[])	114	void apic_spurious(__u8 n, __u32 stack[])
114	{	115	{
115	printf("cpu%d: APIC spurious interrupt\n", CPU->id);	116	printf("cpu%d: APIC spurious interrupt\n", CPU->id);
116	}	117	}
117		118
118	int apic_poll_errors(void)	119	int apic_poll_errors(void)
119	{	120	{
120	__u32 esr;	121	__u32 esr;
121		122
122	esr = l_apic[ESR] & ~ESRClear;	123	esr = l_apic[ESR] & ~ESRClear;
123		124
124	if ((esr>>0) & 1)	125	if ((esr>>0) & 1)
125	printf("Send CS Error\n");	126	printf("Send CS Error\n");
126	if ((esr>>1) & 1)	127	if ((esr>>1) & 1)
127	printf("Receive CS Error\n");	128	printf("Receive CS Error\n");
128	if ((esr>>2) & 1)	129	if ((esr>>2) & 1)
129	printf("Send Accept Error\n");	130	printf("Send Accept Error\n");
130	if ((esr>>3) & 1)	131	if ((esr>>3) & 1)
131	printf("Receive Accept Error\n");	132	printf("Receive Accept Error\n");
132	if ((esr>>5) & 1)	133	if ((esr>>5) & 1)
133	printf("Send Illegal Vector\n");	134	printf("Send Illegal Vector\n");
134	if ((esr>>6) & 1)	135	if ((esr>>6) & 1)
135	printf("Received Illegal Vector\n");	136	printf("Received Illegal Vector\n");
136	if ((esr>>7) & 1)	137	if ((esr>>7) & 1)
137	printf("Illegal Register Address\n");	138	printf("Illegal Register Address\n");
138		139
139	return !esr;	140	return !esr;
140	}	141	}
141		142
142	/*	143	/*
143	* Send all CPUs excluding CPU IPI vector.	144	* Send all CPUs excluding CPU IPI vector.
144	*/	145	*/
145	int l_apic_broadcast_custom_ipi(__u8 vector)	146	int l_apic_broadcast_custom_ipi(__u8 vector)
146	{	147	{
147	__u32 lo;	148	__u32 lo;
148		149
149	/*	150	/*
150	* Read the ICR register in and zero all non-reserved fields.	151	* Read the ICR register in and zero all non-reserved fields.
151	*/	152	*/
152	lo = l_apic[ICRlo] & ICRloClear;	153	lo = l_apic[ICRlo] & ICRloClear;
153		154
154	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;	155	lo \|= DLVRMODE_FIXED \| DESTMODE_LOGIC \| LEVEL_ASSERT \| SHORTHAND_EXCL \| TRGRMODE_LEVEL \| vector;
155		156
156	l_apic[ICRlo] = lo;	157	l_apic[ICRlo] = lo;
157		158
158	lo = l_apic[ICRlo] & ICRloClear;	159	lo = l_apic[ICRlo] & ICRloClear;
159	if (lo & SEND_PENDING)	160	if (lo & SEND_PENDING)
160	printf("IPI is pending.\n");	161	printf("IPI is pending.\n");
161		162
162	return apic_poll_errors();	163	return apic_poll_errors();
163	}	164	}
164		165
165	/*	166	/*
166	* Universal Start-up Algorithm for bringing up the AP processors.	167	* Universal Start-up Algorithm for bringing up the AP processors.
167	*/	168	*/
168	int l_apic_send_init_ipi(__u8 apicid)	169	int l_apic_send_init_ipi(__u8 apicid)
169	{	170	{
170	__u32 lo, hi;	171	__u32 lo, hi;
171	int i;	172	int i;
172		173
173	/*	174	/*
174	* Read the ICR register in and zero all non-reserved fields.	175	* Read the ICR register in and zero all non-reserved fields.
175	*/	176	*/
176	lo = l_apic[ICRlo] & ICRloClear;	177	lo = l_apic[ICRlo] & ICRloClear;
177	hi = l_apic[ICRhi] & ICRhiClear;	178	hi = l_apic[ICRhi] & ICRhiClear;
178		179
179	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	180	lo \|= DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
180	hi \|= apicid << 24;	181	hi \|= apicid << 24;
181		182
182	l_apic[ICRhi] = hi;	183	l_apic[ICRhi] = hi;
183	l_apic[ICRlo] = lo;	184	l_apic[ICRlo] = lo;
184		185
185	/*	186	/*
186	* According to MP Specification, 20us should be enough to	187	* According to MP Specification, 20us should be enough to
187	* deliver the IPI.	188	* deliver the IPI.
188	*/	189	*/
189	delay(20);	190	delay(20);
190		191
191	if (!apic_poll_errors()) return 0;	192	if (!apic_poll_errors()) return 0;
192		193
193	lo = l_apic[ICRlo] & ICRloClear;	194	lo = l_apic[ICRlo] & ICRloClear;
194	if (lo & SEND_PENDING)	195	if (lo & SEND_PENDING)
195	printf("IPI is pending.\n");	196	printf("IPI is pending.\n");
196		197
197	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	198	l_apic[ICRlo] = lo \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
198		199
199	/*	200	/*
200	* Wait 10ms as MP Specification specifies.	201	* Wait 10ms as MP Specification specifies.
201	*/	202	*/
202	delay(10000);	203	delay(10000);
203		204
204	if (!is_82489DX_apic(l_apic[LAVR])) {	205	if (!is_82489DX_apic(l_apic[LAVR])) {
205	/*	206	/*
206	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.	207	* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
207	*/	208	*/
208	for (i = 0; i<2; i++) {	209	for (i = 0; i<2; i++) {
209	lo = l_apic[ICRlo] & ICRloClear;	210	lo = l_apic[ICRlo] & ICRloClear;
210	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */	211	lo \|= ((__address) ap_boot) / 4096; /* calculate the reset vector */
211	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;	212	l_apic[ICRlo] = lo \| DLVRMODE_STUP \| DESTMODE_PHYS \| LEVEL_ASSERT \| SHORTHAND_DEST \| TRGRMODE_LEVEL;
212	delay(200);	213	delay(200);
213	}	214	}
214	}	215	}
215		216
216		217
217	return apic_poll_errors();	218	return apic_poll_errors();
218	}	219	}
219		220
220	void l_apic_init(void)	221	void l_apic_init(void)
221	{	222	{
222	__u32 tmp, t1, t2;	223	__u32 tmp, t1, t2;
223		224
224	l_apic[LVT_Err] \|= (1<<16);	225	l_apic[LVT_Err] \|= (1<<16);
225	l_apic[LVT_LINT0] \|= (1<<16);	226	l_apic[LVT_LINT0] \|= (1<<16);
226	l_apic[LVT_LINT1] \|= (1<<16);	227	l_apic[LVT_LINT1] \|= (1<<16);
227		228
228	tmp = l_apic[SVR] & SVRClear;	229	tmp = l_apic[SVR] & SVRClear;
229	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);	230	l_apic[SVR] = tmp \| (1<<8) \| (VECTOR_APIC_SPUR);
230		231
231	l_apic[TPR] &= TPRClear;	232	l_apic[TPR] &= TPRClear;
232		233
233	if (CPU->arch.family >= 6)	234	if (CPU->arch.family >= 6)
234	enable_l_apic_in_msr();	235	enable_l_apic_in_msr();
235		236
236	tmp = l_apic[ICRlo] & ICRloClear;	237	tmp = l_apic[ICRlo] & ICRloClear;
237	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;	238	l_apic[ICRlo] = tmp \| DLVRMODE_INIT \| DESTMODE_PHYS \| LEVEL_DEASSERT \| SHORTHAND_INCL \| TRGRMODE_LEVEL;
238		239
239	/*	240	/*
240	* Program the timer for periodic mode and respective vector.	241	* Program the timer for periodic mode and respective vector.
241	*/	242	*/
242		243
243	l_apic[TDCR] &= TDCRClear;	244	l_apic[TDCR] &= TDCRClear;
244	l_apic[TDCR] \|= 0xb;	245	l_apic[TDCR] \|= 0xb;
245	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);	246	tmp = l_apic[LVT_Tm] \| (1<<17) \| (VECTOR_CLK);
246	l_apic[LVT_Tm] = tmp & ~(1<<16);	247	l_apic[LVT_Tm] = tmp & ~(1<<16);
247		248
248	t1 = l_apic[CCRT];	249	t1 = l_apic[CCRT];
249	l_apic[ICRT] = 0xffffffff;	250	l_apic[ICRT] = 0xffffffff;
250		251
251	while (l_apic[CCRT] == t1)	252	while (l_apic[CCRT] == t1)
252	;	253	;
253		254
254	t1 = l_apic[CCRT];	255	t1 = l_apic[CCRT];
255	delay(1000);	256	delay(1000);
256	t2 = l_apic[CCRT];	257	t2 = l_apic[CCRT];
257		258
258	l_apic[ICRT] = t1-t2;	259	l_apic[ICRT] = t1-t2;
259		260
260	}	261	}
261		262
262	void l_apic_eoi(void)	263	void l_apic_eoi(void)
263	{	264	{
264	l_apic[EOI] = 0;	265	l_apic[EOI] = 0;
265	}	266	}
266		267
267	void l_apic_debug(void)	268	void l_apic_debug(void)
268	{	269	{
269	#ifdef LAPIC_VERBOSE	270	#ifdef LAPIC_VERBOSE
270	int i, lint;	271	int i, lint;
271		272
272	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());	273	printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
273		274
274	printf("LVT_Tm: ");	275	printf("LVT_Tm: ");
275	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');	276	if (l_apic[LVT_Tm] & (1<<17)) printf("periodic"); else printf("one-shot"); putchar(',');
276	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	277	if (l_apic[LVT_Tm] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
277	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	278	if (l_apic[LVT_Tm] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
278	printf("%B\n", l_apic[LVT_Tm] & 0xff);	279	printf("%B\n", l_apic[LVT_Tm] & 0xff);
279		280
280	for (i=0; i<2; i++) {	281	for (i=0; i<2; i++) {
281	lint = i ? LVT_LINT1 : LVT_LINT0;	282	lint = i ? LVT_LINT1 : LVT_LINT0;
282	printf("LVT_LINT%d: ", i);	283	printf("LVT_LINT%d: ", i);
283	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	284	if (l_apic[lint] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
284	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');	285	if (l_apic[lint] & (1<<15)) printf("level"); else printf("edge"); putchar(',');
285	printf("%d", l_apic[lint] & (1<<14)); putchar(',');	286	printf("%d", l_apic[lint] & (1<<14)); putchar(',');
286	printf("%d", l_apic[lint] & (1<<13)); putchar(',');	287	printf("%d", l_apic[lint] & (1<<13)); putchar(',');
287	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	288	if (l_apic[lint] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
288		289
289	switch ((l_apic[lint]>>8)&7) {	290	switch ((l_apic[lint]>>8)&7) {
290	case 0: printf("fixed"); break;	291	case 0: printf("fixed"); break;
291	case 4: printf("NMI"); break;	292	case 4: printf("NMI"); break;
292	case 7: printf("ExtINT"); break;	293	case 7: printf("ExtINT"); break;
293	}	294	}
294	putchar(',');	295	putchar(',');
295	printf("%B\n", l_apic[lint] & 0xff);	296	printf("%B\n", l_apic[lint] & 0xff);
296	}	297	}
297		298
298	printf("LVT_Err: ");	299	printf("LVT_Err: ");
299	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	300	if (l_apic[LVT_Err] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
300	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	301	if (l_apic[LVT_Err] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
301	printf("%B\n", l_apic[LVT_Err] & 0xff);	302	printf("%B\n", l_apic[LVT_Err] & 0xff);
302		303
303	/*	304	/*
304	* This register is supported only on P6 and higher.	305	* This register is supported only on P6 and higher.
305	*/	306	*/
306	if (CPU->arch.family > 5) {	307	if (CPU->arch.family > 5) {
307	printf("LVT_PCINT: ");	308	printf("LVT_PCINT: ");
308	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');	309	if (l_apic[LVT_PCINT] & (1<<16)) printf("masked"); else printf("not masked"); putchar(',');
309	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');	310	if (l_apic[LVT_PCINT] & (1<<12)) printf("send pending"); else printf("idle"); putchar(',');
310	switch ((l_apic[LVT_PCINT] >> 8)&7) {	311	switch ((l_apic[LVT_PCINT] >> 8)&7) {
311	case 0: printf("fixed"); break;	312	case 0: printf("fixed"); break;
312	case 4: printf("NMI"); break;	313	case 4: printf("NMI"); break;
313	case 7: printf("ExtINT"); break;	314	case 7: printf("ExtINT"); break;
314	}	315	}
315	putchar(',');	316	putchar(',');
316	printf("%B\n", l_apic[LVT_PCINT] & 0xff);	317	printf("%B\n", l_apic[LVT_PCINT] & 0xff);
317	}	318	}
318	#endif	319	#endif
319	}	320	}
320		321
321	void l_apic_timer_interrupt(__u8 n, __u32 stack[])	322	void l_apic_timer_interrupt(__u8 n, __u32 stack[])
322	{	323	{
323	l_apic_eoi();	324	l_apic_eoi();
324	clock();	325	clock();
325	}	326	}
326		327
327	__u8 l_apic_id(void)	328	__u8 l_apic_id(void)
328	{	329	{
329	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;	330	return (l_apic[L_APIC_ID] >> L_APIC_IDShift)&L_APIC_IDMask;
330	}	331	}
331		332
332	__u32 io_apic_read(__u8 address)	333	__u32 io_apic_read(__u8 address)
333	{	334	{
334	__u32 tmp;	335	__u32 tmp;
335		336
336	tmp = io_apic[IOREGSEL] & ~0xf;	337	tmp = io_apic[IOREGSEL] & ~0xf;
337	io_apic[IOREGSEL] = tmp \| address;	338	io_apic[IOREGSEL] = tmp \| address;
338	return io_apic[IOWIN];	339	return io_apic[IOWIN];
339	}	340	}
340		341
341	void io_apic_write(__u8 address, __u32 x)	342	void io_apic_write(__u8 address, __u32 x)
342	{	343	{
343	__u32 tmp;	344	__u32 tmp;
344		345
345	tmp = io_apic[IOREGSEL] & ~0xf;	346	tmp = io_apic[IOREGSEL] & ~0xf;
346	io_apic[IOREGSEL] = tmp \| address;	347	io_apic[IOREGSEL] = tmp \| address;
347	io_apic[IOWIN] = x;	348	io_apic[IOWIN] = x;
348	}	349	}
349		350
350	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)	351	void io_apic_change_ioredtbl(int signal, int dest, __u8 v, int flags)
351	{	352	{
352	__u32 reglo, reghi;	353	__u32 reglo, reghi;
353	int dlvr = 0;	354	int dlvr = 0;
354		355
355	if (flags & LOPRI)	356	if (flags & LOPRI)
356	dlvr = 1;	357	dlvr = 1;
357		358
358	reglo = io_apic_read(IOREDTBL + signal*2);	359	reglo = io_apic_read(IOREDTBL + signal*2);
359	reghi = io_apic_read(IOREDTBL + signal*2 + 1);	360	reghi = io_apic_read(IOREDTBL + signal*2 + 1);
360		361
361	reghi &= ~0x0f000000;	362	reghi &= ~0x0f000000;
362	reghi \|= (dest<<24);	363	reghi \|= (dest<<24);
363		364
364	reglo &= (~0x1ffff) \| (1<<16); /* don't touch the mask */	365	reglo &= (~0x1ffff) \| (1<<16); /* don't touch the mask */
365	reglo \|= (0<<15) \| (0<<13) \| (0<<11) \| (dlvr<<8) \| v;	366	reglo \|= (0<<15) \| (0<<13) \| (0<<11) \| (dlvr<<8) \| v;
366		367
367	io_apic_write(IOREDTBL + signal*2, reglo);	368	io_apic_write(IOREDTBL + signal*2, reglo);
368	io_apic_write(IOREDTBL + signal*2 + 1, reghi);	369	io_apic_write(IOREDTBL + signal*2 + 1, reghi);
369	}	370	}
370		371
371	void io_apic_disable_irqs(__u16 irqmask)	372	void io_apic_disable_irqs(__u16 irqmask)
372	{	373	{
373	int i,pin;	374	int i,pin;
374	__u32 reglo;	375	__u32 reglo;
375		376
376	for (i=0;i<16;i++) {	377	for (i=0;i<16;i++) {
377	if ((irqmask>>i) & 1) {	378	if ((irqmask>>i) & 1) {
378	/*	379	/*
379	* Mask the signal input in IO APIC if there is a	380	* Mask the signal input in IO APIC if there is a
380	* mapping for the respective IRQ number.	381	* mapping for the respective IRQ number.
381	*/	382	*/
382	pin = mps_irq_to_pin(i);	383	pin = mps_irq_to_pin(i);
383	if (pin != -1) {	384	if (pin != -1) {
384	reglo = io_apic_read(IOREDTBL + pin*2);	385	reglo = io_apic_read(IOREDTBL + pin*2);
385	reglo \|= (1<<16);	386	reglo \|= (1<<16);
386	io_apic_write(IOREDTBL + pin*2,reglo);	387	io_apic_write(IOREDTBL + pin*2,reglo);
387	}	388	}
388		389
389	}	390	}
390	}	391	}
391	}	392	}
392		393
393	void io_apic_enable_irqs(__u16 irqmask)	394	void io_apic_enable_irqs(__u16 irqmask)
394	{	395	{
395	int i,pin;	396	int i,pin;
396	__u32 reglo;	397	__u32 reglo;
397		398
398	for (i=0;i<16;i++) {	399	for (i=0;i<16;i++) {
399	if ((irqmask>>i) & 1) {	400	if ((irqmask>>i) & 1) {
400	/*	401	/*
401	* Unmask the signal input in IO APIC if there is a	402	* Unmask the signal input in IO APIC if there is a
402	* mapping for the respective IRQ number.	403	* mapping for the respective IRQ number.
403	*/	404	*/
404	pin = mps_irq_to_pin(i);	405	pin = mps_irq_to_pin(i);
405	if (pin != -1) {	406	if (pin != -1) {
406	reglo = io_apic_read(IOREDTBL + pin*2);	407	reglo = io_apic_read(IOREDTBL + pin*2);
407	reglo &= ~(1<<16);	408	reglo &= ~(1<<16);
408	io_apic_write(IOREDTBL + pin*2,reglo);	409	io_apic_write(IOREDTBL + pin*2,reglo);
409	}	410	}
410		411
411	}	412	}
412	}	413	}
413		414
414	}	415	}
415		416
416	#endif /* __SMP__ */	417	#endif /* __SMP__ */
417		418

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(root)/SPARTAN/trunk/arch/ia32/src/smp/apic.c – Rev 112 → 115