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/*
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/*
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 * Copyright (C) 2001-2004 Jakub Jermar
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 * Copyright (C) 2001-2004 Jakub Jermar
-
 
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 * Copyright (C) 2005 Sergey Bondari
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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 *
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 *
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 * - Redistributions of source code must retain the above copyright
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 * - Redistributions of source code must retain the above copyright
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 *   notice, this list of conditions and the following disclaimer.
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 *   notice, this list of conditions and the following disclaimer.
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 * - Redistributions in binary form must reproduce the above copyright
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 * - Redistributions in binary form must reproduce the above copyright
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 *   notice, this list of conditions and the following disclaimer in the
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 *   notice, this list of conditions and the following disclaimer in the
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 *   documentation and/or other materials provided with the distribution.
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 *   documentation and/or other materials provided with the distribution.
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 * - The name of the author may not be used to endorse or promote products
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 * - The name of the author may not be used to endorse or promote products
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 *   derived from this software without specific prior written permission.
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 *   derived from this software without specific prior written permission.
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 *
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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 */
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#ifndef __ia32_ASM_H__
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#ifndef __ia32_ASM_H__
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#define __ia32_ASM_H__
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#define __ia32_ASM_H__
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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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extern __u32 interrupt_handler_size;
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extern __u32 interrupt_handler_size;
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extern void paging_on(void);
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extern void paging_on(void);
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extern void interrupt_handlers(void);
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extern void interrupt_handlers(void);
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extern void enable_l_apic_in_msr(void);
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extern void enable_l_apic_in_msr(void);
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void asm_delay_loop(__u32 t);
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void asm_delay_loop(__u32 t);
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void asm_fake_loop(__u32 t);
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void asm_fake_loop(__u32 t);
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/** Halt CPU
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/** Halt CPU
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 *
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 *
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 * Halt the current CPU until interrupt event.
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 * Halt the current CPU until interrupt event.
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 */
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 */
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_halt(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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static inline void cpu_sleep(void) { __asm__("hlt\n"); };
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/** Read CR2
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/** Read CR2
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 *
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 *
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 * Return value in CR2
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 * Return value in CR2
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 *
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 *
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 * @return Value read.
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 * @return Value read.
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 */
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 */
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static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
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static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0\n" : "=r" (v)); return v; }
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63
 
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/** Write CR3
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/** Write CR3
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 *
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 *
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 * Write value to CR3.
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 * Write value to CR3.
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 *
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 *
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 * @param v Value to be written.
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 * @param v Value to be written.
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 */
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 */
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static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
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static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
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/** Read CR3
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/** Read CR3
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 *
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 *
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 * Return value in CR3
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 * Return value in CR3
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 *
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 *
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 * @return Value read.
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 * @return Value read.
76
 */
77
 */
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static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
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static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0\n" : "=r" (v)); return v; }
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79
 
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/** Byte to port
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/** Byte to port
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 *
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 *
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 * Output byte to port
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 * Output byte to port
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 *
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 *
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 * @param port Port to write to
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 * @param port Port to write to
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 * @param val Value to write
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 * @param val Value to write
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 */
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 */
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static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
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88
 
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/** Word to port
89
/** Word to port
89
 *
90
 *
90
 * Output word to port
91
 * Output word to port
91
 *
92
 *
92
 * @param port Port to write to
93
 * @param port Port to write to
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 * @param val Value to write
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 * @param val Value to write
94
 */
95
 */
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static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
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97
 
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/** Double word to port
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/** Double word to port
98
 *
99
 *
99
 * Output double word to port
100
 * Output double word to port
100
 *
101
 *
101
 * @param port Port to write to
102
 * @param port Port to write to
102
 * @param val Value to write
103
 * @param val Value to write
103
 */
104
 */
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static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
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106
 
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/** Byte from port
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/** Byte from port
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 *
108
 *
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 * Get byte from port
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 * Get byte from port
109
 *
110
 *
110
 * @param port Port to read from
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 * @param port Port to read from
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 * @return Value read
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 * @return Value read
112
 */
113
 */
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static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
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115
 
115
/** Word from port
116
/** Word from port
116
 *
117
 *
117
 * Get word from port
118
 * Get word from port
118
 *
119
 *
119
 * @param port Port to read from
120
 * @param port Port to read from
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 * @return Value read
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 * @return Value read
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 */
122
 */
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static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
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124
 
124
/** Double word from port
125
/** Double word from port
125
 *
126
 *
126
 * Get double word from port
127
 * Get double word from port
127
 *
128
 *
128
 * @param port Port to read from
129
 * @param port Port to read from
129
 * @return Value read
130
 * @return Value read
130
 */
131
 */
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static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
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133
 
133
/** Set priority level low
134
/** Set priority level low
134
 *
135
 *
135
 * Enable interrupts and return previous
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 * Enable interrupts and return previous
136
 * value of EFLAGS.
137
 * value of EFLAGS.
137
 */
138
 */
138
static inline pri_t cpu_priority_low(void) {
139
static inline pri_t cpu_priority_low(void) {
139
    pri_t v;
140
    pri_t v;
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    __asm__ volatile (
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    __asm__ volatile (
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        "pushf\n\t"
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        "pushf\n\t"
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        "popl %0\n\t"
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        "popl %0\n\t"
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        "sti\n"
144
        "sti\n"
144
        : "=r" (v)
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        : "=r" (v)
145
    );
146
    );
146
    return v;
147
    return v;
147
}
148
}
148
 
149
 
149
/** Set priority level high
150
/** Set priority level high
150
 *
151
 *
151
 * Disable interrupts and return previous
152
 * Disable interrupts and return previous
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 * value of EFLAGS.
153
 * value of EFLAGS.
153
 */
154
 */
154
static inline pri_t cpu_priority_high(void) {
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static inline pri_t cpu_priority_high(void) {
155
    pri_t v;
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    pri_t v;
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    __asm__ volatile (
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    __asm__ volatile (
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        "pushf\n\t"
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        "pushf\n\t"
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        "popl %0\n\t"
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        "popl %0\n\t"
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        "cli\n"
160
        "cli\n"
160
        : "=r" (v)
161
        : "=r" (v)
161
    );
162
    );
162
    return v;
163
    return v;
163
}
164
}
164
 
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165
/** Restore priority level
166
/** Restore priority level
166
 *
167
 *
167
 * Restore EFLAGS.
168
 * Restore EFLAGS.
168
 */
169
 */
169
static inline void cpu_priority_restore(pri_t pri) {
170
static inline void cpu_priority_restore(pri_t pri) {
170
    __asm__ volatile (
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    __asm__ volatile (
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        "pushl %0\n\t"
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        "pushl %0\n\t"
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        "popf\n"
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        "popf\n"
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        : : "r" (pri)
174
        : : "r" (pri)
174
    );
175
    );
175
}
176
}
176
 
177
 
177
/** Return raw priority level
178
/** Return raw priority level
178
 *
179
 *
179
 * Return EFLAFS.
180
 * Return EFLAFS.
180
 */
181
 */
181
static inline pri_t cpu_priority_read(void) {
182
static inline pri_t cpu_priority_read(void) {
182
    pri_t v;
183
    pri_t v;
183
    __asm__ volatile (
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    __asm__ volatile (
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        "pushf\n\t"
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        "pushf\n\t"
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        "popl %0\n"
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        "popl %0\n"
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        : "=r" (v)
187
        : "=r" (v)
187
    );
188
    );
188
    return v;
189
    return v;
189
}
190
}
190
 
191
 
191
/** Return base address of current stack
192
/** Return base address of current stack
192
 *
193
 *
193
 * Return the base address of the current stack.
194
 * Return the base address of the current stack.
194
 * The stack is assumed to be STACK_SIZE bytes long.
195
 * The stack is assumed to be STACK_SIZE bytes long.
195
 * The stack must start on page boundary.
196
 * The stack must start on page boundary.
196
 */
197
 */
197
static inline __address get_stack_base(void)
198
static inline __address get_stack_base(void)
198
{
199
{
199
    __address v;
200
    __address v;
200
   
201
   
201
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
202
    __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
202
   
203
   
203
    return v;
204
    return v;
204
}
205
}
205
 
206
 
206
static inline __u64 rdtsc(void)
207
static inline __u64 rdtsc(void)
207
{
208
{
208
    __u64 v;
209
    __u64 v;
209
   
210
   
210
    __asm__ volatile("rdtsc\n" : "=A" (v));
211
    __asm__ volatile("rdtsc\n" : "=A" (v));
211
   
212
   
212
    return v;
213
    return v;
213
}
214
}
214
 
215
 
215
#endif
216
#endif
216
 
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