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1 | # |
1 | # |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
2 | # Copyright (C) 2005 Ondrej Palkovsky |
3 | # All rights reserved. |
3 | # All rights reserved. |
4 | # |
4 | # |
5 | # Redistribution and use in source and binary forms, with or without |
5 | # Redistribution and use in source and binary forms, with or without |
6 | # modification, are permitted provided that the following conditions |
6 | # modification, are permitted provided that the following conditions |
7 | # are met: |
7 | # are met: |
8 | # |
8 | # |
9 | # - Redistributions of source code must retain the above copyright |
9 | # - Redistributions of source code must retain the above copyright |
10 | # notice, this list of conditions and the following disclaimer. |
10 | # notice, this list of conditions and the following disclaimer. |
11 | # - Redistributions in binary form must reproduce the above copyright |
11 | # - Redistributions in binary form must reproduce the above copyright |
12 | # notice, this list of conditions and the following disclaimer in the |
12 | # notice, this list of conditions and the following disclaimer in the |
13 | # documentation and/or other materials provided with the distribution. |
13 | # documentation and/or other materials provided with the distribution. |
14 | # - The name of the author may not be used to endorse or promote products |
14 | # - The name of the author may not be used to endorse or promote products |
15 | # derived from this software without specific prior written permission. |
15 | # derived from this software without specific prior written permission. |
16 | # |
16 | # |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 | # |
27 | # |
28 | 28 | ||
29 | 29 | ||
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
30 | # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word |
31 | # and 1 means interrupt with error word |
31 | # and 1 means interrupt with error word |
32 | 32 | ||
33 | 33 | ||
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
34 | #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 |
35 | 35 | ||
36 | #define __ASM__ |
36 | #define __ASM__ |
37 | #include <arch/pm.h> |
37 | #include <arch/pm.h> |
38 | 38 | ||
39 | .text |
39 | .text |
40 | .global interrupt_handlers |
40 | .global interrupt_handlers |
41 | .global panic_printf |
41 | .global panic_printf |
42 | 42 | ||
43 | panic_printf: |
43 | panic_printf: |
44 | movq $halt, (%rsp) |
44 | movq $halt, (%rsp) |
45 | jmp printf |
45 | jmp printf |
46 | 46 | ||
47 | .global memcpy |
47 | .global memcpy |
48 | memcpy: |
48 | memcpy: |
49 | jmp _memcpy |
49 | jmp _memcpy |
50 | 50 | ||
51 | .global cpuid |
51 | .global cpuid |
52 | .global has_cpuid |
52 | .global has_cpuid |
53 | .global rdtsc |
53 | .global rdtsc |
54 | .global read_efer_flag |
54 | .global read_efer_flag |
55 | .global set_efer_flag |
55 | .global set_efer_flag |
56 | 56 | ||
57 | 57 | ||
58 | # THIS IS USERSPACE CODE |
58 | # THIS IS USERSPACE CODE |
59 | .global utext |
59 | .global utext |
60 | utext: |
60 | utext: |
61 | xor %ax,%ax; |
- | |
62 | mov %ax,%ds; |
- | |
63 | mov %ax,%es; |
- | |
64 | mov %ax,%fs; |
- | |
65 | mov %ax,%gs; |
- | |
66 | 0: |
61 | 0: |
67 | int $48 |
62 | int $48 |
68 | jmp 0b |
63 | jmp 0b |
69 | # not reached |
64 | # not reached |
70 | utext_end: |
65 | utext_end: |
71 | 66 | ||
72 | .data |
67 | .data |
73 | .global utext_size |
68 | .global utext_size |
74 | utext_size: |
69 | utext_size: |
75 | .long utext_end - utext |
70 | .long utext_end - utext |
76 | 71 | ||
77 | 72 | ||
78 | ## Determine CPUID support |
73 | ## Determine CPUID support |
79 | # |
74 | # |
80 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
75 | # Return 0 in EAX if CPUID is not support, 1 if supported. |
81 | # |
76 | # |
82 | has_cpuid: |
77 | has_cpuid: |
83 | pushq %rbx |
78 | pushq %rbx |
84 | 79 | ||
85 | pushfq # store flags |
80 | pushfq # store flags |
86 | popq %rax # read flags |
81 | popq %rax # read flags |
87 | movq %rax,%rbx # copy flags |
82 | movq %rax,%rbx # copy flags |
88 | btcl $21,%ebx # swap the ID bit |
83 | btcl $21,%ebx # swap the ID bit |
89 | pushq %rbx |
84 | pushq %rbx |
90 | popfq # propagate the change into flags |
85 | popfq # propagate the change into flags |
91 | pushfq |
86 | pushfq |
92 | popq %rbx # read flags |
87 | popq %rbx # read flags |
93 | andl $(1<<21),%eax # interested only in ID bit |
88 | andl $(1<<21),%eax # interested only in ID bit |
94 | andl $(1<<21),%ebx |
89 | andl $(1<<21),%ebx |
95 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
90 | xorl %ebx,%eax # 0 if not supported, 1 if supported |
96 | 91 | ||
97 | popq %rbx |
92 | popq %rbx |
98 | ret |
93 | ret |
99 | 94 | ||
100 | cpuid: |
95 | cpuid: |
101 | movq %rbx, %r10 # we have to preserve rbx across function calls |
96 | movq %rbx, %r10 # we have to preserve rbx across function calls |
102 | 97 | ||
103 | movl %edi,%eax # load the command into %eax |
98 | movl %edi,%eax # load the command into %eax |
104 | 99 | ||
105 | cpuid |
100 | cpuid |
106 | movl %eax,0(%rsi) |
101 | movl %eax,0(%rsi) |
107 | movl %ebx,4(%rsi) |
102 | movl %ebx,4(%rsi) |
108 | movl %ecx,8(%rsi) |
103 | movl %ecx,8(%rsi) |
109 | movl %edx,12(%rsi) |
104 | movl %edx,12(%rsi) |
110 | 105 | ||
111 | movq %r10, %rbx |
106 | movq %r10, %rbx |
112 | ret |
107 | ret |
113 | 108 | ||
114 | rdtsc: |
109 | rdtsc: |
115 | xorq %rax,%rax |
110 | xorq %rax,%rax |
116 | rdtsc |
111 | rdtsc |
117 | ret |
112 | ret |
118 | 113 | ||
119 | set_efer_flag: |
114 | set_efer_flag: |
120 | movq $0xc0000080, %rcx |
115 | movq $0xc0000080, %rcx |
121 | rdmsr |
116 | rdmsr |
122 | btsl %edi, %eax |
117 | btsl %edi, %eax |
123 | wrmsr |
118 | wrmsr |
124 | ret |
119 | ret |
125 | 120 | ||
126 | read_efer_flag: |
121 | read_efer_flag: |
127 | movq $0xc0000080, %rcx |
122 | movq $0xc0000080, %rcx |
128 | rdmsr |
123 | rdmsr |
129 | ret |
124 | ret |
130 | 125 | ||
131 | # Push all general purpose registers on stack except %rbp, %rsp |
126 | # Push all general purpose registers on stack except %rbp, %rsp |
132 | .macro push_all_gpr |
127 | .macro push_all_gpr |
133 | pushq %rax |
128 | pushq %rax |
134 | pushq %rbx |
129 | pushq %rbx |
135 | pushq %rcx |
130 | pushq %rcx |
136 | pushq %rdx |
131 | pushq %rdx |
137 | pushq %rsi |
132 | pushq %rsi |
138 | pushq %rdi |
133 | pushq %rdi |
139 | pushq %r8 |
134 | pushq %r8 |
140 | pushq %r9 |
135 | pushq %r9 |
141 | pushq %r10 |
136 | pushq %r10 |
142 | pushq %r11 |
137 | pushq %r11 |
143 | pushq %r12 |
138 | pushq %r12 |
144 | pushq %r13 |
139 | pushq %r13 |
145 | pushq %r14 |
140 | pushq %r14 |
146 | pushq %r15 |
141 | pushq %r15 |
147 | .endm |
142 | .endm |
148 | 143 | ||
149 | .macro pop_all_gpr |
144 | .macro pop_all_gpr |
150 | popq %r15 |
145 | popq %r15 |
151 | popq %r14 |
146 | popq %r14 |
152 | popq %r13 |
147 | popq %r13 |
153 | popq %r12 |
148 | popq %r12 |
154 | popq %r11 |
149 | popq %r11 |
155 | popq %r10 |
150 | popq %r10 |
156 | popq %r9 |
151 | popq %r9 |
157 | popq %r8 |
152 | popq %r8 |
158 | popq %rdi |
153 | popq %rdi |
159 | popq %rsi |
154 | popq %rsi |
160 | popq %rdx |
155 | popq %rdx |
161 | popq %rcx |
156 | popq %rcx |
162 | popq %rbx |
157 | popq %rbx |
163 | popq %rax |
158 | popq %rax |
164 | .endm |
159 | .endm |
165 | 160 | ||
166 | ## Declare interrupt handlers |
161 | ## Declare interrupt handlers |
167 | # |
162 | # |
168 | # Declare interrupt handlers for n interrupt |
163 | # Declare interrupt handlers for n interrupt |
169 | # vectors starting at vector i. |
164 | # vectors starting at vector i. |
170 | # |
165 | # |
171 | # The handlers setup data segment registers |
166 | # The handlers setup data segment registers |
172 | # and call trap_dispatcher(). |
167 | # and call trap_dispatcher(). |
173 | # |
168 | # |
174 | .macro handler i n |
169 | .macro handler i n |
175 | pushq %rbp |
170 | pushq %rbp |
176 | movq %rsp,%rbp |
171 | movq %rsp,%rbp |
177 | 172 | ||
178 | push_all_gpr |
173 | push_all_gpr |
179 | 174 | ||
180 | # trap_dispatcher(i, stack) |
- | |
181 | movq $(\i),%rdi # %rdi - first parameter |
175 | movq $(\i),%rdi # %rdi - first parameter |
182 | movq %rbp, %rsi |
176 | movq %rbp, %rsi |
183 | addq $8, %rsi # %rsi - second parameter - original stack |
177 | addq $8, %rsi # %rsi - second parameter - original stack |
184 | call trap_dispatcher |
178 | call trap_dispatcher # trap_dispatcher(i, stack) |
185 | 179 | ||
186 | # Test if this is interrupt with error word or not |
180 | # Test if this is interrupt with error word or not |
187 | mov $\i,%cl; |
181 | mov $\i,%cl; |
188 | movl $1,%eax; |
182 | movl $1,%eax; |
189 | test $0xe0,%cl; |
183 | test $0xe0,%cl; |
190 | jnz 0f; |
184 | jnz 0f; |
191 | and $0x1f,%cl; |
185 | and $0x1f,%cl; |
192 | shl %cl,%eax; |
186 | shl %cl,%eax; |
193 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
187 | and $ERROR_WORD_INTERRUPT_LIST,%eax; |
194 | jz 0f; |
188 | jz 0f; |
195 | 189 | ||
196 | 190 | ||
197 | # Return with error word |
191 | # Return with error word |
198 | pop_all_gpr |
192 | pop_all_gpr |
199 | 193 | ||
200 | popq %rbp; |
194 | popq %rbp; |
201 | add $8,%esp; # Skip error word |
195 | add $8,%esp; # Skip error word |
202 | iretq |
196 | iretq |
203 | 197 | ||
204 | 0: |
198 | 0: |
205 | # Return with no error word |
199 | # Return with no error word |
206 | pop_all_gpr |
200 | pop_all_gpr |
207 | 201 | ||
208 | popq %rbp |
202 | popq %rbp |
209 | iretq |
203 | iretq |
210 | 204 | ||
211 | .if (\n-\i)-1 |
205 | .if (\n-\i)-1 |
212 | handler "(\i+1)",\n |
206 | handler "(\i+1)",\n |
213 | .endif |
207 | .endif |
214 | .endm |
208 | .endm |
215 | 209 | ||
216 | interrupt_handlers: |
210 | interrupt_handlers: |
217 | h_start: |
211 | h_start: |
218 | handler 0 IDT_ITEMS |
212 | handler 0 IDT_ITEMS |
219 | # handler 64 128 |
- | |
220 | # handler 128 192 |
- | |
221 | # handler 192 256 |
- | |
222 | h_end: |
213 | h_end: |
223 | 214 | ||
224 | 215 | ||
225 | .data |
216 | .data |
226 | .global interrupt_handler_size |
217 | .global interrupt_handler_size |
227 | 218 | ||
228 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
219 | interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS |
229 | 220 |